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2011-11-10ENGR00161487: Fix SD/USB/FEC performance issue.er3-previewRanjani Vaidyanathan
When WAIT mode is not enabled, execute cpu_do_idle() code. Currently WAIT mode requires the code to be run from IRAM with caches disabled. No L2 cache access should be done for a specified period after the system exits WAIT mode. This delay and running code from IRAM adversely affects the SDHC performance. Hardware team is looking into the extended delay that is required. Till its root caused, default should be to execute cpu_do_idle() and disable entry into WAIT mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00161484 Add HDMI audio support on MX6 Sabre-liteMahesh Mahadevan
Add support for HDMI audio on MX6 Sabre-lite Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
2011-11-10ENGR00161474 [mx6q] Fix build break in imx6_updater_defconfigNancy Chen
Turn on Anatop regulator. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00161447-2 ARM2: fix section missmach warningFrank Li
fix section mismatch warning Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-11-10ENGR00161447-1 v4l2: fix section missmach warningFrank Li
fix section mismatch warning Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-11-10ENGR00161444 V4L2: Fix v4l2 capture build errorFrank Li
Fix v4l2 build error. revert mxc_v4l2.h to 01c98ebc63d Signed-off-by: Frank Li <Frank.Li@freescale.com>
2011-11-10ENGR00159982 - [MX6Q]: Add FEC phy save power function.Fugang Duan
- Set Phy AR8031 to saving power mode while no cable connect. Signed-off-by: Fugang Duan <B38611@freescale.com>
2011-11-10ENGR00159982 - FEC: low power mode when FEC is no use.Fugang Duan
- Set phy AR8031 to save power mode when no cable connect. - Close enet clock gate when FEC is no use. Signed-off-by: Fugang Duan <B38611@freescale.com>
2011-11-10ENGR00161256 mx6q: remove CAN_DEBUG by default in defconfigDong Aisheng
Do not show debug messages by default.
2011-11-10ENGR00161382-4 MX6Q MIPI CSI2: enable MIPI CSI2Even Xu
1. enable MIPI CSI2 driver 2. change v4l2 cowork with mipi csi2 3. enable ov5640 mipi mode Signed-off-by: Even Xu <b21019@freescale.com>
2011-11-10ENGR00161382-3 MX6Q MIPI CSI2: Add MIPI CSI2 driverEven Xu
Add MIPI CSI2 driver Signed-off-by: Even Xu <b21019@freescale.com>
2011-11-10ENGR00161382-2 MX6Q MIPI CSI2: initialize platform dataEven Xu
Initialize MIPI CSI2 platform data Signed-off-by: Even Xu <b21019@freescale.com>
2011-11-10ENGR00161382-1 MX6Q MIPI CSI2: Add platform dataEven Xu
Add MIPI csi2 platform data Signed-off-by: Even Xu <b21019@freescale.com>
2011-11-10ENGR00161383 [MX6Q] USB OTG: enable OTG drivermake shi
Enable OTG driver on mx6q board Signed-off-by: make shi <b15407@freescale.com>
2011-11-10ENGR00161383 [MX6Q] USB OTG: enable OTG drivermake shi
Enable OTG driver on mx6q board Signed-off-by: make shi <b15407@freescale.com>
2011-11-10ENGR00158360 imx MSL: fix __arch_adjust_zones functionJason Chen
fix __arch_adjust_zones if MXC_DMA_ZONE_SIZE if bigger than system memory Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160878-2 mxc v4l2 output: new mxc v4l2 output driver based on videobufJason Chen
This new v4l2 output driver is based on videobuf, using dma contig alloc method. It creates video dev node for each display framebuffer begin from /dev/video16 by default. If need post-processing, this driver will do it by ipu pp driver which support: - resizing - CSC - rotate - deinterlacing If no need post-processing, the IPU IC will be bypassed as old driver, the buf will be set to fb buffer directly by crack fb smem_start. The user should do setting before streamon like below: 1. set output crop 2. set ctrl like rotate/vflip/hflip/deinterlacing motion 3. set fmt 4. reqbuf The new features compare to old driver: - support multi-instance - support user point buffer - runtime suspend/resume For suspend/resume, still has chance to meet issue on mx6q, will fix later. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160878-1 mxc v4l2 output: new mxc v4l2 output driver based on videobufJason Chen
This new v4l2 output driver is based on videobuf, using dma contig alloc method. It creates video dev node for each display framebuffer begin from /dev/video16 by default. If need post-processing, this driver will do it by ipu pp driver which support: - resizing - CSC - rotate - deinterlacing If no need post-processing, the IPU IC will be bypassed as old driver, the buf will be set to fb buffer directly by crack fb smem_start. The user should do setting before streamon like below: 1. set output crop 2. set ctrl like rotate/vflip/hflip/deinterlacing motion 3. set fmt 4. reqbuf The new features compare to old driver: - support multi-instance - support user point buffer - runtime suspend/resume For suspend/resume, still has chance to meet issue on mx6q, will fix later. This patch for head file. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160877 ipuv3: pm method changeJason Chen
1. use late suspend early resume 2. disable/enable clk when suspend/resume with clk on. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160876 videobuf: add timestamp for user point bufferJason Chen
1. add timestamp for userpoint buffer 2. use pgprot_writecombine for mmap Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160875-3 ipuv3 dev: low performance if enable rotationJason Chen
1. no dma alloc for rot buf every time which will cost time. 2. fix split mode condition. 3. export some functions. This patch for driver file. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160875-2 ipuv3 dev: low performance if enable rotationJason Chen
1. no dma alloc for rot buf every time which will cost time. 2. fix split mode condition. 3. export some functions. This patch for MSL file. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00160875-1 ipuv3 dev: low performance if enable rotationJason Chen
1. no dma alloc for rot buf every time which will cost time. 2. fix split mode condition. 3. export some functions. This patch for common head file. Signed-off-by: Jason Chen <b02280@freescale.com>
2011-11-10ENGR00161314-3 mx6q usb-host: add hsic supportPeter Chen
Header file Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-11-10ENGR00161314-2 mx6q usb-host: add hsic supportPeter Chen
Device part Add HSIC run and HSIC phy's definition Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-11-10ENGR00161314-1 mx6q usb-host: add hsic supportPeter Chen
MSL part Add HSIC support for Host2 and Host3, for HSIC mode, there is not usb phy needed, the usb device is always at the board - Validation hardware: iMX6Q Validation Port Card and Re-worked Rev X3 board, for hardware rework detail, contact Ken Sun (b03826) - Validation device: HSIC interface SMSC HUB(USB4640) and Host 3. Host 2 is coding finishes, but not verified due to hardware limitation. - Pin Conflict with Ethernet, order to use HSIC, the user need disable ethernet function at both u-boot and linux kernel. For u-boot: please undefine CONFIG_MXC_FEC at your board config file For kernel: please define CONFIG_USB_EHCI_ARC_HSIC, the entry is: Device Drivers---> USB support---> Support HSIC Host controller for Freescale SoC - Suspend/resume and wakeup are not supported due to IC issues, these IC issues will be fixed at TO1.1 for i.mx6, software will add these support after receiving TO1.1 chip. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2011-11-10ENGR00161215-2 vpu: Add ioctls for querying and setting bitwork memorySammy He
Add VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM ioctls implementation for registerring bitwork memory allocated from user space to vpu driver. Signed-off-by: Sammy He <r62914@freescale.com>
2011-11-10ENGR00161215-1 arch/arm: Add two new IOCTLs in mxc_vpu.hSammy He
Add IOCTL VPU_IOC_QUERY_BITWORK_MEM and VPU_IOC_SET_BITWORK_MEM for vpu driver. The two ioctls can be used when user allocates working buffer from user space, for exmaple, allocating it from pmem interface on android, then register it to vpu driver. Signed-off-by: Sammy He <r62914@freescale.com>
2011-11-10ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_areaWill Deacon
commit a248b13b21ae00b97638b4f435c8df3075808b5d upstream. The v6 and v7 implementations of flush_kern_dcache_area do not align the passed MVA to the size of a cacheline in the data cache. If a misaligned address is used, only a subset of the requested area will be flushed. This has been observed to cause failures in SMP boot where the secondary_data initialised by the primary CPU is not cacheline aligned, causing the secondary CPUs to read incorrect values for their pgd and stack pointers. This patch ensures that the base address is cacheline aligned before flushing the d-cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit f311af550d6d24b03c1c911572192bc95fe58404)
2011-11-10Fix memory leak in cpufreq_statsteven finney
commit 98586ed8b8878e10691203687e89a42fa3355300 upstream. When a CPU is taken offline in an SMP system, cpufreq_remove_dev() nulls out the per-cpu policy before cpufreq_stats_free_table() can make use of it. cpufreq_stats_free_table() then skips the call to sysfs_remove_group(), leaving about 100 bytes of sysfs-related memory unclaimed each time a CPU-removal occurs. Break up cpu_stats_free_table into sysfs and table portions, and call the sysfs portion early. Signed-off-by: Steven Finney <steven.finney@palm.com> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit a5ba67df5b332a1e9bd73f6954285a3284f86e71)
2011-11-10CPU hotplug, re-create sysfs directory and symlinksJacob Shin
commit 27ecddc2a9f99ce4ac9a59a0acd77f7100b6d034 upstream. When we discover CPUs that are affected by each other's frequency/voltage transitions, the first CPU gets a sysfs directory created, and rest of the siblings get symlinks. Currently, when we hotplug off only the first CPU, all of the symlinks and the sysfs directory gets removed. Even though rest of the siblings are still online and functional, they are orphaned, and no longer governed by cpufreq. This patch, given the above scenario, creates a sysfs directory for the first sibling and symlinks for the rest of the siblings. Please note the recursive call, it was rather too ugly to roll it out. And the removal of redundant NULL setting (it is already taken care of near the top of the function). Signed-off-by: Jacob Shin <jacob.shin@amd.com> Acked-by: Mark Langsdorf <mark.langsdorf@amd.com> Reviewed-by: Thomas Renninger <trenn@suse.de> Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit 15ae4738537b75bb8f9ba737bcb18c8cb0cb1e07)
2011-11-10ARM: zImage: make sure the stack is 64-bit alignedNicolas Pitre
commit 3bd2cbb95543acf44fe123eb9f038de54e655eb4 upstream. With ARMv5+ and EABI, the compiler expects a 64-bit aligned stack so instructions like STRD and LDRD can be used. Without this, mysterious boot failures were seen semi randomly with the LZMA decompressor. While at it, let's align .bss as well. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit 1da3e2d35573b23ae38aa0f1b096cb978ecef445)
2011-11-10serial/imx: read cts state only after acking cts change irqUwe Kleine-König
commit 5680e94148a86e8c31fdc5cb0ea0d5c6810c05b0 upstream. If cts changes between reading the level at the cts input (USR1_RTSS) and acking the irq (USR1_RTSD) the last edge doesn't generate an irq and uart_handle_cts_change is called with a outdated value for cts. The race was introduced by commit ceca629 ([ARM] 2971/1: i.MX uart handle rts irq) Reported-by: Arwed Springer <Arwed.Springer@de.trumpf.com> Tested-by: Arwed Springer <Arwed.Springer@de.trumpf.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit 1eb710f4e01a9afab735828c87ef13e2e6b57386)
2011-11-10ARM: 6864/1: hw_breakpoint: clear DBGVCR out of resetWill Deacon
commit e89c0d7090c54d7b11b9b091e495a1ae345dd3ff upstream. The DBGVCR, used for configuring vector catch debug events, is UNKNOWN out of reset on ARMv7. When enabling monitor mode, this must be zeroed to avoid UNPREDICTABLE behaviour. This patch adds the zeroing code to the debug reset path. Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit c421122f3dea5b5c42133f67a8084e6c0793a35c)
2011-11-10ASoC: imx: fix burstsize for DMAWolfram Sang
commit e1bb31b444668bc957c337d33803db7cb3330745 upstream. SSI counts in words, the DMA engine in bytes. (Wrong) factor got removed in bf974a0 (ASoC i.MX: switch to new DMA api). Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit e34910dd0fcf32e9a0e5ff6f3249910cff4c06d8)
2011-11-10ASoC: imx: set watermarks for mx2-dmaWolfram Sang
commit 2c4cf17a52f04fbe929977252d5b8ab81d2c6e9b upstream. They got accidently removed by f0fba2a (ASoC: multi-component - ASoC Multi-Component Support). Reintroduce them and get rid of the superfluous defines because the fiq-driver has its own hardcoded values. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit ad5d054f79f20dfaecf23322783e652eee303d98)
2011-11-10smp_call_function_many: handle concurrent clearing of maskMilton Miller
commit 723aae25d5cdb09962901d36d526b44d4be1051c upstream. Mike Galbraith reported finding a lockup ("perma-spin bug") where the cpumask passed to smp_call_function_many was cleared by other cpu(s) while a cpu was preparing its call_data block, resulting in no cpu to clear the last ref and unlock the block. Having cpus clear their bit asynchronously could be useful on a mask of cpus that might have a translation context, or cpus that need a push to complete an rcu window. Instead of adding a BUG_ON and requiring yet another cpumask copy, just detect the race and handle it. Note: arch_send_call_function_ipi_mask must still handle an empty cpumask because the data block is globally visible before the that arch callback is made. And (obviously) there are no guarantees to which cpus are notified if the mask is changed during the call; only cpus that were online and had their mask bit set during the whole call are guaranteed to be called. Reported-by: Mike Galbraith <efault@gmx.de> Reported-by: Jan Beulich <JBeulich@novell.com> Acked-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit d1342fed517f89ad4c3d956d9e214d72c06bb7c1)
2011-11-10call_function_many: add missing orderingMilton Miller
commit 45a5791920ae643eafc02e2eedef1a58e341b736 upstream. Paul McKenney's review pointed out two problems with the barriers in the 2.6.38 update to the smp call function many code. First, a barrier that would force the func and info members of data to be visible before their consumption in the interrupt handler was missing. This can be solved by adding a smp_wmb between setting the func and info members and setting setting the cpumask; this will pair with the existing and required smp_rmb ordering the cpumask read before the read of refs. This placement avoids the need a second smp_rmb in the interrupt handler which would be executed on each of the N cpus executing the call request. (I was thinking this barrier was present but was not). Second, the previous write to refs (establishing the zero that we the interrupt handler was testing from all cpus) was performed by a third party cpu. This would invoke transitivity which, as a recient or concurrent addition to memory-barriers.txt now explicitly states, would require a full smp_mb(). However, we know the cpumask will only be set by one cpu (the data owner) and any preivous iteration of the mask would have cleared by the reading cpu. By redundantly writing refs to 0 on the owning cpu before the smp_wmb, the write to refs will follow the same path as the writes that set the cpumask, which in turn allows us to keep the barrier in the interrupt handler a smp_rmb instead of promoting it to a smp_mb (which will be be executed by N cpus for each of the possible M elements on the list). I moved and expanded the comment about our (ab)use of the rcu list primitives for the concurrent walk earlier into this function. I considered moving the first two paragraphs to the queue list head and lock, but felt it would have been too disconected from the code. Cc: Paul McKinney <paulmck@linux.vnet.ibm.com> Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit 4718af584c9db2b2002a89b856462cedaaf3d7da)
2011-11-10call_function_many: fix list delete vs add raceMilton Miller
commit e6cd1e07a185d5f9b0aa75e020df02d3c1c44940 upstream. Peter pointed out there was nothing preventing the list_del_rcu in smp_call_function_interrupt from running before the list_add_rcu in smp_call_function_many. Fix this by not setting refs until we have gotten the lock for the list. Take advantage of the wmb in list_add_rcu to save an explicit additional one. I tried to force this race with a udelay before the lock & list_add and by mixing all 64 online cpus with just 3 random cpus in the mask, but was unsuccessful. Still, inspection shows a valid race, and the fix is a extension of the existing protection window in the current code. Reported-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit cb8385e61fb736ef6748d305d868b28a9f649ef1)
2011-11-10ENGR00161285 [MX6Q ARM2] make spdif and i2c3 mutually exclusiveAlan Tull
Both S/PDIF in and I2C3 SDA use GPIO_16, so only one can be enabled at a time. Add early param "spdif_in" to enable S/PDIF in. Default is to enable I2C3 and leave S/PDIF in disabled. Signed-off-by: Alan Tull <alan.tull@freescale.com>
2011-11-10ENGR00161256-2 mx6q arm2: add flexcan supportDong Aisheng
Add flexcan support. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2011-11-10ENGR00161256-1 flexcan: convert driver to use platform idsDong Aisheng
Using platform ids to handle differences between different SoCs. The default rx fifo global mask register, newly introduced in mx6q, is 0xffffffff and the reset value in Message buffers(can be reused as the memory of rx fifo filter table) is none zero, it will wrongly cause the can to be unable to recevie packets due to filter. We need to clear it to make sure to receive all packets. Signed-off-by: Dong Aisheng <b29396@freescale.com>
2011-11-10ENGR00161321 [MX6 ARM2]Disable Warm resetAnson Huang
Current warm reset is not working with MMDC_CH1 bypass bit set, now we disable warm reset to workaround it for the coming release. Then, wdog reset will be cold reset. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00161312 - FEC: fix build warningFugang Duan
fix build warning: > drivers/net/fec.c:435: warning: unused variable 'estatus' Signed-off-by: Fugang Duan <B38611@freescale.com>
2011-11-10ENGR00161300 MXC V4L2 capture: fix build warningYuxi
fix build warning: > drivers/media/video/mxc/capture/mxc_v4l2_capture.c:2457: warning: > comparison between pointer and integer Signed-off-by: Yuxi Sun <b36102@freescale.com>
2011-11-10ENGR00161234-2: Enable ocotp clock for mx6qTerry Lv
Add clock enable code to arch. OCOTP driver missed code to enable clock in driver. Thus if ocotp clock is not enabled in clock.c, ocotp will not work. We will remove ocotp clock enable code in board file and leave this operation to driver. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-11-10ENGR00161234-1: Enable ocotp clock for mx6qTerry Lv
Add clock enable code to driver. OCOTP driver missed code to enable clock in driver. Thus if ocotp clock is not enabled in clock.c, ocotp will not work. Signed-off-by: Terry Lv <r65388@freescale.com>
2011-11-10ENGR00161301 Upgrade to 4.6.2Richard Zhao
Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Lily Zhang
2011-11-10ENGR00161292 [mx6q] Fix incompatible pointer warningsNancy Chen
Fix build warnings regarding initialization from incompatible pointer type. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2011-11-10ENGR00161288 balance spdif clock enables and disablesAlan Tull
Add tx_active, rx_active flags to keep track of what channels have enabled clocks. In suspend/resume, only disable/re-enable the clocks that were enabled. Signed-off-by: Alan Tull <alan.tull@freescale.com>