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-rw-r--r--arch/blackfin/mach-bf561/secondary.S35
1 files changed, 15 insertions, 20 deletions
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4624eebbf9c..4c462838f4e 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -13,7 +13,11 @@
#include <asm/asm-offsets.h>
#include <asm/trace.h>
-__INIT
+/*
+ * This code must come first as CoreB is hardcoded (in hardware)
+ * to start at the beginning of its L1 instruction memory.
+ */
+.section .l1.text.head
/* Lay the initial stack into the L1 scratch area of Core B */
#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
@@ -160,43 +164,34 @@ ENTRY(_coreb_trampoline_start)
.LWAIT_HERE:
jump .LWAIT_HERE;
ENDPROC(_coreb_trampoline_start)
-ENTRY(_coreb_trampoline_end)
+#ifdef CONFIG_HOTPLUG_CPU
.section ".text"
-ENTRY(_set_sicb_iwr)
- P0.H = hi(SICB_IWR0);
- P0.L = lo(SICB_IWR0);
- P1.H = hi(SICB_IWR1);
- P1.L = lo(SICB_IWR1);
- [P0] = R0;
- [P1] = R1;
- SSYNC;
- RTS;
-ENDPROC(_set_sicb_iwr)
-
-ENTRY(_coreb_sleep)
+ENTRY(_coreb_die)
sp.l = lo(INITIAL_STACK);
sp.h = hi(INITIAL_STACK);
fp = sp;
usp = sp;
- call _set_sicb_iwr;
-
CLI R2;
SSYNC;
IDLE;
STI R2;
R0 = IWR_DISABLE_ALL;
- R1 = IWR_DISABLE_ALL;
- call _set_sicb_iwr;
+ P0.H = hi(SYSMMR_BASE);
+ P0.L = lo(SYSMMR_BASE);
+ [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
+ [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
+ SSYNC;
p0.h = hi(COREB_L1_CODE_START);
p0.l = lo(COREB_L1_CODE_START);
jump (p0);
-ENDPROC(_coreb_sleep)
+ENDPROC(_coreb_die)
+#endif
-__CPUINIT
+__INIT
ENTRY(_coreb_start)
[--sp] = reti;