diff options
Diffstat (limited to 'arch/arm/mach-stmp378x/include/mach')
37 files changed, 0 insertions, 2775 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S deleted file mode 100644 index 731a92286da..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP378X - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT - cmp \irqnr, #0x7f - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h deleted file mode 100644 index cc59673becd..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/irqs.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Freescale STMP378X interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_BCH 56 -#define IRQ_PXP 57 -#define IRQ_UARTAPP2_TX_DMA 58 -#define IRQ_UARTAPP2_INTERNAL 59 -#define IRQ_UARTAPP2_RX_DMA 60 -#define IRQ_VDAC_DETECT 61 -#define IRQ_VDD5V_DROOP 64 -#define IRQ_DCDC4P2_BO 65 - - -#define NR_REAL_IRQS 128 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* All interrupts are FIQ capable */ -#define FIQ_START IRQ_DEBUG_UART - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h deleted file mode 100644 index 93f952d3596..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/pins.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale STMP378X SoC pin multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) -#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) -#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) -#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) -#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) -#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) -#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) -#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) -#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) -#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) -#define PINID_LCD_RS STMP3XXX_PINID(1, 19) -#define PINID_LCD_WR STMP3XXX_PINID(1, 20) -#define PINID_LCD_CS STMP3XXX_PINID(1, 21) -#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) -#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) -#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) -#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) -#define PINID_PWM0 STMP3XXX_PINID(1, 26) -#define PINID_PWM1 STMP3XXX_PINID(1, 27) -#define PINID_PWM2 STMP3XXX_PINID(1, 28) -#define PINID_PWM3 STMP3XXX_PINID(1, 29) -#define PINID_PWM4 STMP3XXX_PINID(1, 30) - -/* Bank 2 */ -#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) -#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) -#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) -#define PINID_ROTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) -#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) -#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) -#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) -#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h deleted file mode 100644 index dbcf85b6ac2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp378x: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) -#define REGS_APBH_PHYS 0x80004000 -#define REGS_APBH_SIZE 0x2000 - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_CTRL2 0x20 - -#define HW_APBH_DEVSEL 0x30 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBH_CHn_CMD_COMMAND 0x00000003 -#define BP_APBH_CHn_CMD_COMMAND 0 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h deleted file mode 100644 index 3b934a4d27f..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * stmp378x: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#define REGS_APBX_PHYS 0x80024000 -#define REGS_APBX_SIZE 0x2000 - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_CTRL2 0x20 - -#define HW_APBX_CHANNEL_CTRL 0x30 -#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 -#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 - -#define HW_APBX_DEVSEL 0x40 - -#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x110 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x130 - -#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x140 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif - diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h deleted file mode 100644 index 641ac6126f8..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) -#define REGS_AUDIOIN_PHYS 0x8004C000 -#define REGS_AUDIOIN_SIZE 0x2000 - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h deleted file mode 100644 index f533e23694a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * stmp378x: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) -#define REGS_AUDIOOUT_PHYS 0x80048000 -#define REGS_AUDIOOUT_SIZE 0x2000 - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_SPEAKERCTRL 0x100 -#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h deleted file mode 100644 index 532d2465071..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp378x: BCH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000) -#define REGS_BCH_PHYS 0x8000A000 -#define REGS_BCH_SIZE 0x2000 - -#define HW_BCH_CTRL 0x0 -#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_BCH_CTRL_COMPLETE_IRQ 0 -#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 - -#define HW_BCH_STATUS0 0x10 -#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_BCH_STATUS0_CORRECTED 0x00000008 -#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 -#define BP_BCH_STATUS0_STATUS_BLK0 8 -#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_BCH_STATUS0_COMPLETED_CE 16 - -#define HW_BCH_LAYOUTSELECT 0x70 - -#define HW_BCH_FLASH0LAYOUT0 0x80 -#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 -#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 -#define BP_BCH_FLASH0LAYOUT0_ECC0 12 -#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 -#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 -#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 -#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 -#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 -#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 -#define BP_BCH_FLASH0LAYOUT1_ECCN 12 -#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 -#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 - -#define HW_BCH_BLOCKNAME 0x150 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h deleted file mode 100644 index 7c546afd57a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp378x: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) -#define REGS_CLKCTRL_PHYS 0x80040000 -#define REGS_CLKCTRL_SIZE 0x2000 - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 -#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 -#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00000FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 -#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F -#define BP_CLKCTRL_EMI_DIV_EMI 0 -#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 -#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 -#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_TV 0xD0 - -#define HW_CLKCTRL_ETM 0xE0 - -#define HW_CLKCTRL_FRAC 0xF0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_FRAC1 0x100 - -#define HW_CLKCTRL_CLKSEQ 0x110 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0x120 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h deleted file mode 100644 index fdedd00c0e2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: DCP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) -#define REGS_DCP_PHYS 0x80028000 -#define REGS_DCP_SIZE 0x2000 - -#define HW_DCP_CTRL 0x0 -#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF -#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 -#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 -#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 -#define BM_DCP_CTRL_CLKGATE 0x40000000 -#define BM_DCP_CTRL_SFTRST 0x80000000 - -#define HW_DCP_STAT 0x10 -#define BM_DCP_STAT_IRQ 0x0000000F -#define BP_DCP_STAT_IRQ 0 - -#define HW_DCP_CHANNELCTRL 0x20 -#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF -#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 - -#define HW_DCP_CONTEXT 0x50 -#define BM_DCP_PACKET1_INTERRUPT 0x00000001 -#define BP_DCP_PACKET1_INTERRUPT 0 -#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 -#define BM_DCP_PACKET1_CHAIN 0x00000004 -#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 -#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 -#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 -#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 -#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 -#define BM_DCP_PACKET1_OTP_KEY 0x00000400 -#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 -#define BM_DCP_PACKET1_HASH_INIT 0x00001000 -#define BM_DCP_PACKET1_HASH_TERM 0x00002000 -#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F -#define BP_DCP_PACKET2_CIPHER_SELECT 0 -#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 -#define BP_DCP_PACKET2_CIPHER_MODE 4 -#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 -#define BP_DCP_PACKET2_KEY_SELECT 8 -#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 -#define BP_DCP_PACKET2_HASH_SELECT 16 -#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 -#define BP_DCP_PACKET2_CIPHER_CFG 24 - -#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40) -#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40) -#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40) -#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40) - -#define HW_DCP_CHnCMDPTR 0x100 - -#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40) -#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40) -#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40) -#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40) - -#define HW_DCP_CHnSEMA 0x110 -#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF -#define BP_DCP_CHnSEMA_INCREMENT 0 - -#define HW_DCP_CH0STAT (0x120 + 0 * 0x40) -#define HW_DCP_CH1STAT (0x120 + 1 * 0x40) -#define HW_DCP_CH2STAT (0x120 + 2 * 0x40) -#define HW_DCP_CH3STAT (0x120 + 3 * 0x40) - -#define HW_DCP_CHnSTAT 0x120 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h deleted file mode 100644 index 5293005523b..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * stmp378x: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) -#define REGS_DIGCTL_PHYS 0x8001C000 -#define REGS_DIGCTL_SIZE 0x2000 - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 - -#define HW_DIGCTL_ARMCACHE 0x2B0 -#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 -#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 -#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 -#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 -#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 -#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 -#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 -#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 -#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 -#define BP_DIGCTL_ARMCACHE_VALID_SS 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h deleted file mode 100644 index 02851431677..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * stmp378x: DRAM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000) -#define REGS_DRAM_PHYS 0x800E0000 -#define REGS_DRAM_SIZE 0x2000 - -#define HW_DRAM_CTL06 0x18 - -#define HW_DRAM_CTL08 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h deleted file mode 100644 index da25f7e397e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: DRI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) -#define REGS_DRI_PHYS 0x80074000 -#define REGS_DRI_SIZE 0x2000 - -#define HW_DRI_CTRL 0x0 -#define BM_DRI_CTRL_RUN 0x00000001 -#define BP_DRI_CTRL_RUN 0 -#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 -#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 -#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 -#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 -#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 -#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 -#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 -#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 -#define BM_DRI_CTRL_CLKGATE 0x40000000 -#define BM_DRI_CTRL_SFTRST 0x80000000 - -#define HW_DRI_TIMING 0x10 -#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF -#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 -#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 -#define BP_DRI_TIMING_PILOT_REP_RATE 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h deleted file mode 100644 index cc353bec331..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * stmp378x: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) -#define REGS_ECC8_PHYS 0x80008000 -#define REGS_ECC8_SIZE 0x2000 - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h deleted file mode 100644 index 98773fc33d7..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * stmp378x: EMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) -#define REGS_EMI_PHYS 0x80020000 -#define REGS_EMI_SIZE 0x2000 - -#define HW_EMI_STAT 0x10 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h deleted file mode 100644 index 2cc8bbe9168..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * stmp378x: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 -#define BP_GPMI_CTRL0_ADDRESS 17 -#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 -#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 -#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 -#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF -#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 -#define BP_GPMI_CTRL1_RDN_DELAY 12 -#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 -#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 -#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h deleted file mode 100644 index 13a234c9943..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp378x: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h deleted file mode 100644 index f996e80f40e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) -#define REGS_ICOLL_PHYS 0x80000000 -#define REGS_ICOLL_SIZE 0x2000 - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 -#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F -#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x70 - -#define HW_ICOLL_INTERRUPTn 0x120 - -#define HW_ICOLL_INTERRUPTn 0x120 -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h deleted file mode 100644 index a5b4ef10fab..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: IR register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) -#define REGS_IR_PHYS 0x80078000 -#define REGS_IR_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h deleted file mode 100644 index 9cdbef4badc..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * stmp378x: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_RUN 0x00000001 -#define BP_LCDIF_CTRL_RUN 0 -#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 -#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 -#define BP_LCDIF_CTRL_WORD_LENGTH 8 -#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 -#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 -#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 -#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 -#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 -#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 -#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 - -#define HW_LCDIF_TRANSFER_COUNT 0x20 -#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF -#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 -#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 -#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 - -#define HW_LCDIF_CUR_BUF 0x30 - -#define HW_LCDIF_NEXT_BUF 0x40 - -#define HW_LCDIF_TIMING 0x60 - -#define HW_LCDIF_VDCTRL0 0x70 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF -#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x80 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 - -#define HW_LCDIF_VDCTRL2 0x90 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 - -#define HW_LCDIF_VDCTRL3 0xA0 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 - -#define HW_LCDIF_VDCTRL4 0xB0 -#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF -#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 - -#define HW_LCDIF_DVICTRL0 0xC0 -#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF -#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 -#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 -#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 -#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 -#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 - -#define HW_LCDIF_DVICTRL1 0xD0 -#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF -#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 -#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 -#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 - -#define HW_LCDIF_DVICTRL2 0xE0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 -#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 - -#define HW_LCDIF_DVICTRL3 0xF0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 -#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 - -#define HW_LCDIF_DVICTRL4 0x100 -#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF -#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 -#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 -#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 -#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 -#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 -#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 -#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 - -#define HW_LCDIF_CSC_COEFF0 0x110 -#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 -#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 -#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 -#define BP_LCDIF_CSC_COEFF0_C0 16 - -#define HW_LCDIF_CSC_COEFF1 0x120 -#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF -#define BP_LCDIF_CSC_COEFF1_C1 0 -#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 -#define BP_LCDIF_CSC_COEFF1_C2 16 - -#define HW_LCDIF_CSC_COEFF2 0x130 -#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF -#define BP_LCDIF_CSC_COEFF2_C3 0 -#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 -#define BP_LCDIF_CSC_COEFF2_C4 16 - -#define HW_LCDIF_CSC_COEFF3 0x140 -#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF -#define BP_LCDIF_CSC_COEFF3_C5 0 -#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 -#define BP_LCDIF_CSC_COEFF3_C6 16 - -#define HW_LCDIF_CSC_COEFF4 0x150 -#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF -#define BP_LCDIF_CSC_COEFF4_C7 0 -#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 -#define BP_LCDIF_CSC_COEFF4_C8 16 - -#define HW_LCDIF_CSC_OFFSET 0x160 -#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF -#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 -#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 -#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 - -#define HW_LCDIF_CSC_LIMIT 0x170 -#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF -#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 -#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 -#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 -#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 -#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 - -#define HW_LCDIF_STAT 0x1D0 -#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h deleted file mode 100644 index cb8cb06f827..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * stmp378x: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) -#define REGS_LRADC_PHYS 0x80050000 -#define REGS_LRADC_SIZE 0x2000 - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h deleted file mode 100644 index f0af64d9937..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: OCOTP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000) -#define REGS_OCOTP_PHYS 0x8002C000 -#define REGS_OCOTP_SIZE 0x2000 - -#define HW_OCOTP_CTRL 0x0 -#define BM_OCOTP_CTRL_BUSY 0x00000100 -#define BM_OCOTP_CTRL_ERROR 0x00000200 -#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 -#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 -#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 -#define BP_OCOTP_CTRL_WR_UNLOCK 16 - -#define HW_OCOTP_DATA 0x10 - -#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10) -#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10) -#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10) -#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10) - -#define HW_OCOTP_CUSTn 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h deleted file mode 100644 index 50d90ea1b13..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * stmp378x: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h deleted file mode 100644 index e454c830f07..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) -#define REGS_POWER_PHYS 0x80044000 -#define REGS_POWER_SIZE 0x2000 - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 -#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 -#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 -#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xC0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000200 - -#define HW_POWER_RESET 0x100 - -#define HW_POWER_DEBUG 0x110 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h deleted file mode 100644 index 0d0f9e56ec7..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * stmp378x: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) -#define REGS_PWM_PHYS 0x80064000 -#define REGS_PWM_SIZE 0x2000 - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h deleted file mode 100644 index 54d297896de..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * stmp378x: PXP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) -#define REGS_PXP_PHYS 0x8002A000 -#define REGS_PXP_SIZE 0x2000 - -#define HW_PXP_CTRL 0x0 -#define BM_PXP_CTRL_ENABLE 0x00000001 -#define BP_PXP_CTRL_ENABLE 0 -#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 -#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 -#define BM_PXP_CTRL_ROTATE 0x00000300 -#define BP_PXP_CTRL_ROTATE 8 -#define BM_PXP_CTRL_HFLIP 0x00000400 -#define BM_PXP_CTRL_VFLIP 0x00000800 -#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 -#define BP_PXP_CTRL_S0_FORMAT 12 -#define BM_PXP_CTRL_SCALE 0x00040000 -#define BM_PXP_CTRL_CROP 0x00080000 - -#define HW_PXP_STAT 0x10 -#define BM_PXP_STAT_IRQ 0x00000001 -#define BP_PXP_STAT_IRQ 0 - -#define HW_PXP_RGBBUF 0x20 - -#define HW_PXP_RGBSIZE 0x40 -#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF -#define BP_PXP_RGBSIZE_HEIGHT 0 -#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 -#define BP_PXP_RGBSIZE_WIDTH 12 - -#define HW_PXP_S0BUF 0x50 - -#define HW_PXP_S0UBUF 0x60 - -#define HW_PXP_S0VBUF 0x70 - -#define HW_PXP_S0PARAM 0x80 -#define BM_PXP_S0PARAM_HEIGHT 0x000000FF -#define BP_PXP_S0PARAM_HEIGHT 0 -#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 -#define BP_PXP_S0PARAM_WIDTH 8 -#define BM_PXP_S0PARAM_YBASE 0x00FF0000 -#define BP_PXP_S0PARAM_YBASE 16 -#define BM_PXP_S0PARAM_XBASE 0xFF000000 -#define BP_PXP_S0PARAM_XBASE 24 - -#define HW_PXP_S0BACKGROUND 0x90 - -#define HW_PXP_S0CROP 0xA0 -#define BM_PXP_S0CROP_HEIGHT 0x000000FF -#define BP_PXP_S0CROP_HEIGHT 0 -#define BM_PXP_S0CROP_WIDTH 0x0000FF00 -#define BP_PXP_S0CROP_WIDTH 8 -#define BM_PXP_S0CROP_YBASE 0x00FF0000 -#define BP_PXP_S0CROP_YBASE 16 -#define BM_PXP_S0CROP_XBASE 0xFF000000 -#define BP_PXP_S0CROP_XBASE 24 - -#define HW_PXP_S0SCALE 0xB0 -#define BM_PXP_S0SCALE_XSCALE 0x00003FFF -#define BP_PXP_S0SCALE_XSCALE 0 -#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 -#define BP_PXP_S0SCALE_YSCALE 16 - -#define HW_PXP_CSCCOEFF0 0xD0 - -#define HW_PXP_CSCCOEFF1 0xE0 - -#define HW_PXP_CSCCOEFF2 0xF0 - -#define HW_PXP_S0COLORKEYLOW 0x180 - -#define HW_PXP_S0COLORKEYHIGH 0x190 - -#define HW_PXP_OL0 (0x200 + 0 * 0x40) -#define HW_PXP_OL1 (0x200 + 1 * 0x40) -#define HW_PXP_OL2 (0x200 + 2 * 0x40) -#define HW_PXP_OL3 (0x200 + 3 * 0x40) -#define HW_PXP_OL4 (0x200 + 4 * 0x40) -#define HW_PXP_OL5 (0x200 + 5 * 0x40) -#define HW_PXP_OL6 (0x200 + 6 * 0x40) -#define HW_PXP_OL7 (0x200 + 7 * 0x40) - -#define HW_PXP_OLn 0x200 - -#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) -#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) -#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) -#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) -#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) -#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) -#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) -#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) - -#define HW_PXP_OLnSIZE 0x210 -#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF -#define BP_PXP_OLnSIZE_HEIGHT 0 -#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 -#define BP_PXP_OLnSIZE_WIDTH 8 - -#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) -#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) -#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) -#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) -#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) -#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) -#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) -#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) - -#define HW_PXP_OLnPARAM 0x220 -#define BM_PXP_OLnPARAM_ENABLE 0x00000001 -#define BP_PXP_OLnPARAM_ENABLE 0 -#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 -#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 -#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 -#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 -#define BP_PXP_OLnPARAM_FORMAT 4 -#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 -#define BP_PXP_OLnPARAM_ALPHA 8 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h deleted file mode 100644 index b8dbd6742d9..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * stmp378x: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 -#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF -#define BP_RTC_PERSISTENT1_GENERAL 0 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h deleted file mode 100644 index 6df41762c2a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * stmp378x: SAIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SAIF_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h deleted file mode 100644 index 801539848c2..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp378x: SPDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 - -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 -#define BM_SPDIF_CTRL_SFTRST 0x80000000 - -#define HW_SPDIF_STAT 0x10 - -#define HW_SPDIF_FRAMECTRL 0x20 - -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 -#define BP_SPDIF_SRR_BASEMULT 28 - -#define HW_SPDIF_DEBUG 0x40 - -#define HW_SPDIF_DATA 0x50 - -#define HW_SPDIF_VERSION 0x60 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h deleted file mode 100644 index 28aacf0f58e..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * stmp378x: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h deleted file mode 100644 index 08343a8b556..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: SYDMA register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) -#define REGS_SYDMA_PHYS 0x80026000 -#define REGS_SYDMA_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h deleted file mode 100644 index b5527957c67..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * stmp378x: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) -#define REGS_TIMROT_PHYS 0x80068000 -#define REGS_TIMROT_SIZE 0x2000 - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 -#define BP_TIMROT_ROTCTRL_SELECT_A 0 -#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 -#define BP_TIMROT_ROTCTRL_SELECT_B 4 -#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 -#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 -#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 -#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 -#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 -#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 -#define BP_TIMROT_ROTCTRL_DIVIDER 16 -#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_ROTCOUNT 0x10 -#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF -#define BP_TIMROT_ROTCOUNT_UPDOWN 0 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h deleted file mode 100644 index 7f895cb3435..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * stmp378x: TVENC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) -#define REGS_TVENC_PHYS 0x80038000 -#define REGS_TVENC_SIZE 0x2000 - -#define HW_TVENC_CTRL 0x0 -#define BM_TVENC_CTRL_CLKGATE 0x40000000 -#define BM_TVENC_CTRL_SFTRST 0x80000000 - -#define HW_TVENC_CONFIG 0x10 -#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 -#define BP_TVENC_CONFIG_ENCD_MODE 0 -#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 -#define BP_TVENC_CONFIG_SYNC_MODE 4 -#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 -#define BM_TVENC_CONFIG_CGAIN 0x0000C000 -#define BP_TVENC_CONFIG_CGAIN 14 -#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 -#define BP_TVENC_CONFIG_YGAIN_SEL 16 -#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 - -#define HW_TVENC_SYNCOFFSET 0x30 - -#define HW_TVENC_COLORSUB0 0xC0 - -#define HW_TVENC_COLORBURST 0x140 -#define BM_TVENC_COLORBURST_PBA 0x00FF0000 -#define BP_TVENC_COLORBURST_PBA 16 -#define BM_TVENC_COLORBURST_NBA 0xFF000000 -#define BP_TVENC_COLORBURST_NBA 24 - -#define HW_TVENC_MACROVISION0 0x150 - -#define HW_TVENC_MACROVISION1 0x160 - -#define HW_TVENC_MACROVISION2 0x170 - -#define HW_TVENC_MACROVISION3 0x180 - -#define HW_TVENC_MACROVISION4 0x190 - -#define HW_TVENC_DACCTRL 0x1A0 -#define BM_TVENC_DACCTRL_RVAL 0x00000070 -#define BP_TVENC_DACCTRL_RVAL 4 -#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 -#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 -#define BM_TVENC_DACCTRL_GAINUP 0x00040000 -#define BM_TVENC_DACCTRL_GAINDN 0x00080000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h deleted file mode 100644 index a251e68bb3a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000) -#define REGS_UARTAPP2_PHYS 0x8006E000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb552a..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h deleted file mode 100644 index 25112c1aa60..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 -#define REGS_USBCTRL_SIZE 0x2000 - -#define HW_USBCTRL_USBCMD 0x140 -#define BM_USBCTRL_USBCMD_RS 0x00000001 -#define BP_USBCTRL_USBCMD_RS 0 -#define BM_USBCTRL_USBCMD_RST 0x00000002 - -#define HW_USBCTRL_USBINTR 0x148 -#define BM_USBCTRL_USBINTR_UE 0x00000001 -#define BP_USBCTRL_USBINTR_UE 0 - -#define HW_USBCTRL_PORTSC1 0x184 -#define BM_USBCTRL_PORTSC1_PHCD 0x00800000 - -#define HW_USBCTRL_OTGSC 0x1A4 -#define BM_USBCTRL_OTGSC_ID 0x00000100 -#define BM_USBCTRL_OTGSC_IDIS 0x00010000 -#define BM_USBCTRL_OTGSC_IDIE 0x01000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h deleted file mode 100644 index 11f3b732dc9..00000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp378x: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) -#define REGS_USBPHY_PHYS 0x8007C000 -#define REGS_USBPHY_SIZE 0x2000 - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 |