diff options
| author | Anish Trivedi <anish@freescale.com> | 2011-04-11 14:49:02 -0500 |
|---|---|---|
| committer | Eric Miao <eric.miao@canonical.com> | 2011-11-10 07:37:40 +0800 |
| commit | 15deb1198811f3df3e7adbe4c7701b1915700442 (patch) | |
| tree | 81818bc2018e93405b631a6718dfdc424beda4db /include | |
| parent | 61c83607e9095c54caf06500861c546e03132527 (diff) | |
ENGR00122019 SAHARA: Add padding around buffers to prevent cache incoherency
Added padding of 64 bytes (cache line size for Cortex-A8) around
buffers that are used by the hardware to prevent any cache
coherency problems that could arise if buffers share a cache line
with some other data that is used by the CPU.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mxc_sahara.h | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/include/linux/mxc_sahara.h b/include/linux/mxc_sahara.h index 8e341cce970..244d6920fd5 100644 --- a/include/linux/mxc_sahara.h +++ b/include/linux/mxc_sahara.h @@ -968,7 +968,10 @@ typedef struct fsl_shw_hco_t { /* fsl_shw_hash_context_object */ uint8_t digest_length; /* in bytes */ uint8_t context_length; /* in bytes */ uint8_t context_register_length; /* in bytes */ - uint32_t context[9]; /* largest digest + msg size */ + /* ensure following HW buffers not cached with surrounding fields */ + uint8_t cache_front_pad[64]; /* fill out cache line */ + uint32_t context[9]; /* largest digest + msg size */ + uint8_t cache_back_pad[64]; /* fill out cache line */ } fsl_shw_hco_t; /*! @@ -980,12 +983,12 @@ typedef struct fsl_shw_hmco_t { /* fsl_shw_hmac_context_object */ uint8_t digest_length; /*!< in bytes */ uint8_t context_length; /*!< in bytes */ uint8_t context_register_length; /*!< in bytes */ - uint32_t ongoing_context[9]; /*!< largest digest + msg - size */ - uint32_t inner_precompute[9]; /*!< largest digest + msg - size */ - uint32_t outer_precompute[9]; /*!< largest digest + msg - size */ + /* ensure following HW buffers not cached with surrounding fields */ + uint8_t cache_front_pad[64]; /* fill out cache line */ + uint32_t ongoing_context[9]; /**< largest digest + msg size */ + uint32_t inner_precompute[9]; /**< largest digest + msg size */ + uint32_t outer_precompute[9]; /**< largest digest + msg size */ + uint8_t cache_back_pad[64]; /* fill out cache line */ } fsl_shw_hmco_t; /* REQ-S2LRD-PINTFC-COA-SCCO-001 */ @@ -999,7 +1002,10 @@ typedef struct fsl_shw_scco_t { /* Could put modulus plus 16-octet context in union with arc4 sbox+ptrs... */ fsl_shw_ctr_mod_t modulus_exp; + /* ensure following HW buffers not cached with surrounding fields */ + uint8_t cache_front_pad[64]; /* fill out cache line */ uint8_t context[259]; + uint8_t cache_back_pad[64]; /* fill out cache line */ } fsl_shw_scco_t; /*! @@ -1023,6 +1029,8 @@ typedef struct fsl_shw_acco_t { fsl_shw_hco_t hash_ctx_info; /*!< For running the hash */ } auth_info; /*!< "auth" info struct */ uint8_t unencrypted_mac[16]; /*!< max block size... */ + /* ensure above HW buffer not cached with any following variables */ + uint8_t cache_back_pad[64]; /* fill out cache line */ } fsl_shw_acco_t; /*! |