imx6q-sabrelite: add vpu dt support

Signed-off-by: Jason Chen <jason.chen@linaro.org>

6 files changed, 37 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index c24f7723f15..c82bdee711c 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -203,8 +203,9 @@
 			};
 
 			vpu@02040000 {
+				compatible = "fsl,vpu";
 				reg = <0x02040000 0x3c000>;
-				interrupts = <0 3 0x04 0 12 0x04>;
+				interrupts = <0 12 0x04 0 3 0x04>;
 			};
 
 			aipstz@0207c000 { /* AIPSTZ1 */
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index c436a711d7e..5cdafb0e14a 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -1938,6 +1938,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_iahb_clk),
 	_REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
 	_REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
+	_REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk),
 };
 
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 0584524611f..f5b31867953 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -30,6 +30,7 @@
 #include <mach/iram.h>
 #include <mach/iomux-mx6q.h>
 #include <mach/ipu-v3.h>
+#include <mach/mxc_vpu.h>
 
 static iomux_v3_cfg_t imx6q_sabrelite_pads[] = {
 	/* DISPLAY */
@@ -103,9 +104,21 @@ static struct imx_ipuv3_platform_data ipuv3_pdata = {
 	.pg = mx6q_ipuv3_pg,
 };
 
+static void mx6q_vpu_reset(void)
+{
+	imx_reset_vpu();
+}
+
+static struct mxc_vpu_platform_data vpu_pdata = {
+	.iram_enable = true,
+	.iram_size = 0x21000,
+	.reset = mx6q_vpu_reset,
+};
+
 static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("fsl,ipuv3", MX6Q_IPU1_BASE_ADDR, "imx-ipuv3.0", &ipuv3_pdata),
 	OF_DEV_AUXDATA("fsl,ipuv3", MX6Q_IPU2_BASE_ADDR, "imx-ipuv3.1", &ipuv3_pdata),
+	OF_DEV_AUXDATA("fsl,vpu", MX6Q_VPU_BASE_ADDR, "mxc_vpu.0", &vpu_pdata),
 };
 
 static void __init imx6q_init_machine(void)
@@ -148,6 +161,9 @@ static void __init imx6q_map_io(void)
 	imx6q_iomux_map_io();
 
 	init_consistent_dma_size(SZ_64M);
+
+	if (!system_rev)
+		system_rev = 0x63000;
 }
 
 static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index ac8eb58aeeb..bcc4e93acc5 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -28,6 +28,22 @@ static void __iomem *src_base;
 #define cpu_logical_map(cpu)		0
 #endif
 
+void imx_reset_vpu(void)
+{
+	u32 val;
+
+	/* mask interrupt due to vpu passed reset */
+	val = readl_relaxed(src_base + 0x18);
+	val |= 0x02;
+	writel_relaxed(val, src_base + 0x18);
+
+	val = readl_relaxed(src_base);
+	val |= 0x5;    /* warm reset vpu */
+	writel_relaxed(val, src_base);
+	while (readl_relaxed(src_base) & 0x04)
+		;
+}
+
 void imx_reset_ipu(int ipu)
 {
 	u32 val;
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 21f4a9282cd..d6a191de71f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -122,6 +122,7 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 #endif
 extern void imx_reset_ipu(int ipu);
+extern void imx_reset_vpu(void);
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
index 28b1561adf2..9292e2e4ecc 100644
--- a/arch/arm/plat-mxc/include/mach/mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -39,6 +39,7 @@
 #define MX6Q_IRAM_BASE_ADDR		0x00900000
 #define MX6Q_IRAM_SIZE			(SZ_256K - SZ_4K)
 
+#define MX6Q_VPU_BASE_ADDR         	0x02040000
 #define MX6Q_IPU1_BASE_ADDR         	0x02400000
 #define MX6Q_IPU2_BASE_ADDR         	0x02800000