diff options
| author | Jason Chen <jason.chen@linaro.org> | 2011-12-05 17:54:54 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2012-01-11 21:39:10 +0800 |
| commit | 95756b30fb488275e2a2b9925c1e52f8a06aeca1 (patch) | |
| tree | 271f36f53d44ba4a3fb0555732b32260a6bd59f7 /arch | |
| parent | d7de772d2ea23a3cf013d5c0bcf08452dc8a4385 (diff) | |
imx6q-sabrelite: add mxc hdmi and related i2c dt support
Signed-off-by: Jason Chen <jason.chen@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-sabrelite.dts | 15 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/mach-imx/clock-imx6q.c | 1 |
3 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 08d920de728..a8bd4dcdd4d 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -44,6 +44,21 @@ uart2: uart@021e8000 { status = "okay"; }; + + i2c@021a4000 { /* I2C2 */ + status = "okay"; + clock-frequency = <400000>; + + ddc: ddc@50 { + compatible = "fsl,imx6q-hdmi-ddc"; + reg = <0x50>; + }; + }; + }; + + hdmi@0x00120000 { /* HDMI */ + ipu = <0>; + di = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index f19e37775d5..c46e917a799 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -572,6 +572,12 @@ }; }; + hdmi@0x00120000 { /* HDMI */ + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x00120000 0x9000>; + interrupts = <0 115 0x04 0 116 0x04>; + }; + ipu@0x02400000 { /* IPU1 */ compatible = "fsl,ipuv3"; reg = <0x02400000 0x400000>; diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 1d19f7dbc5c..34567c0af25 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1935,6 +1935,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di1_clk), _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di0_clk), _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di1_clk), + _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_iahb_clk), }; int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) |