diff options
| author | Jason Chen <jason.chen@linaro.org> | 2011-12-09 11:22:41 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2012-01-11 21:39:23 +0800 |
| commit | 07aede42ca7714453009892477efa1a7f164e1d4 (patch) | |
| tree | da88581478dd553ad32436effa7a915689932f2e /arch | |
| parent | b844c16efcd79ef2aaf71974b44403af20746c6a (diff) | |
MXC SRC: refine IPU VPU reset function
Signed-off-by: Jason Chen <jason.chen@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/src.c | 46 |
1 files changed, 31 insertions, 15 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index bcc4e93acc5..9c6b01c488f 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -18,9 +18,16 @@ #include <asm/unified.h> #define SRC_SCR 0x000 +#define SRC_SIMR 0x018 #define SRC_GPR1 0x020 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 +#define BP_SRC_SCR_VPU_RST 2 +#define BP_SRC_SCR_IPU1_RST 3 +#define BP_SRC_SCR_IPU2_RST 12 +#define BP_SRC_SIMR_VPU_MASK 1 +#define BP_SRC_SIMR_IPU1_MASK 2 +#define BP_SRC_SIMR_IPU2_MASK 4 static void __iomem *src_base; @@ -33,28 +40,37 @@ void imx_reset_vpu(void) u32 val; /* mask interrupt due to vpu passed reset */ - val = readl_relaxed(src_base + 0x18); - val |= 0x02; - writel_relaxed(val, src_base + 0x18); - - val = readl_relaxed(src_base); - val |= 0x5; /* warm reset vpu */ - writel_relaxed(val, src_base); - while (readl_relaxed(src_base) & 0x04) + val = readl_relaxed(src_base + SRC_SIMR); + val |= (1 << BP_SRC_SIMR_VPU_MASK); + writel_relaxed(val, src_base + SRC_SIMR); + + val = readl_relaxed(src_base + SRC_SCR); + val |= (1 << BP_SRC_SCR_VPU_RST); /* reset vpu */ + writel_relaxed(val, src_base + SRC_SCR); + while (readl_relaxed(src_base + SRC_SCR) & + (1 << BP_SRC_SCR_VPU_RST)) ; } void imx_reset_ipu(int ipu) { u32 val; + u32 scr_off = ipu ? BP_SRC_SCR_IPU2_RST : BP_SRC_SCR_IPU1_RST; + u32 simr_off = ipu ? BP_SRC_SIMR_IPU2_MASK : BP_SRC_SIMR_IPU1_MASK; + + /* mask interrupt due to ipu passed reset */ + val = readl_relaxed(src_base + SRC_SIMR); + val |= (1 << simr_off); + writel_relaxed(val, src_base + SRC_SIMR); - /* hard reset the IPU */ - val = readl_relaxed(src_base); - if (ipu == 0) - val |= 1 << 3; - else - val |= 1 << 12; - writel_relaxed(val, src_base); + /* reset the IPU */ + val = readl_relaxed(src_base + SRC_SCR); + val |= (1 << scr_off); + writel_relaxed(val, src_base + SRC_SCR); + + while (readl_relaxed(src_base + SRC_SCR) & + (1 << scr_off)) + ; } void imx_enable_cpu(int cpu, bool enable) |