ENGR00155612-1 [mx6q]dynamically sd pad setting change

on mx6q, it supports sd3.0 card with DDR 50MHz, SDR 100Mhz and SDR 200MHz.
sd pads have to be changed dynamically for these large scale of clock
frequencies.
add different pad setting definitions for these clock frequencies under
board file, since these settings are really board dependent.
add callback funtion in sdhc platform data to give driver approach to
change pad setting according to current clock frequency.

Signed-off-by: Tony Lin <tony.lin@freescale.com>

3 files changed, 214 insertions, 40 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index 1f7b3d0f779..b447c247c65 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -132,16 +132,16 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
 	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
 	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
 	/* SD3 */
-	MX6Q_PAD_SD3_CLK__USDHC3_CLK,
-	MX6Q_PAD_SD3_CMD__USDHC3_CMD,
-	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
-	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
-	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
-	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
-	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
-	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
-	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
-	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
 	MX6Q_PAD_SD3_RST__USDHC3_RST,
 	/* SD3 VSelect */
 	MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
@@ -149,16 +149,16 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
 	MX6Q_PAD_NANDF_CS0__GPIO_6_11,
 	MX6Q_PAD_NANDF_CS1__GPIO_6_14,
 	/* SD4 */
-	MX6Q_PAD_SD4_CLK__USDHC4_CLK,
-	MX6Q_PAD_SD4_CMD__USDHC4_CMD,
-	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
-	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
-	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
-	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
-	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
-	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
-	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
-	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
+	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
+	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
+	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
+	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
+	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
+	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
+	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,
+	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,
+	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,
+	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,
 	MX6Q_PAD_NANDF_ALE__USDHC4_RST,
 	/* eCSPI1 */
 	MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
@@ -247,17 +247,102 @@ static iomux_v3_cfg_t mx6q_sabreauto_esai_record_pads[] = {
 	MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR,
 };
 
+#define MX6Q_USDHC_PAD_SETTING(id, speed)	\
+mx6q_sd##id##_##speed##mhz[] = {		\
+	MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT4__USDHC##id##_DAT4_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT5__USDHC##id##_DAT5_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT6__USDHC##id##_DAT6_##speed##MHZ,	\
+	MX6Q_PAD_SD##id##_DAT7__USDHC##id##_DAT7_##speed##MHZ,	\
+}
+
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 50);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 100);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 200);
+
+enum sd_pad_mode {
+	SD_PAD_MODE_LOW_SPEED,
+	SD_PAD_MODE_MED_SPEED,
+	SD_PAD_MODE_HIGH_SPEED,
+};
+
+static int plt_sd3_pad_change(int clock)
+{
+	static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
+
+	if (clock > 100000000) {
+		if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_HIGH_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_200mhz,
+					ARRAY_SIZE(mx6q_sd3_200mhz));
+	} else if (clock > 52000000) {
+		if (pad_mode == SD_PAD_MODE_MED_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_MED_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_100mhz,
+					ARRAY_SIZE(mx6q_sd3_100mhz));
+	} else {
+		if (pad_mode == SD_PAD_MODE_LOW_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_LOW_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_50mhz,
+					ARRAY_SIZE(mx6q_sd3_50mhz));
+	}
+}
+
+static int plt_sd4_pad_change(int clock)
+{
+	static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
+
+	if (clock > 100000000) {
+		if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_HIGH_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_200mhz,
+					ARRAY_SIZE(mx6q_sd4_200mhz));
+	} else if (clock > 52000000) {
+		if (pad_mode == SD_PAD_MODE_MED_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_MED_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_100mhz,
+					ARRAY_SIZE(mx6q_sd4_100mhz));
+	} else {
+		if (pad_mode == SD_PAD_MODE_LOW_SPEED)
+			return 0;
+
+		pad_mode = SD_PAD_MODE_LOW_SPEED;
+		return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_50mhz,
+					ARRAY_SIZE(mx6q_sd4_50mhz));
+	}
+}
+
 static const struct esdhc_platform_data mx6q_sabreauto_sd3_data __initconst = {
 	.cd_gpio = MX6Q_SABREAUTO_SD3_CD,
 	.wp_gpio = MX6Q_SABREAUTO_SD3_WP,
 	.support_18v = 1,
 	.support_8bit = 1,
+	.platform_pad_change = plt_sd3_pad_change,
 };
 
 /* No card detect signal for SD4 */
 static const struct esdhc_platform_data mx6q_sabreauto_sd4_data __initconst = {
 	.always_present = 1,
 	.support_8bit = 1,
+	.platform_pad_change = plt_sd4_pad_change,
 };
 
 /* The GPMI is conflicted with SD3, so init this in the driver. */
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
index cb34cd82806..ee9e41cdd1a 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -25,5 +25,6 @@ struct esdhc_platform_data {
 	unsigned int always_present;
 	unsigned int support_18v;
 	unsigned int support_8bit;
+	int (*platform_pad_change)(int clock);
 };
 #endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index 55bc053a6dc..ce2624390c7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -48,6 +48,14 @@ typedef enum iomux_config {
 		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
 #define MX6Q_USDHC_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |	\
+		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |	\
+		PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_100MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
+		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED |	\
+		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_200MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
 		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH |	\
 		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
@@ -6476,8 +6484,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_TEST_MODE__TCU_TEST_MODE		\
 		(_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7		\
+#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT7__UART1_TXD		\
 		(_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT7__UART1_RXD		\
@@ -6495,8 +6507,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV		\
 		(_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6		\
+#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT6__UART1_TXD		\
 		(_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT6__UART1_RXD		\
@@ -6514,8 +6530,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10		\
 		(_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5		\
+#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT5__UART2_TXD		\
 		(_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT5__UART2_RXD		\
@@ -6533,8 +6553,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11		\
 		(_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4		\
+#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT4__UART2_TXD		\
 		(_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT4__UART2_RXD		\
@@ -6552,8 +6576,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12		\
 		(_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD		\
+#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ		\
 		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ		\
+		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ		\
+		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_CMD__UART2_CTS		\
 		(_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_CMD__CAN1_TXCAN		\
@@ -6569,8 +6597,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13		\
 		(_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK		\
+#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ		\
 		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ		\
+		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ		\
+		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_CLK__UART2_CTS		\
 		(_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_CLK__UART2_RTS		\
@@ -6588,8 +6620,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14		\
 		(_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0		\
+#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ	\
+		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ	\
+		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT0__UART1_CTS		\
 		(_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT0__CAN2_TXCAN		\
@@ -6605,8 +6641,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15		\
 		(_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1		\
+#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT1__UART1_CTS		\
 		(_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT1__UART1_RTS		\
@@ -6624,8 +6664,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0		\
 		(_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2		\
+#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28		\
 		(_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8		\
@@ -6639,8 +6683,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1		\
 		(_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3		\
+#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ		\
+		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ		\
+		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD3_DAT3__UART3_CTS		\
 		(_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29		\
@@ -6799,8 +6847,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_NANDF_CS3__TPSMP_CLK		\
 		(_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD		\
+#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ		\
 		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ	\
+		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ	\
+		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_CMD__RAWNAND_RDN		\
 		(_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
 #define  MX6Q_PAD_SD4_CMD__UART3_TXD		\
@@ -6814,8 +6866,12 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR		\
 		(_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
 
-#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK		\
+#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ	\
 		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ	\
+		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ	\
+		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_CLK__RAWNAND_WRN		\
 		(_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
 #define  MX6Q_PAD_SD4_CLK__UART3_TXD		\
@@ -6965,8 +7021,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT0__RAWNAND_D8		\
 		(_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0		\
+#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT0__RAWNAND_DQS		\
 		(_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
 #define  MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24		\
@@ -6982,8 +7042,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT1__RAWNAND_D9		\
 		(_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1		\
+#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT1__PWM3_PWMO		\
 		(_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25		\
@@ -6999,8 +7063,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT2__RAWNAND_D10		\
 		(_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2		\
+#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT2__PWM4_PWMO		\
 		(_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26		\
@@ -7016,8 +7084,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT3__RAWNAND_D11		\
 		(_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3		\
+#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27		\
 		(_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27		\
@@ -7031,8 +7103,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT4__RAWNAND_D12		\
 		(_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4		\
+#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT4__UART2_TXD		\
 		(_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT4__UART2_RXD		\
@@ -7050,8 +7126,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT5__RAWNAND_D13		\
 		(_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5		\
+#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT5__UART2_CTS		\
 		(_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT5__UART2_RTS		\
@@ -7069,8 +7149,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT6__RAWNAND_D14		\
 		(_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6		\
+#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT6__UART2_CTS		\
 		(_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30		\
@@ -7086,8 +7170,12 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD4_DAT7__RAWNAND_D15		\
 		(_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7		\
+#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ	\
 		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ	\
+		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ	\
+		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
 #define  MX6Q_PAD_SD4_DAT7__UART2_TXD		\
 		(_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
 #define  MX6Q_PAD_SD4_DAT7__UART2_RXD		\