diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2008-09-11 15:06:34 +0100 |
|---|---|---|
| committer | Eric Miao <eric.miao@canonical.com> | 2011-11-10 07:37:27 +0800 |
| commit | 9c6d057e0d63c0eb32e0fdff9fe00b79d5813557 (patch) | |
| tree | 69c6cc0e3add2fa01bcb6c56d2b015f52bb7d53f /arch | |
| parent | cc41c14bd2ced506571fa061e22477930ff2e294 (diff) | |
Enable partial low interrupt latency mode for ARM1136
Enable partial low interrupt latency mode for ARM1136
This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 13 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 16 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 26d19bc75af..ea4f13d7158 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,6 +1088,19 @@ config ARM_ERRATA_411920 It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround. +config ARM_ERRATA_364296 + bool "Enable partial low interrupt latency mode for ARM1136" + depends on CPU_V6 && !SMP + default n + help + This options enables the workaround for the 364296 ARM1136 + r0pX errata (possible cache data corruption with + hit-under-miss enabled). It sets the undocumented bit 31 in + the auxiliary control register and the FI bit in the control + register, thus disabling hit-under-miss without putting the + processor into full low interrupt latency mode. ARM11MPCore + is not affected. + config ARM_ERRATA_430973 bool "ARM errata: Stale prediction on replaced interworking branch" depends on CPU_V7 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 59a7e1ffe7b..6d0467c9c4a 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -181,6 +181,22 @@ __v6_setup: mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them +#ifdef CONFIG_ARM_ERRATA_364296 + /* Workaround for the 364296 ARM1136 r0pX errata (possible cache data + * corruption with hit-under-miss enabled). The conditional code below + * (setting the undocumented bit 31 in the auxiliary control register + * and the FI bit in the control register) disables hit-under-miss + * without putting the processor into full low interrupt latency mode. + */ + ldr r6, =0x4107b360 @ id for ARM1136 r0pX + mrc p15, 0, r5, c0, c0, 0 @ get processor id + bic r5, r5, #0xf @ mask out part bits [3:0] + teq r5, r6 @ check for the faulty core + mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg + orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + orreq r0, r0, #(1 << 21) @ low interrupt latency configuration +#endif mov pc, lr @ return to head.S:__ret /* |