diff options
| author | Jason Chen <b02280@freescale.com> | 2011-08-22 13:56:41 +0800 |
|---|---|---|
| committer | Jason Chen <b02280@freescale.com> | 2011-08-29 11:26:40 +0800 |
| commit | 89b755ee1fe44010bc17ceb773d7fb1679fe9ca3 (patch) | |
| tree | 26e9e8b259deafcd9903b3b8b52ec744aeb52aa6 /arch/arm | |
| parent | 032ef9ccbdf2a6d9d7163dcec63109e19b17eea1 (diff) | |
ENGR00155151 imx6q clock: fix ldb and ipu-di clock enable register
ipu2-di should use CCGR3 4&5, ldb_di should use 6&7.
Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 50a13a48adc..c037f553911 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -2630,7 +2630,7 @@ static struct clk ipu2_di_clk[] = { .id = 0, .parent = &pll5_video_main_clk, .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, .enable = _clk_enable, .disable = _clk_disable, .set_parent = _clk_ipu2_di0_set_parent, @@ -2643,7 +2643,7 @@ static struct clk ipu2_di_clk[] = { .id = 1, .parent = &pll5_video_main_clk, .enable_reg = MXC_CCM_CCGR3, - .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, .enable = _clk_enable, .disable = _clk_disable, .set_parent = _clk_ipu2_di1_set_parent, |