ENGR00127265-1 MX3X: Upgrade kernel to 2.6.35

This patch contains changes to plat-mxc files.
Contains all checkpatch and copyright fixes.

Signed-off-by: Jason Liu <r64343@freescale.com>

9 files changed, 216 insertions, 26 deletions

diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 00000000000..b6494e5fa21
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h
index a6cbddc53fe..2bcf9db2617 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h
@@ -19,7 +19,10 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 
+#include <mach/irqs.h>
+
 #define MXC_PSEUDO_PARENT	MXC_INT_FORCE
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX35_GPIO1_1)
 
 enum {
 	MCU_INT_HEADPHONE = 0,
@@ -45,4 +48,8 @@ enum {
 #define MXC_PSEUDO_IRQ_RTC		(MXC_PSEUDO_IO_BASE + MCU_INT_RTC)
 #define MXC_PSEUDO_IRQ_TS_ADC		(MXC_PSEUDO_IO_BASE + MCU_INT_TS_ADC)
 
+extern int is_suspend_ops_started(void);
+extern int __init mx35_3stack_init_mc13892(void);
+extern int __init mx35_3stack_init_mc9s08dz60(void);
+
 #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100755
index 00000000000..5120007a50e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Copyright (C) 2010 Freescale Semiconductor
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *imx_add_platform_device(const char *name, int id,
+		const struct resource *res, unsigned int num_resources,
+		const void *data, size_t size_data);
+
+#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/can/platform/flexcan.h>
+struct platform_device *__init imx_add_flexcan(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irq,
+		const struct flexcan_platform_data *pdata);
+#else
+/* the ifdef can be removed once the flexcan driver has been merged */
+struct flexcan_platform_data;
+static inline struct platform_device *__init imx_add_flexcan(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irq,
+		const struct flexcan_platform_data *pdata)
+{
+	return NULL;
+}
+#endif
+
+#include <mach/i2c.h>
+struct platform_device *__init imx_add_imx_i2c(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct imxi2c_platform_data *pdata);
+
+#include <mach/imx-uart.h>
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irqrx, resource_size_t irqtx,
+		resource_size_t irqrts,
+		const struct imxuart_platform_data *pdata);
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irq,
+		const struct imxuart_platform_data *pdata);
+
+#include <mach/mxc_nand.h>
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata);
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata);
+
+#include <mach/spi.h>
+struct platform_device *__init imx_add_spi_imx(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct spi_imx_master *pdata);
+
+#include <mach/mmc.h>
+struct platform_device *__init imx_add_imx_mmc(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq1,
+		int irq2, const struct mxc_mmc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 2a24bae1b87..03996854bbf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -20,6 +20,7 @@
 #define __MACH_IOMUX_MX35_H__
 
 #include <mach/iomux-v3.h>
+#include <mach/irqs.h>
 
 /*
  * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
@@ -1263,5 +1264,10 @@
 
 #define MX35_PAD_TEST_MODE__TCU_TEST_MODE			IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
 
+#define MX35_GPIO1_1		(0 * 32 + 1)
+#define MX35_GPIO1_4		(0 * 32 + 4)
+#define MX35_GPIO2_0		(1 * 32 + 0)
+
+#define IOMUX_TO_IRQ(pin)	(MXC_GPIO_IRQ_START + pin)
 
 #endif /* __MACH_IOMUX_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 6beaf8cd69b..c18e69bca9e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -54,6 +54,11 @@ struct pad_desc {
 	unsigned select_input:3;
 };
 
+struct pad_cfg {
+	struct pad_desc pd;
+	int    pad_ctrl;
+};
+
 #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
 		_select_input, _pad_ctrl)				\
 		{							\
@@ -95,12 +100,15 @@ struct pad_desc {
  * setups a single pad in the iomuxer
  */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
+int mxc_iomux_v3_setup_pad_ext(struct pad_cfg *pad);
 
 /*
  * setups mutliple pads
  * convenient way to call the above function with tables
  */
 int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads_ext(struct pad_cfg *pad_list,
+								unsigned count);
 
 /*
  * Initialise the iomux controller
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b..352eec09e5b 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -138,6 +138,23 @@ static inline void mx31_setup_weimcs(size_t cs,
 }
 #endif
 
+/*
+ * DMA request assignments
+ */
+#define MX31_DMA_REQ_SDHC2      21
+#define MX31_DMA_REQ_SDHC1      20
+#define MX31_DMA_REQ_FIRI_TX    17
+#define MX31_DMA_REQ_FIRI_RX    16
+#define MX31_DMA_REQ_UART4_TX   13
+#define MX31_DMA_REQ_UART4_RX   12
+#define MX31_DMA_REQ_CSPI3_TX   11
+#define MX31_DMA_REQ_CSPI3_RX   10
+#define MX31_DMA_REQ_UART5_TX   11
+#define MX31_DMA_REQ_UART5_RX   10
+#define MX31_DMA_REQ_UART3_TX   9
+#define MX31_DMA_REQ_UART3_RX   8
+#define MX31_DMA_REQ_SIM        5
+
 #define MX31_INT_I2C3		3
 #define MX31_INT_I2C2		4
 #define MX31_INT_MPEG4_ENCODER	5
@@ -197,6 +214,8 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_EXT_WDOG	62
 #define MX31_INT_EXT_TV		63
 
+#define ARM11_PMU_IRQ		MXC_INT_EVTMON
+
 #define MX31_PROD_SIGNATURE		0x1	/* For MX31 */
 
 /* silicon revisions specific to i.MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae..20d342a0ebf 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,11 +1,25 @@
 #ifndef __MACH_MX35_H__
 #define __MACH_MX35_H__
+
+/*!
+ * Define this option to specify we are using the newer SDMA module.
+ */
+#define MXC_SDMA_V2
+
 /*
  * IRAM
  */
 #define MX35_IRAM_BASE_ADDR		0x10000000	/* internal ram */
 #define MX35_IRAM_SIZE			SZ_128K
 
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+#define SND_RAM_SIZE 0x10000
+#else
+#define SND_RAM_SIZE 0
+#endif
+
+#define VPU_IRAM_SIZE 0
+
 #define MX35_L2CC_BASE_ADDR		0x30000000
 #define MX35_L2CC_SIZE			SZ_1M
 
@@ -18,7 +32,7 @@
 #define MX35_ETB_SLOT4_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x10000)
 #define MX35_ETB_SLOT5_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x14000)
 #define MX35_ECT_CTIO_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
 #define MX35_I2C3_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x84000)
 #define MX35_UART1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x90000)
 #define MX35_UART2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -39,6 +53,10 @@
 #define MX35_SSI2_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x14000)
 #define MX35_ATA_DMA_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x20000)
 #define MX35_MSHC1_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_SPDIF_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x28000)
+#define MX35_ATA_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_ASRC_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x2C000)
+#define MX35_ESAI_BASE_ADDR			(MX35_SPBA0_BASE_ADDR + 0x34000)
 #define MX35_FEC_BASE_ADDR		0x50038000
 #define MX35_SPBA_CTRL_BASE_ADDR		(MX35_SPBA0_BASE_ADDR + 0x3c000)
 
@@ -52,6 +70,14 @@
 #define MX35_GPIO3_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xa4000)
 #define MX35_SCC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xac000)
 #define MX35_RNGA_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_MMC_SDHC1_BASE_ADDR 		(MX35_AIPS2_BASE_ADDR + 0xB4000)
+#define MX35_MMC_SDHC2_BASE_ADDR 		(MX35_AIPS2_BASE_ADDR + 0xB8000)
+#define MX35_MMC_SDHC3_BASE_ADDR 		(MX35_AIPS2_BASE_ADDR + 0xBC000)
+#define MX35_CAN1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xE4000)
+#define MX35_CAN2_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xE8000)
+#define MX35_IIM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xF0000)
+#define MX35_OTG_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xF4000)
+#define MX35_MLB_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xF8000)
 #define MX35_IPU_CTRL_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc0000)
 #define MX35_AUDMUX_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xc4000)
 #define MX35_GPIO1_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -61,7 +87,6 @@
 #define MX35_WDOG_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xdc000)
 #define MX35_PWM_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xe0000)
 #define MX35_RTIC_BASE_ADDR			(MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_OTG_BASE_ADDR		0x53ff4000
 
 #define MX35_ROMP_BASE_ADDR		0x60000000
 #define MX35_ROMP_BASE_ADDR_VIRT	0xfc500000
@@ -123,7 +148,7 @@
 #define MX35_INT_MMC_SDHC1	7
 #define MX35_INT_MMC_SDHC2	8
 #define MX35_INT_MMC_SDHC3	9
-#define MX35_INT_I2C		10
+#define MX35_INT_I2C1		10
 #define MX35_INT_SSI1		11
 #define MX35_INT_SSI2		12
 #define MX35_INT_CSPI2		13
@@ -189,6 +214,35 @@
 #define MX35_SYSTEM_REV_MIN		MX35_CHIP_REV_1_0
 #define MX35_SYSTEM_REV_NUM		3
 
+#define MX35_DMA_REQ_ASRC_DMA6  41
+#define MX35_DMA_REQ_ASRC_DMA5  40
+#define MX35_DMA_REQ_ASRC_DMA4  39
+#define MX35_DMA_REQ_ASRC_DMA3  38
+#define MX35_DMA_REQ_ASRC_DMA2  37
+#define MX35_DMA_REQ_ASRC_DMA1  36
+#define MX35_DMA_REQ_RSVD3      35
+#define MX35_DMA_REQ_RSVD2      34
+#define MX35_DMA_REQ_ESAI_TX    33
+#define MX35_DMA_REQ_ESAI_RX    32
+#define MX35_DMA_REQ_IPU        21
+#define MX35_DMA_REQ_RSVD1      20
+#define MX35_DMA_REQ_SPDIF_TX   13
+#define MX35_DMA_REQ_SPDIF_RX   12
+#define MX35_DMA_REQ_UART3_TX   11
+#define MX35_DMA_REQ_UART3_RX   10
+#define MX35_DMA_REQ_MSHC       5
+#define MX35_DMA_REQ_DPTC	   1
+#define MX35_DMA_REQ_DVFS  	   1
+
+/*!
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+#define NFMS  \
+	(*((volatile u32 *)MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR+0x18)))
+#define NFMS_BIT                8
+#define NFMS_NF_DWIDTH          14
+#define NFMS_NF_PG_SZ           8
+
 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
 /* these should go away */
 #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 7a356de385f..d5953f1b074 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -152,16 +152,7 @@
  * and returning the virtual address. If the physical address is not mapped,
  * it returns 0xDEADBEEF
  */
-#define IO_ADDRESS(x)   \
-	(void __force __iomem *) \
-	(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
-	((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
-	((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
-	((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
-	((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
-	((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
-	((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
-	0xDEADBEEF)
+#define IO_ADDRESS MX31_IO_ADDRESS
 
 /*
  * define the address mapping macros: in physical address order
@@ -197,6 +188,35 @@
 	(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 
 /*
+ * DMA request assignments
+ */
+#define MX3x_DMA_REQ_ECT        31
+#define MX3x_DMA_REQ_NFC        30
+#define MX3x_DMA_REQ_SSI1_TX1   29
+#define MX3x_DMA_REQ_SSI1_RX1   28
+#define MX3x_DMA_REQ_SSI1_TX2   27
+#define MX3x_DMA_REQ_SSI1_RX2   26
+#define MX3x_DMA_REQ_SSI2_TX1   25
+#define MX3x_DMA_REQ_SSI2_RX1   24
+#define MX3x_DMA_REQ_SSI2_TX2   23
+#define MX3x_DMA_REQ_SSI2_RX2   22
+#define MX3x_DMA_REQ_UART1_TX   19
+#define MX3x_DMA_REQ_UART1_RX   18
+#define MX3x_DMA_REQ_UART2_TX   17
+#define MX3x_DMA_REQ_UART2_RX   16
+#define MX3x_DMA_REQ_EXTREQ1    15
+#define MX3x_DMA_REQ_EXTREQ2    14
+#define MX3x_DMA_REQ_CSPI1_TX   9
+#define MX3x_DMA_REQ_CSPI1_RX   8
+#define MX3x_DMA_REQ_CSPI2_TX   7
+#define MX3x_DMA_REQ_CSPI2_RX   6
+#define MX3x_DMA_REQ_ATA_RX     4
+#define MX3x_DMA_REQ_ATA_TX     3
+#define MX3x_DMA_REQ_ATA_TX_END 2
+#define MX3x_DMA_REQ_CCM        1
+#define MX3x_DMA_REQ_EXTREQ0    0
+
+/*
  * Interrupt numbers
  */
 #define MX3x_INT_I2C3		3
@@ -217,6 +237,7 @@
 #define MX3x_INT_EPIT1		28
 #define MX3x_INT_GPT		29
 #define MX3x_INT_POWER_FAIL	30
+#define MX3x_INT_DVFS		31
 #define MX3x_INT_UART2		32
 #define MX3x_INT_NANDFC		33
 #define MX3x_INT_SDMA		34
@@ -389,17 +410,6 @@ static inline int mx31_revision(void)
 #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
 #define MXC_INT_EXT_TV MX3x_INT_EXT_TV
 #define PROD_SIGNATURE MX3x_PROD_SIGNATURE
-#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
-#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
-#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
-#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
-#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
-#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
-#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
-#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
-#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
-#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
-#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
 #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
 #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 08b22e1b23d..1b274a01cd5 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -235,9 +235,11 @@ struct mxc_unifi_platform_data *get_unifi_plat_data(void);
 
 #define MUX_IO_P		29
 #define MUX_IO_I		24
+
+#ifdef CONFIG_ARCH_MX5
 #define IOMUX_TO_GPIO(pin) 	((((unsigned int)pin >> MUX_IO_P) * 32) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
 #define IOMUX_TO_IRQ(pin)	(MXC_GPIO_IRQ_START + IOMUX_TO_GPIO(pin))
-
+#endif
 
 #ifndef __ASSEMBLY__