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| author | Nicolas Pitre <nicolas.pitre@linaro.org> | 2010-08-11 03:27:12 -0400 |
|---|---|---|
| committer | Nicolas Pitre <nicolas.pitre@linaro.org> | 2010-08-11 03:27:12 -0400 |
| commit | f9baa031dd6bedc6d4b39e254e3b76cd2c37769b (patch) | |
| tree | 216e51a0dc73b76f8e7be6648ecf4ee7dbbceec1 /arch/arm/mach-omap2/omap-smp.c | |
| parent | 21ee0ab5fa80eb7307079e1a126f642fe7a937a6 (diff) | |
| parent | d21872b3683ff37f73c68993749a6e6aeeaed265 (diff) | |
Merge commit 'd21872b'linaro_merge_100811
Diffstat (limited to 'arch/arm/mach-omap2/omap-smp.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap-smp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 1cf52313759..af3c20c8d3f 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -73,9 +73,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ - omap_modify_auxcoreboot0(0x200, 0x0); + omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + smp_cross_call(cpumask_of(cpu)); /* * Now the secondary core is starting up let it run its |