path: root/arch/arm/mach-mx6/cpu.c
diff options
authorRanjani Vaidyanathan <ra5478@freescale.com>2011-11-04 16:19:19 -0500
committerEric Miao <eric.miao@canonical.com>2011-11-10 07:39:07 +0800
commitaaae26e5a7f1d54ae768b4d1efa79602faf5a48d (patch)
treec83c158c2225da92ec41e24e8009ca4381c3506f /arch/arm/mach-mx6/cpu.c
parentc1773f52758dc09e037087b39f3cfc6a47d2f5a8 (diff)
ENGR00161487: Fix SD/USB/FEC performance issue.er3-preview
When WAIT mode is not enabled, execute cpu_do_idle() code. Currently WAIT mode requires the code to be run from IRAM with caches disabled. No L2 cache access should be done for a specified period after the system exits WAIT mode. This delay and running code from IRAM adversely affects the SDHC performance. Hardware team is looking into the extended delay that is required. Till its root caused, default should be to execute cpu_do_idle() and disable entry into WAIT mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/cpu.c')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index 0e85d925dfd..0833b574c30 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -37,7 +37,7 @@ extern void mx6_wait(void);
struct cpu_op *(*get_cpu_op)(int *op);
static void __iomem *arm_base = IO_ADDRESS(MX6Q_A9_PLATFRM_BASE);
-static bool enable_wait_mode;
+bool enable_wait_mode;
void __iomem *gpc_base;
void __iomem *ccm_base;