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| author | Michal Marek <mmarek@suse.cz> | 2011-06-07 15:37:51 +0200 |
|---|---|---|
| committer | Michal Marek <mmarek@suse.cz> | 2011-06-07 15:37:51 +0200 |
| commit | 2e483528cebad089d0bb3f9aebb0ada22d968ffa (patch) | |
| tree | d701405826b271e819a9a8500838cebd37b1364a /arch/arm/mach-lpc32xx/pm.c | |
| parent | 163d3fe6a2357aba7b18b938d6ae6ce9570324e4 (diff) | |
| parent | 55922c9d1b84b89cb946c777fddccb3247e7df2c (diff) | |
Merge commit 'v3.0-rc1' into kbuild/kbuild
Diffstat (limited to 'arch/arm/mach-lpc32xx/pm.c')
| -rw-r--r-- | arch/arm/mach-lpc32xx/pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index e76d41bb705..b9c80597b7b 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -41,7 +41,7 @@ * DRAM clocking and refresh are slightly different for systems with DDR * DRAM or regular SDRAM devices. If SDRAM is used in the system, the * SDRAM will still be accessible in direct-run mode. In DDR based systems, - * a transistion to direct-run mode will stop all DDR accesses (no clocks). + * a transition to direct-run mode will stop all DDR accesses (no clocks). * Because of this, the code to switch power modes and the code to enter * and exit DRAM self-refresh modes must not be executed in DRAM. A small * section of IRAM is used instead for this. |