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authorRichardZhu <richard.zhu@linaro.org>2011-11-16 11:28:50 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-09 20:42:49 +0800
commitc68b33e4d23fbe733becfe6b2264f837e9459613 (patch)
tree400bac09227c6cf45716eebcf276347ed63fac0c
parent6155aface4a5048b6398fe2b5bc33687db9fb26b (diff)
downloadlinux-linaro-c68b33e4d23fbe733becfe6b2264f837e9459613.tar.gz
mmc: sdhci-esdhc-imx: workaround for TC intr coming ealier than DMA intri
On mx6, if TC interrupt bit is set but DMA interrupt bit is clear, read status register again in case DMA interrupt will come in next time cycle. Signed-off-by: Tony Lin <tony.lin@freescale.com> Signed-off-by: RichardZhu <richard.zhu@linaro.org>
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 38ebc4ea259..5888f041ae2 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -170,6 +170,19 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
}
if (unlikely(reg == SDHCI_INT_STATUS)) {
+ if (is_imx6q_usdhc(imx_data)) {
+ /*
+ * on mx6q, there is low possibility that
+ * DATA END interrupt comes ealier than DMA
+ * END interrupt which is conflict with standard
+ * host controller spec. In this case, read the
+ * status register again will workaround this issue.
+ */
+ if ((val & SDHCI_INT_DATA_END) && \
+ !(val & SDHCI_INT_DMA_END))
+ val = readl(host->ioaddr + reg);
+ }
+
if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
val |= SDHCI_INT_ADMA_ERROR;