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authorShawn Guo <shawn.guo@linaro.org>2011-12-30 17:26:40 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-06 12:11:38 +0800
commit6155aface4a5048b6398fe2b5bc33687db9fb26b (patch)
treef2507b6464f3a389207e7451eb8e7090192ddf1c
parent1c7bb81885f56666a4eaf934989c6607120add30 (diff)
downloadlinux-linaro-topic/lt-3.2-imx6-base.tar.gz
ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidationtopic/lt-3.2-imx6-base
The recent suspend/resume and reset testing on imx6q discovers that not only D-Cache but also I-Cache has random data and validity when the core comes out of a power recycle. This patch adds I-Cache invalidation into v7_invalidate_l1 to make sure both D-Cache and I-Cache invalidated on power-up. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org>
-rw-r--r--arch/arm/mach-imx/head-v7.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index cec23a857c7..ea12b0c4a05 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -33,6 +33,7 @@
*/
ENTRY(v7_invalidate_l1)
mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0