diff options
| author | Anson Huang <b20788@freescale.com> | 2011-09-01 17:07:46 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2011-09-01 17:07:46 +0800 |
| commit | ca317a06df0eb316fef53abb1a9f0c82822d4a71 (patch) | |
| tree | 5288b6f9a9a49e43584cb6e9e0cbe26526473e92 | |
| parent | 32dee1ecc3224a8b79e056ff3545070bc38b9b0f (diff) | |
ENGR00155759 [MX6]MMDC clock should be always on
1. We should enable mmdc_ch0 clock in init to make
its usecount > 0, or ipu's parent is mmdc_ch0,
when ipu enable/disable clock, mmdc_ch0 will be
also enable/disable, cause system hang when disable.
2. Remove build warning of unuse variable.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 3a83c772fc6..4a56fd640ee 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -3937,7 +3937,6 @@ static struct clk pcie_clk = { static int _clk_sata_enable(struct clk *clk) { unsigned int reg; - unsigned int cyclecount; /* Clear Power Down and Enable PLLs */ reg = __raw_readl(PLL8_ENET_BASE_ADDR); @@ -4144,6 +4143,10 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_debug_register(lookups[i].clk); } + /* enable mmdc_ch0_axi_clk to make sure the usecount is > 0 + * or ipu's parent is mmdc_ch0_axi_clk, if ipu disable clk, + * mmdc_ch0_axi_clk will also be disabled, system will hang */ + clk_enable(&mmdc_ch0_axi_clk[0]); /* Initialize Audio and Video PLLs to valid frequency (650MHz). */ clk_set_rate(&pll4_audio_main_clk, 650000000); clk_set_rate(&pll5_video_main_clk, 650000000); |