diff options
| author | Huang Shijie <b32955@freescale.com> | 2010-12-17 11:04:48 +0800 |
|---|---|---|
| committer | Robby Cai <R63905@freescale.com> | 2010-12-17 13:46:22 +0800 |
| commit | 26a8bc1b05801eb101edd375dd8305bc2ef4a2f5 (patch) | |
| tree | c396ca408ce93a93da90b971a178419cbbe9795f | |
| parent | b340e1b45c1eb2b93000dccf810cead1096ebdc1 (diff) | |
ENGR00137101-1 clock : keep GPMI and BCH working in the same frequency
add the BCH clock setting, and keep them work in the same
frequncy.
Signed-off-by: Huang Shijie <b32955@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 2 |
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index af9e4e58d7e..87eee08fdbb 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -2458,6 +2458,8 @@ static int gpmi_set_parent(struct clk *clk, struct clk *parent) reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK) | (0x2 << MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK) | + (0x2 << MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); @@ -2479,10 +2481,15 @@ static int gpmi_set_rate(struct clk *clk, unsigned long rate) value /= rate; value /= 2; /* HW_GPMI_CTRL1's GPMI_CLK_DIV2_EN will be set */ + /* set GPMI clock */ reg = __raw_readl(MXC_CCM_GPMI); reg = (reg & ~MXC_CCM_GPMI_CLK_DIV_MASK) | value; - __raw_writel(reg, MXC_CCM_GPMI); + + /* set BCH clock */ + reg = __raw_readl(MXC_CCM_BCH); + reg = (reg & ~MXC_CCM_BCH_CLK_DIV_MASK) | value; + __raw_writel(reg, MXC_CCM_BCH); } else printk(KERN_WARNING "You should not call the %s\n", __func__); return 0; diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 532bcc09920..45db5f60d7b 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -683,6 +683,8 @@ #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK (0x3 << 12) #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET 6 #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET 8 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET 4 #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET 2 |