diff options
| author | Jie Zhou <b30303@freescale.com> | 2010-07-29 17:04:43 +0800 |
|---|---|---|
| committer | Jie Zhou <b30303@freescale.com> | 2010-07-30 15:53:02 +0800 |
| commit | fa1e059caedc746ee4d9d6d236452d4e47d3d264 (patch) | |
| tree | 56c2c321a5a6581ac408cdd0836421586f6695a1 | |
| parent | e8ad323e64eef602ce1cfb0eb654aeac06f060c3 (diff) | |
ENGR00125729-2 GPU: merge hal for MX35/MX50 and MX51/MX53
Add MX508 support, and adapt the gpu driver to one image
Signed-off-by: Jie Zhou <b30303@freescale.com>
20 files changed, 839 insertions, 1897 deletions
diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig index f4f442787de..629d8cbbc98 100644 --- a/drivers/mxc/amd-gpu/Kconfig +++ b/drivers/mxc/amd-gpu/Kconfig @@ -6,7 +6,7 @@ menu "MXC GPU support" config MXC_AMD_GPU tristate "MXC GPU support" - depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 + depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 || ARCH_MX50 ---help--- Say Y to get the GPU driver support. diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile index a661de4d6a7..84cf02e5b3a 100644 --- a/drivers/mxc/amd-gpu/Makefile +++ b/drivers/mxc/amd-gpu/Makefile @@ -25,25 +25,7 @@ gpu-objs += common/gsl_cmdstream.o \ common/gsl_yamato.o \ platform/hal/linux/gsl_linux_map.o \ platform/hal/linux/gsl_kmod.o \ + platform/hal/linux/gsl_hal.o \ platform/hal/linux/gsl_kmod_cleanup.o \ platform/hal/linux/misc.o \ os/kernel/src/linux/kos_lib.o -ifeq ($(CONFIG_ARCH_MX5),y) -EXTRA_CFLAGS += -DMX51=1 \ - -I$(obj)/platform/hal/MX51 \ - -I$(obj)/platform/hal/MX51/linux \ - -I$(obj)/platform/hal/MX51/memcfg - -gpu-objs += platform/hal/MX51/linux/gsl_hal.o \ - platform/hal/MX51/memcfg/gsl_memcfg.o -endif - -ifeq ($(CONFIG_ARCH_MX35),y) -EXTRA_CFLAGS += -DMX35=1 \ - -I$(obj)/platform/hal/MX35 \ - -I$(obj)/platform/hal/MX35/linux \ - -I$(obj)/platform/hal/MX35/memcfg - -gpu-objs += platform/hal/MX35/linux/gsl_hal.o \ - platform/hal/MX35/memcfg/gsl_memcfg.o -endif diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c index bcb557e69d6..0aedf1154be 100644 --- a/drivers/mxc/amd-gpu/common/gsl_device.c +++ b/drivers/mxc/amd-gpu/common/gsl_device.c @@ -161,6 +161,10 @@ kgsl_device_close(gsl_device_t *device) kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device ); + if (!(device->flags & GSL_FLAGS_INITIALIZED)) { + return status; + } + /* make sure the device is stopped before close kgsl_device_close is only called for last running caller process */ @@ -174,12 +178,8 @@ kgsl_device_close(gsl_device_t *device) status = kgsl_cmdstream_close(device); if( status != GSL_SUCCESS ) return status; - if (device->flags & GSL_FLAGS_INITIALIZED) - { - if (device->ftbl.device_close) - { - status = device->ftbl.device_close(device); - } + if (device->ftbl.device_close) { + status = device->ftbl.device_close(device); } // DumpX allocates memstore from MMU aperture diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c index fd4bcc0df96..1d1564022b1 100644 --- a/drivers/mxc/amd-gpu/common/gsl_driver.c +++ b/drivers/mxc/amd-gpu/common/gsl_driver.c @@ -203,7 +203,7 @@ kgsl_driver_entry(gsl_flags_t flags) status = kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1)); if (status != GSL_SUCCESS) { - break; + continue; } } } diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h index 82824f511d5..cda8dae511f 100644 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_buildconfig.h +++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h @@ -26,6 +26,10 @@ * */ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + #ifndef __GSL__BUILDCONFIG_H #define __GSL__BUILDCONFIG_H @@ -41,22 +45,12 @@ #define GSL_RB_USE_MEM_RPTR #define GSL_RB_USE_MEM_TIMESTAMP #define GSL_RB_TIMESTAMP_INTERUPT -//#define GSL_RB_USE_WPTR_POLLING +/* #define GSL_RB_USE_WPTR_POLLING */ -#if defined(_WIN32_WCE) && (_WIN32_WCE >= 600) -#define GSL_DEVICE_SHADOW_MEMSTORE_TO_USER -#endif - -//#define GSL_MMU_TRANSLATION_ENABLED -//#define GSL_MMU_PAGETABLE_PERPROCESS +/* #define GSL_MMU_TRANSLATION_ENABLED */ +/* #define GSL_MMU_PAGETABLE_PERPROCESS */ #define GSL_CALLER_PROCESS_MAX 10 #define GSL_SHMEM_MAX_APERTURES 3 -#ifdef _WIN32 -#ifndef _CRT_SECURE_NO_DEPRECATE -#define _CRT_SECURE_NO_DEPRECATE -#endif -#endif // _WIN32 - -#endif // __GSL__BUILDCONFIG_H +#endif /* __GSL__BUILDCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_config.h b/drivers/mxc/amd-gpu/include/gsl_config.h new file mode 100644 index 00000000000..aa911b4096a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_config.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL__CONFIG_H +#define __GSL__CONFIG_H + +/* ------------------------ + * Yamato ringbuffer config + * ------------------------ */ +static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K; +static const unsigned int gsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16; + +/* ------------------------ + * Yamato MH arbiter config + * ------------------------ */ +static const mh_arbiter_config_t gsl_cfg_yamato_mharb = { + 0x10, /* same_page_limit */ + 0, /* same_page_granularity */ + 1, /* l1_arb_enable */ + 1, /* l1_arb_hold_enable */ + 0, /* l2_arb_control */ + 1, /* page_size */ + 1, /* tc_reorder_enable */ + 1, /* tc_arb_hold_enable */ + 1, /* in_flight_limit_enable */ + 0x8, /* in_flight_limit */ + 1, /* cp_clnt_enable */ + 1, /* vgt_clnt_enable */ + 1, /* tc_clnt_enable */ + 1, /* rb_clnt_enable */ + 1, /* pa_clnt_enable */ +}; + +/* --------------------- + * G12 MH arbiter config + * --------------------- */ +static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = { + 0x10, /* SAME_PAGE_LIMIT */ + 0, /* SAME_PAGE_GRANULARITY */ + 1, /* L1_ARB_ENABLE */ + 1, /* L1_ARB_HOLD_ENABLE */ + 0, /* L2_ARB_CONTROL */ + 1, /* PAGE_SIZE */ + 1, /* TC_REORDER_ENABLE */ + 1, /* TC_ARB_HOLD_ENABLE */ + 0, /* IN_FLIGHT_LIMIT_ENABLE */ + 0x8, /* IN_FLIGHT_LIMIT */ + 1, /* CP_CLNT_ENABLE */ + 1, /* VGT_CLNT_ENABLE */ + 1, /* TC_CLNT_ENABLE */ + 1, /* RB_CLNT_ENABLE */ + 1, /* PA_CLNT_ENABLE */ +}; + +/* ----------------------------- + * interrupt block register data + * ----------------------------- */ +static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = { + { /* Yamato MH */ + GSL_INTR_BLOCK_YDX_MH, + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + mmMH_INTERRUPT_STATUS, + mmMH_INTERRUPT_CLEAR, + mmMH_INTERRUPT_MASK + }, + { /* Yamato CP */ + GSL_INTR_BLOCK_YDX_CP, + GSL_INTR_YDX_CP_SW_INT, + GSL_INTR_YDX_CP_RING_BUFFER, + mmCP_INT_STATUS, + mmCP_INT_ACK, + mmCP_INT_CNTL + }, + { /* Yamato RBBM */ + GSL_INTR_BLOCK_YDX_RBBM, + GSL_INTR_YDX_RBBM_READ_ERROR, + GSL_INTR_YDX_RBBM_GUI_IDLE, + mmRBBM_INT_STATUS, + mmRBBM_INT_ACK, + mmRBBM_INT_CNTL + }, + { /* Yamato SQ */ + GSL_INTR_BLOCK_YDX_SQ, + GSL_INTR_YDX_SQ_PS_WATCHDOG, + GSL_INTR_YDX_SQ_VS_WATCHDOG, + mmSQ_INT_STATUS, + mmSQ_INT_ACK, + mmSQ_INT_CNTL + }, + { /* G12 */ + GSL_INTR_BLOCK_G12, + GSL_INTR_G12_MH, +#ifndef _Z180 + GSL_INTR_G12_FBC, +#else + GSL_INTR_G12_FIFO, +#endif /* _Z180 */ + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQENABLE >> 2) + }, + { /* G12 MH */ + GSL_INTR_BLOCK_G12_MH, + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + ADDR_MH_INTERRUPT_STATUS, /* G12 MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_INTERRUPT_CLEAR, + ADDR_MH_INTERRUPT_MASK + }, +}; + +/* ----------------------- + * interrupt mask bit data + * ----------------------- */ +static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = { + MH_INTERRUPT_MASK__AXI_READ_ERROR, + MH_INTERRUPT_MASK__AXI_WRITE_ERROR, + MH_INTERRUPT_MASK__MMU_PAGE_FAULT, + + CP_INT_CNTL__SW_INT_MASK, + CP_INT_CNTL__T0_PACKET_IN_IB_MASK, + CP_INT_CNTL__OPCODE_ERROR_MASK, + CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK, + CP_INT_CNTL__RESERVED_BIT_ERROR_MASK, + CP_INT_CNTL__IB_ERROR_MASK, + CP_INT_CNTL__IB2_INT_MASK, + CP_INT_CNTL__IB1_INT_MASK, + CP_INT_CNTL__RB_INT_MASK, + + RBBM_INT_CNTL__RDERR_INT_MASK, + RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK, + RBBM_INT_CNTL__GUI_IDLE_INT_MASK, + + SQ_INT_CNTL__PS_WATCHDOG_MASK, + SQ_INT_CNTL__VS_WATCHDOG_MASK, + + (1 << VGC_IRQENABLE_MH_FSHIFT), + (1 << VGC_IRQENABLE_G2D_FSHIFT), + (1 << VGC_IRQENABLE_FIFO_FSHIFT), +#ifndef _Z180 + (1 << VGC_IRQENABLE_FBC_FSHIFT), +#endif + (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT), +}; + +/* ----------------- + * mmu register data + * ----------------- */ +static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = { + { /* Yamato */ + mmMH_MMU_CONFIG, + mmMH_MMU_MPU_BASE, + mmMH_MMU_MPU_END, + mmMH_MMU_VA_RANGE, + mmMH_MMU_PT_BASE, + mmMH_MMU_PAGE_FAULT, + mmMH_MMU_TRAN_ERROR, + mmMH_MMU_INVALIDATE, + }, + { /* G12 - MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_MMU_CONFIG, + ADDR_MH_MMU_MPU_BASE, + ADDR_MH_MMU_MPU_END, + ADDR_MH_MMU_VA_RANGE, + ADDR_MH_MMU_PT_BASE, + ADDR_MH_MMU_PAGE_FAULT, + ADDR_MH_MMU_TRAN_ERROR, + ADDR_MH_MMU_INVALIDATE, + }, +}; + +/* ----------------- + * mh interrupt data + * ----------------- */ +static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] = +{ + { /* Yamato */ + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_AXI_WRITE_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + }, + { /* G12 */ + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_AXI_WRITE_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + } +}; + +#endif /* __GSL__CONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h index 8a8a10cfb86..fa26b1f2311 100644 --- a/drivers/mxc/amd-gpu/include/gsl_hal.h +++ b/drivers/mxc/amd-gpu/include/gsl_hal.h @@ -132,7 +132,6 @@ KGSLHAL_API int kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config); KGSLHAL_API int kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config); KGSLHAL_API int kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value); KGSLHAL_API gsl_chipid_t kgsl_hal_getchipid(gsl_deviceid_t device_id); -KGSLHAL_API int kgsl_hal_getplatformtype(char *platform); KGSLHAL_API int kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); KGSLHAL_API int kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h index 9cfe9fe5b3b..64f48e9d068 100644..100755 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_buildconfig.h +++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h @@ -26,37 +26,26 @@ * */ -#ifndef __GSL__BUILDCONFIG_H -#define __GSL__BUILDCONFIG_H - -#define GSL_BLD_G12 - -#define GSL_LOCKING_COURSEGRAIN -#define GSL_MMU_TRANSLATION_ENABLED -//#define GSL_MMU_PAGETABLE_PERPROCESS - -#if defined(_WIN32_WCE) && (_WIN32_WCE >= 600) -#define GSL_DEVICE_SHADOW_MEMSTORE_TO_USER -#endif - -//#define GSL_LOG - -#define GSL_STATS_MEM -#define GSL_STATS_RINGBUFFER -#define GSL_STATS_MMU +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ -#define GSL_RB_USE_MEM_RPTR -#define GSL_RB_USE_MEM_TIMESTAMP -//#define GSL_RB_USE_WPTR_POLLING +#ifndef __GSL_HALCONFIG_H +#define __GSL_HALCONFIG_H +#define GSL_HAL_GPUBASE_REG_YDX 0x30000000 +#define GSL_HAL_SIZE_REG_YDX 0x00020000 /* 128KB */ -#define GSL_CALLER_PROCESS_MAX 10 -#define GSL_SHMEM_MAX_APERTURES 3 +#define GSL_HAL_SIZE_REG_G12 0x00001000 /* 4KB */ -#ifdef _WIN32 -#ifndef _CRT_SECURE_NO_DEPRECATE -#define _CRT_SECURE_NO_DEPRECATE +#if defined(GSL_MMU_TRANSLATION_ENABLED) +#define GSL_HAL_SHMEM_SIZE_EMEM1 0x01800000 /* 24MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00400000 /* 4MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS 0x00400000 /* 4MB */ +#else +#define GSL_HAL_SHMEM_SIZE_EMEM1 0x00D00000 /* 13MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00200000 /* 2MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS 0x00100000 /* 1MB */ #endif -#endif // _WIN32 -#endif // __GSL__BUILDCONFIG_H +#endif /* __GSL_HALCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h deleted file mode 100644 index 58a38c608de..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_config.h +++ /dev/null @@ -1,195 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __GSL__CONFIG_H -#define __GSL__CONFIG_H - - -// --------------------- -// G12 MH arbiter config -// --------------------- -static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = -{ - 0x10, // SAME_PAGE_LIMIT - 0, // SAME_PAGE_GRANULARITY - 1, // L1_ARB_ENABLE - 1, // L1_ARB_HOLD_ENABLE - 0, // L2_ARB_CONTROL - 1, // PAGE_SIZE - 1, // TC_REORDER_ENABLE - 1, // TC_ARB_HOLD_ENABLE - 0, // IN_FLIGHT_LIMIT_ENABLE - 0x8, // IN_FLIGHT_LIMIT - 1, // CP_CLNT_ENABLE - 1, // VGT_CLNT_ENABLE - 1, // TC_CLNT_ENABLE - 1, // RB_CLNT_ENABLE - 1, // PA_CLNT_ENABLE -}; - -// ----------------------------- -// interrupt block register data -// ----------------------------- -static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = -{ - { // Yamato MH - 0, - 0, - 0, - 0, - 0, - 0 - }, - { // Yamato CP - 0, - 0, - 0, - 0, - 0, - 0 - }, - { // Yamato RBBM - 0, - 0, - 0, - 0, - 0, - 0 - }, - { // Yamato SQ - 0, - 0, - 0, - 0, - 0, - 0 - }, - { // G12 - GSL_INTR_BLOCK_G12, - GSL_INTR_G12_MH, -#ifndef _Z180 - GSL_INTR_G12_FBC, -#else - GSL_INTR_G12_FIFO, -#endif //_Z180 - (ADDR_VGC_IRQSTATUS >> 2), - (ADDR_VGC_IRQSTATUS >> 2), - (ADDR_VGC_IRQENABLE >> 2) - }, - { // G12 MH - GSL_INTR_BLOCK_G12_MH, - GSL_INTR_G12_MH_AXI_READ_ERROR, - GSL_INTR_G12_MH_MMU_PAGE_FAULT, - ADDR_MH_INTERRUPT_STATUS, // G12 MH offsets are considered to be dword based, therefore no down shift - ADDR_MH_INTERRUPT_CLEAR, - ADDR_MH_INTERRUPT_MASK - }, -}; - -// ----------------------- -// interrupt mask bit data -// ----------------------- -static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = -{ - 0, - 0, - 0, - - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - - 0, - 0, - 0, - - 0, - 0, - - (1 << VGC_IRQENABLE_MH_FSHIFT), - (1 << VGC_IRQENABLE_G2D_FSHIFT), - (1 << VGC_IRQENABLE_FIFO_FSHIFT), -#ifndef _Z180 - (1 << VGC_IRQENABLE_FBC_FSHIFT), -#endif - 0, - 0, - 0, -}; - -// ----------------- -// mmu register data -// ----------------- -static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = -{ - { // Yamato - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - }, - { // G12 - MH offsets are considered to be dword based, therefore no down shift - ADDR_MH_MMU_CONFIG, - ADDR_MH_MMU_MPU_BASE, - ADDR_MH_MMU_MPU_END, - ADDR_MH_MMU_VA_RANGE, - ADDR_MH_MMU_PT_BASE, - ADDR_MH_MMU_PAGE_FAULT, - ADDR_MH_MMU_TRAN_ERROR, - ADDR_MH_MMU_INVALIDATE, - } -}; - -// ----------------- -// mh interrupt data -// ----------------- -static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] = -{ - { // Yamato - 0, - 0, - 0, - }, - { // G12 - GSL_INTR_G12_MH_AXI_READ_ERROR, - GSL_INTR_G12_MH_AXI_WRITE_ERROR, - GSL_INTR_G12_MH_MMU_PAGE_FAULT, - } -}; - -#endif // __GSL__CONFIG_H diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h deleted file mode 100644 index 01104123601..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/gsl_halconfig.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __GSL_HALCONFIG_H -#define __GSL_HALCONFIG_H - - - -#define GSL_HAL_PLATFORM "i.MX35G" - - -#define GSL_HAL_GPUBASE_GMEM 0x00100000 // 1MB -#define GSL_HAL_GPUBASE_GMEM_PHYS 0x20000000 // 1MB - -#define GSL_HAL_GPUBASE_REG_YDX 0x30000000 -#define GSL_HAL_GPUBASE_REG_G12 0x20000000 - -#define GSL_HAL_SIZE_REG_YDX 0x00020000 // 128KB -#define GSL_HAL_SIZE_REG_G12 0x00001000 // 4KB -#define GSL_HAL_SIZE_GMEM 0x00040000 // 256KB - 0 to 384KB in 128KB increments - -#if defined(_LINUX) && defined(GSL_MMU_TRANSLATION_ENABLED) -#define GSL_HAL_SHMEM_SIZE_EMEM1 0x02400000 // 36MB -#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00400000 // 4MB -#define GSL_HAL_SHMEM_SIZE_PHYS 0x00400000 // 4MB -#elif defined(_LINUX) //MX35 Linux can able to allocate only 4MB -#define GSL_HAL_SHMEM_SIZE_EMEM1 0x00400000 // 4MB -#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00200000 // 2MB -#define GSL_HAL_SHMEM_SIZE_PHYS 0x00200000 // 2MB -#else //Not possible to allocate 24 MB on WinCE -#define GSL_HAL_SHMEM_SIZE_EMEM1 0x00D00000 // 13MB -#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00200000 // 2MB -#define GSL_HAL_SHMEM_SIZE_PHYS 0x00100000 // 1MB -#endif - -#define MX35_G12_INTERRUPT 16 - -#endif // __GSL_HALCONFIG_H diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c deleted file mode 100644 index 294cd9eb5af..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/linux/gsl_hal.c +++ /dev/null @@ -1,524 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ - -#include "gsl_hal.h" -#include "gsl_halconfig.h" -#include "gsl_linux_map.h" - -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/vmalloc.h> - -#include <asm/atomic.h> -#include <asm/uaccess.h> -#include <asm/tlbflush.h> -#include <asm/cacheflush.h> - -////////////////////////////////////////////////////////////////////////////// -// constants -////////////////////////////////////////////////////////////////////////////// - - -////////////////////////////////////////////////////////////////////////////// -// defines -////////////////////////////////////////////////////////////////////////////// - -#define GSL_HAL_MEM1 0 -#define GSL_HAL_MEM2 1 -#define GSL_HAL_MEM3 2 - -//#define GSL_HAL_DEBUG -////////////////////////////////////////////////////////////////////////////// -// types -////////////////////////////////////////////////////////////////////////////// - -typedef struct _gsl_hal_t { - gsl_memregion_t z160_regspace; -#if 0 - gsl_memregion_t z430_regspace; -#endif - gsl_memregion_t memchunk; - gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES]; -} gsl_hal_t; - -////////////////////////////////////////////////////////////////////////////// -// functions -////////////////////////////////////////////////////////////////////////////// - -KGSLHAL_API int -kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) -{ - // - // allocate physically contiguous memory - // - - int i; - void *va; - - va = (void*)gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE); - - if (!va) - return (GSL_FAILURE_OUTOFMEM); - - for(i = 0; i < numpages; i++) - { - scattergatterlist[i] = page_to_phys(vmalloc_to_page(va)); - va += PAGE_SIZE; - } - - return (GSL_SUCCESS); -} - -// --------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) -{ - // - // free physical memory - // - - gsl_linux_map_free(virtaddr); - - return(GSL_SUCCESS); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_init(void) -{ - gsl_hal_t *hal; - unsigned long totalsize, mem1size; - unsigned int va, pa; - - if (gsl_driver.hal) - { - return (GSL_FAILURE_ALREADYINITIALIZED); - } - - gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t)); - - if (!gsl_driver.hal) - { - return (GSL_FAILURE_OUTOFMEM); - } - - kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t)); - - - // overlay structure on hal memory - hal = (gsl_hal_t *) gsl_driver.hal; - -#if 0 - // setup register space - hal->z430_regspace.mmio_phys_base = GSL_HAL_GPUBASE_REG_YDX; - hal->z430_regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; - hal->z430_regspace.mmio_virt_base = (unsigned char*)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes); - - if (hal->z430_regspace.mmio_virt_base == NULL) - { - return (GSL_FAILURE_SYSTEMERROR); - } - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_phys_base); - printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_virt_base); - printk(KERN_INFO "%s: hal->z430_regspace.sizebytes = 0x%08x\n", __func__, hal->z430_regspace.sizebytes); -#endif -#endif - - hal->z160_regspace.mmio_phys_base = GSL_HAL_GPUBASE_REG_G12; - hal->z160_regspace.sizebytes = GSL_HAL_SIZE_REG_G12; - hal->z160_regspace.mmio_virt_base = (unsigned char*)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes); - - if (hal->z160_regspace.mmio_virt_base == NULL) - { - return (GSL_FAILURE_SYSTEMERROR); - } - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_phys_base); - printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_virt_base); - printk(KERN_INFO "%s: hal->z160_regspace.sizebytes = 0x%08x\n", __func__, hal->z160_regspace.sizebytes); -#endif - -#ifdef GSL_MMU_TRANSLATION_ENABLED - totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; - mem1size = GSL_HAL_SHMEM_SIZE_EMEM1; -#else - totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; - mem1size = GSL_HAL_SHMEM_SIZE_EMEM1; -#endif - - // allocate a single chunk of physical memory - va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); - - if (va) - { - kos_memset((void *)va, 0, totalsize); - - hal->memchunk.mmio_virt_base = (void *)va; - hal->memchunk.mmio_phys_base = pa; - hal->memchunk.sizebytes = totalsize; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_phys_base); - printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_virt_base); - printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes); -#endif - - hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM2].gpu_base = pa; - hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2; - va += GSL_HAL_SHMEM_SIZE_EMEM2; - pa += GSL_HAL_SHMEM_SIZE_EMEM2; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes); -#endif - - hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM3].gpu_base = pa; - hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS; - va += GSL_HAL_SHMEM_SIZE_PHYS; - pa += GSL_HAL_SHMEM_SIZE_PHYS; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes); -#endif - -#ifdef GSL_MMU_TRANSLATION_ENABLED - gsl_linux_map_init(); - hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START; - hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START; - hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; -#else - hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM1].gpu_base = pa; - hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; -#endif - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes); -#endif - } - else - { - kgsl_hal_close(); - return (GSL_FAILURE_SYSTEMERROR); - } - - return GSL_SUCCESS; -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_close(void) -{ - gsl_hal_t *hal; - - if (gsl_driver.hal) - { - // overlay structure on hal memory - hal = (gsl_hal_t *) gsl_driver.hal; - - // unmap registers -#if 0 - if (hal->z430_regspace.mmio_virt_base) - { - iounmap(hal->z430_regspace.mmio_virt_base); - } -#endif - if (hal->z160_regspace.mmio_virt_base) - { - iounmap(hal->z160_regspace.mmio_virt_base); - } - - // free physical block - if (hal->memchunk.mmio_virt_base) - { - dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base); - } - -#ifdef GSL_MMU_TRANSLATION_ENABLED - gsl_linux_map_destroy(); -#endif - - // release hal struct - kos_memset(hal, 0, sizeof(gsl_hal_t)); - kos_free(gsl_driver.hal); - gsl_driver.hal = NULL; - } - - return (GSL_SUCCESS); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config) -{ - int status = GSL_FAILURE_DEVICEERROR; - gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; - - kos_memset(config, 0, sizeof(gsl_shmemconfig_t)); - - if (hal) - { - config->numapertures = GSL_SHMEM_MAX_APERTURES; - -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->apertures[0].id = GSL_APERTURE_MMU; -#else - config->apertures[0].id = GSL_APERTURE_EMEM; -#endif - config->apertures[0].channel = GSL_CHANNEL_1; - config->apertures[0].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base; - config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes; - - config->apertures[1].id = GSL_APERTURE_EMEM; - config->apertures[1].channel = GSL_CHANNEL_2; - config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base; - config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base; - config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes; - - config->apertures[2].id = GSL_APERTURE_PHYS; - config->apertures[2].channel = GSL_CHANNEL_1; - config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base; - config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base; - config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes; - - status = GSL_SUCCESS; - } - - return (status); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config) -{ - int status = GSL_FAILURE_DEVICEERROR; - gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; - - kos_memset(config, 0, sizeof(gsl_devconfig_t)); - - if (hal) - { - switch (device_id) - { - case GSL_DEVICE_YAMATO: - { -#if 0 - mh_mmu_config_u mmu_config = {0}; - - config->gmemspace.gpu_base = 0; - config->gmemspace.mmio_virt_base = 0; - config->gmemspace.mmio_phys_base = 0; - config->gmemspace.sizebytes = GSL_HAL_SIZE_GMEM; - - config->regspace.gpu_base = 0; - config->regspace.mmio_virt_base = (unsigned char *)hal->z430_regspace.mmio_virt_base; - config->regspace.mmio_phys_base = (unsigned int) hal->z430_regspace.mmio_phys_base; - config->regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; - - mmu_config.f.mmu_enable = 1; -#ifdef GSL_MMU_TRANSLATION_ENABLED - mmu_config.f.split_mode_enable = 0; - mmu_config.f.rb_w_clnt_behavior = 1; - mmu_config.f.cp_w_clnt_behavior = 1; - mmu_config.f.cp_r0_clnt_behavior = 1; - mmu_config.f.cp_r1_clnt_behavior = 1; - mmu_config.f.cp_r2_clnt_behavior = 1; - mmu_config.f.cp_r3_clnt_behavior = 1; - mmu_config.f.cp_r4_clnt_behavior = 1; - mmu_config.f.vgt_r0_clnt_behavior = 1; - mmu_config.f.vgt_r1_clnt_behavior = 1; - mmu_config.f.tc_r_clnt_behavior = 1; - mmu_config.f.pa_w_clnt_behavior = 1; -#endif // GSL_MMU_TRANSLATION_ENABLED - - config->mmu_config = mmu_config.val; -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; -#else - config->va_base = 0x00000000; - config->va_range = 0x00000000; -#endif // GSL_MMU_TRANSLATION_ENABLED - - // turn off memory protection unit by setting acceptable physical address range to include all pages - config->mpu_base = 0x00000000; // hal->memchunk.mmio_virt_base; - config->mpu_range = 0xFFFFF000; // hal->memchunk.sizebytes; - - status = GSL_SUCCESS; -#endif - break; - } - - case GSL_DEVICE_G12: - { -#ifndef GSL_MMU_TRANSLATION_ENABLED - unsigned int mmu_config = {0}; -#endif - config->regspace.gpu_base = 0; - config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base; - config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base; - config->regspace.sizebytes = GSL_HAL_SIZE_REG_G12; - - - -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->mmu_config = 0x00555551; - config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; -#else - config->mmu_config = mmu_config; - config->va_base = 0x00000000; - config->va_range = 0x00000000; -#endif // GSL_MMU_TRANSLATION_ENABLED - - config->mpu_base = 0x00000000; //(unsigned int) hal->memchunk.mmio_virt_base; - config->mpu_range = 0xFFFFF000; //hal->memchunk.sizebytes; - - status = GSL_SUCCESS; - break; - } - - default: - - break; - } - } - - return (status); -} - -//---------------------------------------------------------------------------- -// -// kgsl_hal_getchipid -// -// The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE -// -KGSLHAL_API gsl_chipid_t -kgsl_hal_getchipid(gsl_deviceid_t device_id) -{ - return (0); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getplatformtype(char *platform) -{ - if (gsl_driver.hal) - { - kos_strcpy(platform, GSL_HAL_PLATFORM); - return (GSL_SUCCESS); - } - else - { - return (GSL_FAILURE_NOTINITIALIZED); - } -} - -//--------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value) -{ - gsl_device_t *device = &gsl_driver.device[device_id-1]; // device_id is 1 based - struct clk *gpu_clk = 0; - - // unreferenced formal parameters - (void) value; - - switch (device_id) - { - case GSL_DEVICE_G12: - gpu_clk = clk_get(0, "gpu2d_clk"); - break; - default: - return (GSL_FAILURE_DEVICEERROR); - } - - if (!gpu_clk) - return (GSL_FAILURE_DEVICEERROR); - - switch (state) - { - case GSL_PWRFLAGS_CLK_ON: - break; - case GSL_PWRFLAGS_POWER_ON: - clk_enable(gpu_clk); - kgsl_device_autogate_init(&gsl_driver.device[device_id-1]); - break; - case GSL_PWRFLAGS_CLK_OFF: - break; - case GSL_PWRFLAGS_POWER_OFF: - if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) - { - return (GSL_FAILURE_DEVICEERROR); - } - kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]); - clk_disable(gpu_clk); - break; - default: - break; - } - - return (GSL_SUCCESS); -} - -KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable) -{ - struct clk *gpu_clk = 0; - - switch (dev) - { - case GSL_DEVICE_G12: - gpu_clk = clk_get(0, "gpu2d_clk"); - break; - default: - printk(KERN_ERR "GPU device %d is invalid!\n", dev); - return (GSL_FAILURE_DEVICEERROR); - } - - if (IS_ERR(gpu_clk)) { - printk(KERN_ERR "%s: GPU clock get failed!\n", __func__); - return (GSL_FAILURE_DEVICEERROR); - } - - if (enable) - clk_enable(gpu_clk); - else - clk_disable(gpu_clk); - - return (GSL_SUCCESS); -} diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c deleted file mode 100644 index f3ca6191d7c..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.c +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ - -#include "kos_libapi.h" - -// -// Return the maximum amount of memory that can be allocated to the Z160. This number -// will be constrained to 2MB as a minimum and the original hardcoded value for the caller -// as a maximum. If the return value is outside of this range, then the original value in -// the caller will be used. For this reason, returning 0 is used to signify to use the -// original value as the default. -// -KOS_DLLEXPORT unsigned long kgsl_get_z160_memory_amount(void) -{ - return(0); -} diff --git a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h b/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h deleted file mode 100644 index 164a17c925c..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX35/memcfg/gsl_memcfg.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef GSL_MEMCFG_H -#define GSL_MEMCFG_H - -// -// Return the maximum amount of memory that can be allocated to the Z430. This number -// will be constrained to 2MB as a minimum and the original hardcoded value for the caller -// as a maximum. If the return value is outside of this range, then the original value in -// the caller will be used. For this reason, returning 0 is used to signify to use the -// original value as the default. -// -KOS_DLLEXPORT unsigned long kgsl_get_z160_memory_amount(void); - -#endif diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h deleted file mode 100644 index 6fad1d01277..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_config.h +++ /dev/null @@ -1,222 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __GSL__CONFIG_H -#define __GSL__CONFIG_H - -// ------------------------ -// Yamato ringbuffer config -// ------------------------ -static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K; -static const unsigned int gsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16; - -// ------------------------ -// Yamato MH arbiter config -// ------------------------ -static const mh_arbiter_config_t gsl_cfg_yamato_mharb = -{ - 0x10, // same_page_limit - 0, // same_page_granularity - 1, // l1_arb_enable - 1, // l1_arb_hold_enable - 0, // l2_arb_control - 1, // page_size - 1, // tc_reorder_enable - 1, // tc_arb_hold_enable - 1, // in_flight_limit_enable - 0x8, // in_flight_limit - 1, // cp_clnt_enable - 1, // vgt_clnt_enable - 1, // tc_clnt_enable - 1, // rb_clnt_enable - 1, // pa_clnt_enable -}; - -// --------------------- -// G12 MH arbiter config -// --------------------- -static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = -{ - 0x10, // SAME_PAGE_LIMIT - 0, // SAME_PAGE_GRANULARITY - 1, // L1_ARB_ENABLE - 1, // L1_ARB_HOLD_ENABLE - 0, // L2_ARB_CONTROL - 1, // PAGE_SIZE - 1, // TC_REORDER_ENABLE - 1, // TC_ARB_HOLD_ENABLE - 0, // IN_FLIGHT_LIMIT_ENABLE - 0x8, // IN_FLIGHT_LIMIT - 1, // CP_CLNT_ENABLE - 1, // VGT_CLNT_ENABLE - 1, // TC_CLNT_ENABLE - 1, // RB_CLNT_ENABLE - 1, // PA_CLNT_ENABLE -}; - -// ----------------------------- -// interrupt block register data -// ----------------------------- -static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = -{ - { // Yamato MH - GSL_INTR_BLOCK_YDX_MH, - GSL_INTR_YDX_MH_AXI_READ_ERROR, - GSL_INTR_YDX_MH_MMU_PAGE_FAULT, - mmMH_INTERRUPT_STATUS, - mmMH_INTERRUPT_CLEAR, - mmMH_INTERRUPT_MASK - }, - { // Yamato CP - GSL_INTR_BLOCK_YDX_CP, - GSL_INTR_YDX_CP_SW_INT, - GSL_INTR_YDX_CP_RING_BUFFER, - mmCP_INT_STATUS, - mmCP_INT_ACK, - mmCP_INT_CNTL - }, - { // Yamato RBBM - GSL_INTR_BLOCK_YDX_RBBM, - GSL_INTR_YDX_RBBM_READ_ERROR, - GSL_INTR_YDX_RBBM_GUI_IDLE, - mmRBBM_INT_STATUS, - mmRBBM_INT_ACK, - mmRBBM_INT_CNTL - }, - { // Yamato SQ - GSL_INTR_BLOCK_YDX_SQ, - GSL_INTR_YDX_SQ_PS_WATCHDOG, - GSL_INTR_YDX_SQ_VS_WATCHDOG, - mmSQ_INT_STATUS, - mmSQ_INT_ACK, - mmSQ_INT_CNTL - }, - { // G12 - GSL_INTR_BLOCK_G12, - GSL_INTR_G12_MH, -#ifndef _Z180 - GSL_INTR_G12_FBC, -#else - GSL_INTR_G12_FIFO, -#endif //_Z180 - (ADDR_VGC_IRQSTATUS >> 2), - (ADDR_VGC_IRQSTATUS >> 2), - (ADDR_VGC_IRQENABLE >> 2) - }, - { // G12 MH - GSL_INTR_BLOCK_G12_MH, - GSL_INTR_G12_MH_AXI_READ_ERROR, - GSL_INTR_G12_MH_MMU_PAGE_FAULT, - ADDR_MH_INTERRUPT_STATUS, // G12 MH offsets are considered to be dword based, therefore no down shift - ADDR_MH_INTERRUPT_CLEAR, - ADDR_MH_INTERRUPT_MASK - }, -}; - -// ----------------------- -// interrupt mask bit data -// ----------------------- -static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = -{ - MH_INTERRUPT_MASK__AXI_READ_ERROR, - MH_INTERRUPT_MASK__AXI_WRITE_ERROR, - MH_INTERRUPT_MASK__MMU_PAGE_FAULT, - - CP_INT_CNTL__SW_INT_MASK, - CP_INT_CNTL__T0_PACKET_IN_IB_MASK, - CP_INT_CNTL__OPCODE_ERROR_MASK, - CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK, - CP_INT_CNTL__RESERVED_BIT_ERROR_MASK, - CP_INT_CNTL__IB_ERROR_MASK, - CP_INT_CNTL__IB2_INT_MASK, - CP_INT_CNTL__IB1_INT_MASK, - CP_INT_CNTL__RB_INT_MASK, - - RBBM_INT_CNTL__RDERR_INT_MASK, - RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK, - RBBM_INT_CNTL__GUI_IDLE_INT_MASK, - - SQ_INT_CNTL__PS_WATCHDOG_MASK, - SQ_INT_CNTL__VS_WATCHDOG_MASK, - - (1 << VGC_IRQENABLE_MH_FSHIFT), - (1 << VGC_IRQENABLE_G2D_FSHIFT), - (1 << VGC_IRQENABLE_FIFO_FSHIFT), -#ifndef _Z180 - (1 << VGC_IRQENABLE_FBC_FSHIFT), -#endif - (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT), - (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT), - (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT), -}; - -// ----------------- -// mmu register data -// ----------------- -static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = -{ - { // Yamato - mmMH_MMU_CONFIG, - mmMH_MMU_MPU_BASE, - mmMH_MMU_MPU_END, - mmMH_MMU_VA_RANGE, - mmMH_MMU_PT_BASE, - mmMH_MMU_PAGE_FAULT, - mmMH_MMU_TRAN_ERROR, - mmMH_MMU_INVALIDATE, - }, - { // G12 - MH offsets are considered to be dword based, therefore no down shift - ADDR_MH_MMU_CONFIG, - ADDR_MH_MMU_MPU_BASE, - ADDR_MH_MMU_MPU_END, - ADDR_MH_MMU_VA_RANGE, - ADDR_MH_MMU_PT_BASE, - ADDR_MH_MMU_PAGE_FAULT, - ADDR_MH_MMU_TRAN_ERROR, - ADDR_MH_MMU_INVALIDATE, - } -}; - -// ----------------- -// mh interrupt data -// ----------------- -static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] = -{ - { // Yamato - GSL_INTR_YDX_MH_AXI_READ_ERROR, - GSL_INTR_YDX_MH_AXI_WRITE_ERROR, - GSL_INTR_YDX_MH_MMU_PAGE_FAULT, - }, - { // G12 - GSL_INTR_G12_MH_AXI_READ_ERROR, - GSL_INTR_G12_MH_AXI_WRITE_ERROR, - GSL_INTR_G12_MH_MMU_PAGE_FAULT, - } -}; - -#endif // __GSL__CONFIG_H diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h b/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h deleted file mode 100644 index 589c56fa9bf..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/gsl_halconfig.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __GSL_HALCONFIG_H -#define __GSL_HALCONFIG_H - - -#define GSL_HAL_PLATFORM "i.MX51" - -#define GSL_HAL_GPUBASE_GMEM 0x00100000 // 1MB -#define GSL_HAL_GPUBASE_GMEM_PHYS 0x20000000 // 1MB - -#define GSL_HAL_GPUBASE_REG_YDX 0x30000000 -#define GSL_HAL_GPUBASE_REG_G12 0xD0000000 - -#define GSL_HAL_SIZE_REG_YDX 0x00020000 // 128KB -#define GSL_HAL_SIZE_REG_G12 0x00001000 // 4KB -#define GSL_HAL_SIZE_GMEM 0x00020000 // 128KB - 0 to 384KB in 128KB increments - -#if defined(GSL_MMU_TRANSLATION_ENABLED) -#define GSL_HAL_SHMEM_SIZE_EMEM1 0x02400000 // 36MB -#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00400000 // 4MB -#define GSL_HAL_SHMEM_SIZE_PHYS 0x00400000 // 4MB -#else -#define GSL_HAL_SHMEM_SIZE_EMEM1 0x00D00000 // 13MB -#define GSL_HAL_SHMEM_SIZE_EMEM2 0x00200000 // 2MB -#define GSL_HAL_SHMEM_SIZE_PHYS 0x00100000 // 1MB -#endif - -#define MX51_G12_INTERRUPT 84 // Interrupt line taken from Reference Manual -#define MX51_YDX_INTERRUPT 12 // Interrupt line taken from Reference Manual - -#endif // __GSL_HALCONFIG_H diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c deleted file mode 100644 index 965416b59ec..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/linux/gsl_hal.c +++ /dev/null @@ -1,598 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ - -#include "gsl_hal.h" -#include "gsl_halconfig.h" -#include "gsl_memcfg.h" -#include "gsl_linux_map.h" - -#include <linux/clk.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/vmalloc.h> - -#include <asm/atomic.h> -#include <asm/uaccess.h> -#include <asm/tlbflush.h> -#include <asm/cacheflush.h> - -////////////////////////////////////////////////////////////////////////////// -// constants -////////////////////////////////////////////////////////////////////////////// - - -////////////////////////////////////////////////////////////////////////////// -// defines -////////////////////////////////////////////////////////////////////////////// - -#define GSL_HAL_MEM1 0 -#define GSL_HAL_MEM2 1 -#define GSL_HAL_MEM3 2 - -//#define GSL_HAL_DEBUG - -////////////////////////////////////////////////////////////////////////////// -// types -////////////////////////////////////////////////////////////////////////////// - -typedef struct _gsl_hal_t { - gsl_memregion_t z160_regspace; - gsl_memregion_t z430_regspace; - gsl_memregion_t memchunk; - gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES]; -} gsl_hal_t; - -extern phys_addr_t gpu_2d_regbase; -extern int gpu_2d_regsize; -extern phys_addr_t gpu_3d_regbase; -extern int gpu_3d_regsize; -extern int gmem_size; -extern phys_addr_t gpu_reserved_mem; -extern int gpu_reserved_mem_size; - -////////////////////////////////////////////////////////////////////////////// -// functions -////////////////////////////////////////////////////////////////////////////// - -KGSLHAL_API int -kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) -{ - // - // allocate physically contiguous memory - // - - int i; - void *va; - - va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE); - - if (!va) - return (GSL_FAILURE_OUTOFMEM); - - for(i = 0; i < numpages; i++) - { - scattergatterlist[i] = page_to_phys(vmalloc_to_page(va)); - va += PAGE_SIZE; - } - - return (GSL_SUCCESS); -} - -// --------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) -{ - // - // free physical memory - // - - gsl_linux_map_free(virtaddr); - - return(GSL_SUCCESS); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_init(void) -{ - gsl_hal_t *hal; - unsigned long totalsize, mem1size; - unsigned int va, pa; - - if (gsl_driver.hal) - { - return (GSL_FAILURE_ALREADYINITIALIZED); - } - - gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t)); - - if (!gsl_driver.hal) - { - return (GSL_FAILURE_OUTOFMEM); - } - - kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t)); - - - // overlay structure on hal memory - hal = (gsl_hal_t *) gsl_driver.hal; - - // setup register space - if(gpu_3d_regbase && gpu_3d_regsize){ - hal->z430_regspace.mmio_phys_base = gpu_3d_regbase; - hal->z430_regspace.sizebytes = gpu_3d_regsize; - }else{ - hal->z430_regspace.mmio_phys_base = GSL_HAL_GPUBASE_REG_YDX; - hal->z430_regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; - } - hal->z430_regspace.mmio_virt_base = (unsigned char*)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes); - - if (hal->z430_regspace.mmio_virt_base == NULL) - { - return (GSL_FAILURE_SYSTEMERROR); - } - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_phys_base); - printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z430_regspace.mmio_virt_base); - printk(KERN_INFO "%s: hal->z430_regspace.sizebytes = 0x%08x\n", __func__, hal->z430_regspace.sizebytes); -#endif - - if(gpu_2d_regbase && gpu_2d_regsize){ - hal->z160_regspace.mmio_phys_base = gpu_2d_regbase; - hal->z160_regspace.sizebytes = gpu_2d_regsize; - }else{ - hal->z160_regspace.mmio_phys_base = GSL_HAL_GPUBASE_REG_G12; - hal->z160_regspace.sizebytes = GSL_HAL_SIZE_REG_G12; - } - hal->z160_regspace.mmio_virt_base = (unsigned char*)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes); - - if (hal->z160_regspace.mmio_virt_base == NULL) - { - return (GSL_FAILURE_SYSTEMERROR); - } - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_phys_base); - printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void*)hal->z160_regspace.mmio_virt_base); - printk(KERN_INFO "%s: hal->z160_regspace.sizebytes = 0x%08x\n", __func__, hal->z160_regspace.sizebytes); -#endif - -#ifdef GSL_MMU_TRANSLATION_ENABLED - totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; - mem1size = GSL_HAL_SHMEM_SIZE_EMEM1; - if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) - { - pa = gpu_reserved_mem; - va = (unsigned int)ioremap(gpu_reserved_mem, totalsize); - } - else - { - va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); - } -#else - if(gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M){ - totalsize = gpu_reserved_mem_size; - pa = gpu_reserved_mem; - va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size); - }else{ - gpu_reserved_mem = 0; - totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; - va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); - } - mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS); -#endif - - if (va) - { - kos_memset((void *)va, 0, totalsize); - - hal->memchunk.mmio_virt_base = (void *)va; - hal->memchunk.mmio_phys_base = pa; - hal->memchunk.sizebytes = totalsize; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_phys_base); - printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void*)hal->memchunk.mmio_virt_base); - printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes); -#endif - - hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM2].gpu_base = pa; - hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2; - va += GSL_HAL_SHMEM_SIZE_EMEM2; - pa += GSL_HAL_SHMEM_SIZE_EMEM2; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM2].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes); -#endif - - hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM3].gpu_base = pa; - hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS; - va += GSL_HAL_SHMEM_SIZE_PHYS; - pa += GSL_HAL_SHMEM_SIZE_PHYS; - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM3].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes); -#endif - -#ifdef GSL_MMU_TRANSLATION_ENABLED - gsl_linux_map_init(); - hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START; - hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START; - hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; -#else - hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va; - hal->memspace[GSL_HAL_MEM1].gpu_base = pa; - hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; -#endif - -#ifdef GSL_HAL_DEBUG - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].gpu_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void*)hal->memspace[GSL_HAL_MEM1].mmio_virt_base); - printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes); -#endif - } - else - { - kgsl_hal_close(); - return (GSL_FAILURE_SYSTEMERROR); - } - - return GSL_SUCCESS; -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_close(void) -{ - gsl_hal_t *hal; - - if (gsl_driver.hal) - { - // overlay structure on hal memory - hal = (gsl_hal_t *) gsl_driver.hal; - - // unmap registers - if (hal->z430_regspace.mmio_virt_base) - { - iounmap(hal->z430_regspace.mmio_virt_base); - } - if (hal->z160_regspace.mmio_virt_base) - { - iounmap(hal->z160_regspace.mmio_virt_base); - } - - // free physical block - if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) - { - iounmap(hal->memchunk.mmio_virt_base); - } - else - { - dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base); - } - -#ifdef GSL_MMU_TRANSLATION_ENABLED - gsl_linux_map_destroy(); -#endif - - // release hal struct - kos_memset(hal, 0, sizeof(gsl_hal_t)); - kos_free(gsl_driver.hal); - gsl_driver.hal = NULL; - } - - return (GSL_SUCCESS); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config) -{ - int status = GSL_FAILURE_DEVICEERROR; - gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; - - kos_memset(config, 0, sizeof(gsl_shmemconfig_t)); - - if (hal) - { - config->numapertures = GSL_SHMEM_MAX_APERTURES; - -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->apertures[0].id = GSL_APERTURE_MMU; -#else - config->apertures[0].id = GSL_APERTURE_EMEM; -#endif - config->apertures[0].channel = GSL_CHANNEL_1; - config->apertures[0].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base; - config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes; - - config->apertures[1].id = GSL_APERTURE_EMEM; - config->apertures[1].channel = GSL_CHANNEL_2; - config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base; - config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base; - config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes; - - config->apertures[2].id = GSL_APERTURE_PHYS; - config->apertures[2].channel = GSL_CHANNEL_1; - config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base; - config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base; - config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes; - - status = GSL_SUCCESS; - } - - return (status); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config) -{ - int status = GSL_FAILURE_DEVICEERROR; - gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; - - kos_memset(config, 0, sizeof(gsl_devconfig_t)); - - if (hal) - { - switch (device_id) - { - case GSL_DEVICE_YAMATO: - { - mh_mmu_config_u mmu_config = {0}; - - config->gmemspace.gpu_base = 0; - config->gmemspace.mmio_virt_base = 0; - config->gmemspace.mmio_phys_base = 0; - if(gmem_size){ - config->gmemspace.sizebytes = gmem_size; - }else{ - config->gmemspace.sizebytes = GSL_HAL_SIZE_GMEM; - } - - config->regspace.gpu_base = 0; - config->regspace.mmio_virt_base = (unsigned char *)hal->z430_regspace.mmio_virt_base; - config->regspace.mmio_phys_base = (unsigned int) hal->z430_regspace.mmio_phys_base; - config->regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; - - mmu_config.f.mmu_enable = 1; -#ifdef GSL_MMU_TRANSLATION_ENABLED - mmu_config.f.split_mode_enable = 0; - mmu_config.f.rb_w_clnt_behavior = 1; - mmu_config.f.cp_w_clnt_behavior = 1; - mmu_config.f.cp_r0_clnt_behavior = 1; - mmu_config.f.cp_r1_clnt_behavior = 1; - mmu_config.f.cp_r2_clnt_behavior = 1; - mmu_config.f.cp_r3_clnt_behavior = 1; - mmu_config.f.cp_r4_clnt_behavior = 1; - mmu_config.f.vgt_r0_clnt_behavior = 1; - mmu_config.f.vgt_r1_clnt_behavior = 1; - mmu_config.f.tc_r_clnt_behavior = 1; - mmu_config.f.pa_w_clnt_behavior = 1; -#endif // GSL_MMU_TRANSLATION_ENABLED - - config->mmu_config = mmu_config.val; -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; -#else - config->va_base = 0x00000000; - config->va_range = 0x00000000; -#endif // GSL_MMU_TRANSLATION_ENABLED - - // turn off memory protection unit by setting acceptable physical address range to include all pages - config->mpu_base = 0x00000000; // hal->memchunk.mmio_virt_base; - config->mpu_range = 0xFFFFF000; // hal->memchunk.sizebytes; - - status = GSL_SUCCESS; - break; - } - - case GSL_DEVICE_G12: - { - mh_mmu_config_u mmu_config = {0}; - - config->regspace.gpu_base = 0; - config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base; - config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base; - config->regspace.sizebytes = GSL_HAL_SIZE_REG_G12; - - mmu_config.f.mmu_enable = 1; - -#ifdef GSL_MMU_TRANSLATION_ENABLED - config->mmu_config = 0x00555551; - config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; - config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; -#else - config->mmu_config = mmu_config.val; - config->va_base = 0x00000000; - config->va_range = 0x00000000; -#endif // GSL_MMU_TRANSLATION_ENABLED - - config->mpu_base = 0x00000000; //(unsigned int) hal->memchunk.mmio_virt_base; - config->mpu_range = 0xFFFFF000; //hal->memchunk.sizebytes; - - status = GSL_SUCCESS; - break; - } - - default: - - break; - } - } - - return (status); -} - -//---------------------------------------------------------------------------- -// -// kgsl_hal_getchipid -// -// The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE -// -KGSLHAL_API gsl_chipid_t -kgsl_hal_getchipid(gsl_deviceid_t device_id) -{ - gsl_device_t *device = &gsl_driver.device[device_id-1]; - gsl_chipid_t chipid; - unsigned int coreid, majorid, minorid, patchid, revid; - - // YDX - device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid); - coreid &= 0xF; - - // 2. - device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid); - majorid = (majorid >> 4) & 0xF; - - device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid); - - // 2. - minorid = ((revid >> 0) & 0xFF); // this is a 16bit field, but extremely unlikely it would ever get this high - - // 1 - patchid = ((revid >> 16) & 0xFF); - - chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0)); - - return (chipid); -} - -//---------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_getplatformtype(char *platform) -{ - if (gsl_driver.hal) - { - kos_strcpy(platform, GSL_HAL_PLATFORM); - return (GSL_SUCCESS); - } - else - { - return (GSL_FAILURE_NOTINITIALIZED); - } -} - -//--------------------------------------------------------------------------- - -KGSLHAL_API int -kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value) -{ - gsl_device_t *device = &gsl_driver.device[device_id-1]; - struct clk *gpu_clk = 0; - struct clk *garb_clk = clk_get(0, "garb_clk"); - struct clk *emi_garb_clk = clk_get(0, "emi_garb_clk"); - - // unreferenced formal parameters - (void) value; - - switch (device_id) - { - case GSL_DEVICE_G12: - gpu_clk = clk_get(0, "gpu2d_clk"); - break; - case GSL_DEVICE_YAMATO: - gpu_clk = clk_get(0, "gpu3d_clk"); - break; - default: - return (GSL_FAILURE_DEVICEERROR); - } - - if (!gpu_clk) - return (GSL_FAILURE_DEVICEERROR); - - switch (state) - { - case GSL_PWRFLAGS_CLK_ON: - break; - case GSL_PWRFLAGS_POWER_ON: - clk_enable(gpu_clk); - clk_enable(garb_clk); - clk_enable(emi_garb_clk); - kgsl_device_autogate_init(&gsl_driver.device[device_id-1]); - break; - case GSL_PWRFLAGS_CLK_OFF: - break; - case GSL_PWRFLAGS_POWER_OFF: - if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) - { - return (GSL_FAILURE_DEVICEERROR); - } - kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]); - clk_disable(gpu_clk); - clk_disable(garb_clk); - clk_disable(emi_garb_clk); - break; - default: - break; - } - - return (GSL_SUCCESS); -} - -KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable) -{ - struct clk *gpu_clk; - struct clk *garb_clk = clk_get(0, "garb_clk"); - struct clk *emi_garb_clk = clk_get(0, "emi_garb_clk"); - - switch (dev) - { - case GSL_DEVICE_G12: - gpu_clk = clk_get(0, "gpu2d_clk"); - break; - case GSL_DEVICE_YAMATO: - gpu_clk = clk_get(0, "gpu3d_clk"); - break; - default: - printk(KERN_ERR "GPU device %d is invalid!\n", dev); - return (GSL_FAILURE_DEVICEERROR); - } - - if (IS_ERR(gpu_clk)) { - printk(KERN_ERR "%s: GPU clock get failed!\n", __func__); - return (GSL_FAILURE_DEVICEERROR); - } - - if (enable) { - clk_enable(gpu_clk); - clk_enable(garb_clk); - clk_enable(emi_garb_clk); - } else { - clk_disable(gpu_clk); - clk_disable(garb_clk); - clk_disable(emi_garb_clk); - } - - return (GSL_SUCCESS); -} diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c deleted file mode 100644 index 93fab327a83..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.c +++ /dev/null @@ -1,31 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - * - */ - -#include "kos_libapi.h" - -// -// Return the maximum amount of memory that can be allocated to the Z430. This number -// will be constrained to 2MB as a minimum and the original hardcoded value for the caller -// as a maximum. If the return value is outside of this range, then the original value in -// the caller will be used. For this reason, returning 0 is used to signify to use the -// original value as the default. -// -KOS_DLLEXPORT unsigned long kgsl_get_z430_memory_amount(void) -{ - return(0); -} diff --git a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h b/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h deleted file mode 100644 index e68387f1609..00000000000 --- a/drivers/mxc/amd-gpu/platform/hal/MX51/memcfg/gsl_memcfg.h +++ /dev/null @@ -1,40 +0,0 @@ -/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices nor - * the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef GSL_MEMCFG_H -#define GSL_MEMCFG_H - -// -// Return the maximum amount of memory that can be allocated to the Z430. This number -// will be constrained to 2MB as a minimum and the original hardcoded value for the caller -// as a maximum. If the return value is outside of this range, then the original value in -// the caller will be used. For this reason, returning 0 is used to signify to use the -// original value as the default. -// -KOS_DLLEXPORT unsigned long kgsl_get_z430_memory_amount(void); -#endif diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c new file mode 100644 index 00000000000..45632d8f868 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c @@ -0,0 +1,570 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include "gsl_hal.h" +#include "gsl_halconfig.h" +#include "gsl_linux_map.h" + +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include <asm/atomic.h> +#include <linux/uaccess.h> +#include <asm/tlbflush.h> +#include <asm/cacheflush.h> + +#define GSL_HAL_MEM1 0 +#define GSL_HAL_MEM2 1 +#define GSL_HAL_MEM3 2 + +/* #define GSL_HAL_DEBUG */ + +typedef struct _gsl_hal_t { + gsl_memregion_t z160_regspace; + gsl_memregion_t z430_regspace; + gsl_memregion_t memchunk; + gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES]; + unsigned int has_z160; + unsigned int has_z430; +} gsl_hal_t; + +extern phys_addr_t gpu_2d_regbase; +extern int gpu_2d_regsize; +extern phys_addr_t gpu_3d_regbase; +extern int gpu_3d_regsize; +extern int gmem_size; +extern phys_addr_t gpu_reserved_mem; +extern int gpu_reserved_mem_size; + + +KGSLHAL_API int +kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* allocate physically contiguous memory */ + + int i; + void *va; + + va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE); + + if (!va) + return GSL_FAILURE_OUTOFMEM; + + for (i = 0; i < numpages; i++) { + scattergatterlist[i] = page_to_phys(vmalloc_to_page(va)); + va += PAGE_SIZE; + } + + return GSL_SUCCESS; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* free physical memory */ + + gsl_linux_map_free(virtaddr); + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_init(void) +{ + gsl_hal_t *hal; + unsigned long totalsize, mem1size; + unsigned int va, pa; + + if (gsl_driver.hal) { + return GSL_FAILURE_ALREADYINITIALIZED; + } + + gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t)); + + if (!gsl_driver.hal) { + return GSL_FAILURE_OUTOFMEM; + } + + kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t)); + + + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + if (gpu_3d_regbase && gpu_3d_regsize) { + hal->has_z430 = 1; + } else { + hal->has_z430 = 0; + } + + if (gpu_2d_regbase && gpu_2d_regsize) { + hal->has_z160 = 1; + } else { + hal->has_z160 = 0; + } + + /* setup register space */ + if (hal->has_z430) { + hal->z430_regspace.mmio_phys_base = gpu_3d_regbase; + hal->z430_regspace.sizebytes = gpu_3d_regsize; + hal->z430_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes); + + if (hal->z430_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z430_regspace.sizebytes = 0x%08x\n", __func__, hal->z430_regspace.sizebytes); +#endif + } + + if (hal->has_z160) { + hal->z160_regspace.mmio_phys_base = gpu_2d_regbase; + hal->z160_regspace.sizebytes = gpu_2d_regsize; + hal->z160_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes); + + if (hal->z160_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z160_regspace.sizebytes = 0x%08x\n", __func__, hal->z160_regspace.sizebytes); +#endif + } + +#ifdef GSL_MMU_TRANSLATION_ENABLED + totalsize = GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; + mem1size = GSL_HAL_SHMEM_SIZE_EMEM1; + if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) { + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, totalsize); + } else { + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } +#else + if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) { + totalsize = gpu_reserved_mem_size; + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size); + } else { + gpu_reserved_mem = 0; + totalsize = GSL_HAL_SHMEM_SIZE_EMEM1 + GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS; + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } + mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2 + GSL_HAL_SHMEM_SIZE_PHYS); +#endif + + if (va) { + kos_memset((void *)va, 0, totalsize); + + hal->memchunk.mmio_virt_base = (void *)va; + hal->memchunk.mmio_phys_base = pa; + hal->memchunk.sizebytes = totalsize; + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base); + printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base); + printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM2].gpu_base = pa; + hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2; + va += GSL_HAL_SHMEM_SIZE_EMEM2; + pa += GSL_HAL_SHMEM_SIZE_EMEM2; + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM3].gpu_base = pa; + hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS; + va += GSL_HAL_SHMEM_SIZE_PHYS; + pa += GSL_HAL_SHMEM_SIZE_PHYS; + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes); +#endif + +#ifdef GSL_MMU_TRANSLATION_ENABLED + gsl_linux_map_init(); + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; +#else + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM1].gpu_base = pa; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; +#endif + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes); +#endif + } else { + kgsl_hal_close(); + return GSL_FAILURE_SYSTEMERROR; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_close(void) +{ + gsl_hal_t *hal; + + if (gsl_driver.hal) { + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + /* unmap registers */ + if (hal->has_z430 && hal->z430_regspace.mmio_virt_base) { + iounmap(hal->z430_regspace.mmio_virt_base); + } + + if (hal->has_z160 && hal->z160_regspace.mmio_virt_base) { + iounmap(hal->z160_regspace.mmio_virt_base); + } + + /* free physical block */ + if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) { + iounmap(hal->memchunk.mmio_virt_base); + } else { + dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base); + } + +#ifdef GSL_MMU_TRANSLATION_ENABLED + gsl_linux_map_destroy(); +#endif + + /* release hal struct */ + kos_memset(hal, 0, sizeof(gsl_hal_t)); + kos_free(gsl_driver.hal); + gsl_driver.hal = NULL; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_shmemconfig_t)); + + if (hal) { + config->numapertures = GSL_SHMEM_MAX_APERTURES; + +#ifdef GSL_MMU_TRANSLATION_ENABLED + config->apertures[0].id = GSL_APERTURE_MMU; +#else + config->apertures[0].id = GSL_APERTURE_EMEM; +#endif + config->apertures[0].channel = GSL_CHANNEL_1; + config->apertures[0].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base; + config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes; + + config->apertures[1].id = GSL_APERTURE_EMEM; + config->apertures[1].channel = GSL_CHANNEL_2; + config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base; + config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base; + config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes; + + config->apertures[2].id = GSL_APERTURE_PHYS; + config->apertures[2].channel = GSL_CHANNEL_1; + config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base; + config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base; + config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes; + + status = GSL_SUCCESS; + } + + return status; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_devconfig_t)); + + if (hal) { + switch (device_id) { + case GSL_DEVICE_YAMATO: + { + if (hal->has_z430) { + mh_mmu_config_u mmu_config = {0}; + + config->gmemspace.gpu_base = 0; + config->gmemspace.mmio_virt_base = 0; + config->gmemspace.mmio_phys_base = 0; + if (gmem_size) { + config->gmemspace.sizebytes = gmem_size; + } else { + config->gmemspace.sizebytes = 0; + } + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z430_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z430_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; + + mmu_config.f.mmu_enable = 1; +#ifdef GSL_MMU_TRANSLATION_ENABLED + mmu_config.f.split_mode_enable = 0; + mmu_config.f.rb_w_clnt_behavior = 1; + mmu_config.f.cp_w_clnt_behavior = 1; + mmu_config.f.cp_r0_clnt_behavior = 1; + mmu_config.f.cp_r1_clnt_behavior = 1; + mmu_config.f.cp_r2_clnt_behavior = 1; + mmu_config.f.cp_r3_clnt_behavior = 1; + mmu_config.f.cp_r4_clnt_behavior = 1; + mmu_config.f.vgt_r0_clnt_behavior = 1; + mmu_config.f.vgt_r1_clnt_behavior = 1; + mmu_config.f.tc_r_clnt_behavior = 1; + mmu_config.f.pa_w_clnt_behavior = 1; +#endif /* GSL_MMU_TRANSLATION_ENABLED */ + + config->mmu_config = mmu_config.val; +#ifdef GSL_MMU_TRANSLATION_ENABLED + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; +#else + config->va_base = 0x00000000; + config->va_range = 0x00000000; +#endif /* GSL_MMU_TRANSLATION_ENABLED */ + + /* turn off memory protection unit by setting acceptable physical address range to include all pages */ + config->mpu_base = 0x00000000; /* hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + status = GSL_SUCCESS; + } + break; + } + + case GSL_DEVICE_G12: + { + mh_mmu_config_u mmu_config = {0}; + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_G12; + + mmu_config.f.mmu_enable = 1; + +#ifdef GSL_MMU_TRANSLATION_ENABLED + config->mmu_config = 0x00555551; + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; +#else + config->mmu_config = mmu_config.val; + config->va_base = 0x00000000; + config->va_range = 0x00000000; +#endif /* GSL_MMU_TRANSLATION_ENABLED */ + + config->mpu_base = 0x00000000; /* (unsigned int) hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + + status = GSL_SUCCESS; + break; + } + + default: + break; + } + } + + return status; +} + +/*---------------------------------------------------------------------------- + * kgsl_hal_getchipid + * + * The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE + *---------------------------------------------------------------------------- + */ +KGSLHAL_API gsl_chipid_t +kgsl_hal_getchipid(gsl_deviceid_t device_id) +{ + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_chipid_t chipid = 0; + unsigned int coreid, majorid, minorid, patchid, revid; + + if (hal->has_z430 && (device_id == GSL_DEVICE_YAMATO)) { + device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid); + coreid &= 0xF; + + device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid); + majorid = (majorid >> 4) & 0xF; + + device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid); + + minorid = ((revid >> 0) & 0xFF); /* this is a 16bit field, but extremely unlikely it would ever get this high */ + + patchid = ((revid >> 16) & 0xFF); + + chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0)); + } + + return chipid; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value) +{ + gsl_device_t *device = &gsl_driver.device[device_id-1]; + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + /* unreferenced formal parameters */ + (void) value; + + switch (device_id) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + return GSL_FAILURE_DEVICEERROR; + } + + if (!gpu_clk) { + return GSL_FAILURE_DEVICEERROR; + } + + switch (state) { + case GSL_PWRFLAGS_CLK_ON: + break; + case GSL_PWRFLAGS_POWER_ON: + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + kgsl_device_autogate_init(&gsl_driver.device[device_id-1]); + break; + case GSL_PWRFLAGS_CLK_OFF: + break; + case GSL_PWRFLAGS_POWER_OFF: + if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) { + return GSL_FAILURE_DEVICEERROR; + } + kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]); + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + break; + default: + break; + } + + return GSL_SUCCESS; +} + +KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable) +{ + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + switch (dev) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + printk(KERN_ERR "GPU device %d is invalid!\n", dev); + return GSL_FAILURE_DEVICEERROR; + } + + if (IS_ERR(gpu_clk)) { + printk(KERN_ERR "%s: GPU clock get failed!\n", __func__); + return GSL_FAILURE_DEVICEERROR; + } + + if (enable) { + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + } else { + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + } + + return GSL_SUCCESS; +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c index 30f783e1cf1..6aaaa745a84 100644 --- a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c @@ -57,9 +57,7 @@ static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf); static int gsl_kmod_open(struct inode *inode, struct file *fd); static int gsl_kmod_release(struct inode *inode, struct file *fd); static irqreturn_t z160_irq_handler(int irq, void *dev_id); -#if defined(MX51) static irqreturn_t z430_irq_handler(int irq, void *dev_id); -#endif static int gsl_kmod_major; static struct class *gsl_kmod_class; @@ -753,13 +751,11 @@ static irqreturn_t z160_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -#if defined(MX51) static irqreturn_t z430_irq_handler(int irq, void *dev_id) { kgsl_intr_isr(); return IRQ_HANDLED; } -#endif static int gpu_probe(struct platform_device *pdev) { @@ -817,18 +813,21 @@ static int gpu_probe(struct platform_device *pdev) goto kgsl_driver_init_error; } -#if defined(MX51) - if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) + if (gpu_3d_irq > 0) { - printk(KERN_ERR "%s: request_irq error\n", __func__); - goto request_irq_error; + if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) { + printk(KERN_ERR "%s: request_irq error\n", __func__); + gpu_3d_irq = 0; + goto request_irq_error; + } } -#endif - if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) + if (gpu_2d_irq > 0) { - printk(KERN_ERR "2D Acceleration Enabled, OpenVG Disabled!\n"); - gpu_2d_irq = 0; + if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) { + printk(KERN_ERR "2D Acceleration Enabled, OpenVG Disabled!\n"); + gpu_2d_irq = 0; + } } gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops); @@ -879,7 +878,7 @@ static int gpu_remove(struct platform_device *pdev) device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0)); class_destroy(gsl_kmod_class); unregister_chrdev(gsl_kmod_major, "gsl_kmod"); -#if defined(MX51) + if (gpu_3d_irq) { free_irq(gpu_3d_irq, NULL); @@ -889,12 +888,7 @@ static int gpu_remove(struct platform_device *pdev) { free_irq(gpu_2d_irq, NULL); } -#elif defined(MX35) - if (gpu_2d_irq) - { - free_irq(gpu_2d_irq, NULL); - } -#endif + kgsl_driver_close(); return 0; } @@ -965,9 +959,5 @@ static void __exit gsl_kmod_exit(void) module_init(gsl_kmod_init); module_exit(gsl_kmod_exit); MODULE_AUTHOR("Advanced Micro Devices"); -#if defined(MX51) -MODULE_DESCRIPTION("AMD 2D/3D graphics core driver for i.MX51"); -#elif defined(MX35) -MODULE_DESCRIPTION("AMD 2D graphics core driver for i.MX35"); -#endif +MODULE_DESCRIPTION("AMD graphics core driver for i.MX"); MODULE_LICENSE("GPL v2"); |