diff options
| author | Richard Zhao <richard.zhao@freescale.com> | 2010-07-26 16:20:56 +0800 |
|---|---|---|
| committer | Richard Zhao <richard.zhao@freescale.com> | 2010-07-29 10:35:09 +0800 |
| commit | 9fefd36353aeccd32d2531238753d87b705e431e (patch) | |
| tree | 86a3d5955518ac6ebd45f733f6e154365d076ad8 | |
| parent | 2dc5e34f387b1a1691c5440690dc96e9e0710f41 (diff) | |
ENGR00125578-2 mx50 clock: correct pfd mask bits
Add offset to pllctrl pfd mask bits and check lock bit.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 20 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 2 |
2 files changed, 18 insertions, 4 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 7efe52adcb2..d76d12c53a3 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -268,7 +268,6 @@ static struct clk osc_clk = { static int apll_enable(struct clk *clk) { __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); - udelay(10); return 0; } @@ -337,10 +336,24 @@ static int pfd_enable(struct clk *clk) int index; index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); - __raw_writel(1 << index, apll_base + MXC_ANADIG_PLLCTRL_CLR); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_CLR); /* clear clk gate bit */ __raw_writel((1 << (clk->enable_shift + 7)), apll_base + (int)clk->enable_reg + 8); + + /* check lock bit */ + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, 50000)) { + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_CLR); + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_SET); + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, SPIN_DELAY)) + panic("pfd_enable failed!\n"); + } + return 0; } @@ -352,7 +365,8 @@ static void pfd_disable(struct clk *clk) /* set clk gate bit */ __raw_writel((1 << (clk->enable_shift + 7)), apll_base + (int)clk->enable_reg + 4); - __raw_writel(1 << index, apll_base + MXC_ANADIG_PLLCTRL_SET); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_SET); } static struct clk pfd0_clk = { diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 623fcc09154..0a93f585589 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -115,7 +115,7 @@ #define MXC_ANADIG_APLL_LOCK (1 << 31) #define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) -#define MXC_ANADIG_PFD_DIS_OFFSET (1 << 16) +#define MXC_ANADIG_PFD_DIS_OFFSET 16 #define MXC_ANADIG_PFD_DIS_MASK 0xff #define MXC_ANADIG_APLL_LOCK_CNT_OFFSET 0 #define MXC_ANADIG_APLL_LOCK_CNT_MASK 0xffff |