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authorRichard Zhao <richard.zhao@freescale.com>2011-12-31 11:38:37 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-11 21:53:20 +0800
commit2d4cb8a196efc0277920988e305b3c5a8bb0b897 (patch)
treed6dec07d2cd05b2cfa23240dd93cf61152d86302
parenteb6d1ece9e858556799674b6138dd147b3fb4627 (diff)
downloadlinux-linaro-2d4cb8a196efc0277920988e305b3c5a8bb0b897.tar.gz
arm/imx6q: add cko1 clock
imx6q-sabrelite board use it as audio codec clock. Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c75
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c6
2 files changed, 74 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 1029a3b..f29f3be 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -329,6 +329,12 @@
#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+#define BP_CCOSR_CKO1_EN 7
+#define BP_CCOSR_CKO1_PODF 4
+#define BM_CCOSR_CKO1_PODF (0x7 << 4)
+#define BP_CCOSR_CKO1_SEL 0
+#define BM_CCOSR_CKO1_SEL (0xf << 0)
+
#define FREQ_480M 480000000
#define FREQ_528M 528000000
#define FREQ_594M 594000000
@@ -399,6 +405,7 @@ static struct clk ipu1_di1_clk;
static struct clk ipu2_di0_clk;
static struct clk ipu2_di1_clk;
static struct clk enfc_clk;
+static struct clk cko1_clk;
static struct clk dummy_clk = {};
static unsigned long external_high_reference;
@@ -944,6 +951,24 @@ static void _clk_disable(struct clk *clk)
writel_relaxed(reg, clk->enable_reg);
}
+static int _clk_enable_1b(struct clk *clk)
+{
+ u32 reg;
+ reg = readl_relaxed(clk->enable_reg);
+ reg |= 0x1 << clk->enable_shift;
+ writel_relaxed(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_disable_1b(struct clk *clk)
+{
+ u32 reg;
+ reg = readl_relaxed(clk->enable_reg);
+ reg &= ~(0x1 << clk->enable_shift);
+ writel_relaxed(reg, clk->enable_reg);
+}
+
struct divider {
struct clk *clk;
void __iomem *reg;
@@ -989,6 +1014,7 @@ DEF_CLK_DIV1(ipu2_di0_pre_div, &ipu2_di0_pre_clk, CSCDR2, IPU2_DI0_PRE);
DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk, CSCDR2, IPU2_DI1_PRE);
DEF_CLK_DIV1(ipu1_div, &ipu1_clk, CSCDR3, IPU1_HSP);
DEF_CLK_DIV1(ipu2_div, &ipu2_clk, CSCDR3, IPU2_HSP);
+DEF_CLK_DIV1(cko1_div, &cko1_clk, CCOSR, CKO1);
#define DEF_CLK_DIV2(d, c, r, b) \
static struct divider d = { \
@@ -1044,6 +1070,7 @@ static struct divider *dividers[] = {
&enfc_div,
&spdif_div,
&asrc_serial_div,
+ &cko1_div,
};
static unsigned long ldb_di_clk_get_rate(struct clk *clk)
@@ -1631,6 +1658,31 @@ DEF_IPU_DI_MUX(CSCDR2, 2, 1);
DEF_IPU_MUX(1);
DEF_IPU_MUX(2);
+static struct multiplexer cko1_mux = {
+ .clk = &cko1_clk,
+ .reg = CCOSR,
+ .bp = BP_CCOSR_CKO1_SEL,
+ .bm = BM_CCOSR_CKO1_SEL,
+ .parents = {
+ &pll3_usb_otg,
+ &pll2_bus,
+ &pll1_sys,
+ &pll5_video,
+ &axi_clk,
+ &enfc_clk,
+ &ipu1_di0_clk,
+ &ipu1_di1_clk,
+ &ipu2_di0_clk,
+ &ipu2_di1_clk,
+ &ahb_clk,
+ &ipg_clk,
+ &ipg_perclk,
+ &ckil_clk,
+ &pll4_audio,
+ NULL
+ },
+};
+
static struct multiplexer *multiplexers[] = {
&axi_mux,
&periph_mux,
@@ -1673,6 +1725,7 @@ static struct multiplexer *multiplexers[] = {
&ipu2_di1_mux,
&ipu1_mux,
&ipu2_mux,
+ &cko1_mux,
};
static int _clk_set_parent(struct clk *clk, struct clk *parent)
@@ -1753,6 +1806,21 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg);
.secondary = s, \
}
+#define DEF_CLK_1B(name, er, es, p, s) \
+ static struct clk name = { \
+ __INIT_CLK_DEBUG(name) \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .enable = _clk_enable_1b, \
+ .disable = _clk_disable_1b, \
+ .get_rate = _clk_get_rate, \
+ .set_rate = _clk_set_rate, \
+ .round_rate = _clk_round_rate, \
+ .set_parent = _clk_set_parent, \
+ .parent = p, \
+ .secondary = s, \
+ }
+
DEF_CLK(aips_tz1_clk, CCGR0, CG0, &ahb_clk, NULL);
DEF_CLK(aips_tz2_clk, CCGR0, CG1, &ahb_clk, NULL);
DEF_CLK(apbh_dma_clk, CCGR0, CG2, &ahb_clk, NULL);
@@ -1819,7 +1887,8 @@ DEF_CLK(usdhc3_clk, CCGR6, CG3, &pll2_pfd_400m, NULL);
DEF_CLK(usdhc4_clk, CCGR6, CG4, &pll2_pfd_400m, NULL);
DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL);
DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL);
-DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL);
+DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, &ocram_clk);
+DEF_CLK_1B(cko1_clk, CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
static int pcie_clk_enable(struct clk *clk)
{
@@ -1943,6 +2012,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
_REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk),
_REGISTER_CLOCK(NULL, "gpt_clk", gpt_clk),
+ _REGISTER_CLOCK("202c000.ssi", NULL, ssi2_clk),
+ _REGISTER_CLOCK(NULL, "clko_clk", cko1_clk),
};
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
@@ -2057,6 +2128,8 @@ int __init mx6q_clocks_init(void)
clk_set_rate(&usdhc3_clk, 49500000);
clk_set_rate(&usdhc4_clk, 49500000);
+ clk_set_parent(&cko1_clk, &ahb_clk);
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
base = of_iomap(np, 0);
WARN_ON(!base);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index dc4e99f..d273c0a 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -131,7 +131,6 @@ static struct mxc_audio_platform_data mx6_sabrelite_audio_data;
static int mx6_sabrelite_sgtl5000_init(void)
{
struct clk *clko;
- struct clk *new_parent;
int rate;
clko = clk_get(NULL, "clko_clk");
@@ -139,11 +138,6 @@ static int mx6_sabrelite_sgtl5000_init(void)
pr_err("can't get CLKO clock.\n");
return PTR_ERR(clko);
}
- new_parent = clk_get(NULL, "ahb");
- if (!IS_ERR(new_parent)) {
- clk_set_parent(clko, new_parent);
- clk_put(new_parent);
- }
rate = clk_round_rate(clko, 16000000);
if (rate < 8000000 || rate > 27000000) {
pr_err("Error:SGTL5000 mclk freq %d out of range!\n", rate);