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authorAnson Huang <b20788@freescale.com>2011-12-30 14:52:18 +0800
committerAnson Huang <b20788@freescale.com>2011-12-30 14:58:45 +0800
commit1703ca7108c66b9d88d66b1e730447553bc1b161 (patch)
tree29454390cd7079177fa4c45812347a0c1c658ed1
parente6bb3fc2698e4e2e2e9183974460ddfbe47cd418 (diff)
ENGR00171096 [MX6]Remove unnecessary workaroud of L2 in suspend/resume
We have many operation before enabling L2 cache, which can make sure L2 already can be accessed before enabled. Signed-off-by: Anson Huang <b20788@freescale.com>
-rw-r--r--arch/arm/mach-mx6/mx6q_suspend.S9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/arm/mach-mx6/mx6q_suspend.S b/arch/arm/mach-mx6/mx6q_suspend.S
index bbda5aa3676..31bccf15e29 100644
--- a/arch/arm/mach-mx6/mx6q_suspend.S
+++ b/arch/arm/mach-mx6/mx6q_suspend.S
@@ -461,15 +461,6 @@ are running with MMU off.
****************************************************************/
resume:
ldr r0, =SRC_BASE_ADDR
- /* Due to the L2 cache errata(TKT065875)
- , need to wait at least 170ns, each IO read
- takes about 76ns, but the actual wait time
- to make system more stable is about 380ns */
- ldr r1, [r0]
- ldr r1, [r0, #0x4]
- ldr r1, [r0, #0x8]
- ldr r1, [r0, #0xc]
- ldr r1, [r0, #0x10]
mov r1, #0x0
str r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */
ldr r0, [r0, #SRC_GPR2_OFFSET]