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authorWill Deacon <will.deacon@arm.com>2011-04-05 13:57:53 +0100
committerEric Miao <eric.miao@canonical.com>2011-11-10 07:39:01 +0800
commite7ae1fa71713c98625a9dfac084ae7a3548c4e8b (patch)
treeac4ef410358274616c28941c396cc206d4f9ff62
parenteb1091349f27376c86603d9a973e3e8c6436b33e (diff)
downloadlinux-linaro-e7ae1fa71713c98625a9dfac084ae7a3548c4e8b.tar.gz
ARM: 6864/1: hw_breakpoint: clear DBGVCR out of reset
commit e89c0d7090c54d7b11b9b091e495a1ae345dd3ff upstream. The DBGVCR, used for configuring vector catch debug events, is UNKNOWN out of reset on ARMv7. When enabling monitor mode, this must be zeroed to avoid UNPREDICTABLE behaviour. This patch adds the zeroing code to the debug reset path. Reported-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> (cherry picked from commit c421122f3dea5b5c42133f67a8084e6c0793a35c)
-rw-r--r--arch/arm/kernel/hw_breakpoint.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 44b84fe6e1b..7e9a0c7f198 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -868,6 +868,13 @@ static void reset_ctrl_regs(void *info)
*/
asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
isb();
+
+ /*
+ * Clear any configured vector-catch events before
+ * enabling monitor mode.
+ */
+ asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
+ isb();
}
if (enable_monitor_mode())