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authorEric Miao <eric.miao@linaro.org>2011-12-14 17:19:30 +0800
committerEric Miao <eric.miao@linaro.org>2011-12-14 17:19:30 +0800
commitbbc56915e53c6cb54356abcaa26123a496c78134 (patch)
treece7595b1ee4f3ed1c3386c74523d1a0fc336bed7
parent71b0ba808622597c36841dec3b7bb7c11701d6a1 (diff)
parentc7eb15812c072903ec9c9e9cf44328257f27b6a8 (diff)
downloadlinux-linaro-bbc56915e53c6cb54356abcaa26123a496c78134.tar.gz
Merge remote-tracking branch 'weitway/lt-3.2-imx6-display' into lt-3.2-imx6
Conflicts: arch/arm/Kconfig arch/arm/mach-imx/mach-imx6q.c
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts67
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi40
-rw-r--r--arch/arm/configs/imx6q_sabrelite_defconfig182
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c102
-rw-r--r--arch/arm/mach-imx/gpc.c66
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c111
-rw-r--r--arch/arm/mach-imx/mmdc.c5
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c123
-rw-r--r--arch/arm/mach-imx/src.c47
-rw-r--r--arch/arm/mach-imx/suspend-imx6q.S695
-rw-r--r--arch/arm/mm/cache-l2x0.c2
-rw-r--r--arch/arm/plat-mxc/Kconfig1
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx6q.h7359
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h57
-rw-r--r--arch/arm/plat-mxc/include/mach/ipu-v3.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx6q.h12
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_edid.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_hdmi.h1028
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_vpu.h3
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c17
-rw-r--r--arch/arm/plat-mxc/pwm.c9
-rw-r--r--drivers/i2c/busses/i2c-imx.c1
-rw-r--r--drivers/media/video/mxc/output/Kconfig1
-rw-r--r--drivers/media/video/mxc/output/mxc_vout.c25
-rw-r--r--drivers/mfd/Kconfig9
-rw-r--r--drivers/mfd/Makefile1
-rw-r--r--drivers/mfd/mxc-hdmi-core.c590
-rw-r--r--drivers/mxc/Kconfig15
-rw-r--r--drivers/mxc/ipu3/ipu_calc_stripes_sizes.c11
-rw-r--r--drivers/mxc/ipu3/ipu_common.c28
-rw-r--r--drivers/mxc/ipu3/ipu_ic.c1
-rw-r--r--drivers/mxc/ipu3/ipu_prv.h1
-rw-r--r--drivers/mxc/vpu/Kconfig2
-rw-r--r--drivers/mxc/vpu/mxc_vpu.c82
-rw-r--r--drivers/tty/serial/imx.c38
-rw-r--r--drivers/video/Kconfig7
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/backlight/pwm_bl.c40
-rw-r--r--drivers/video/mxc/Kconfig7
-rw-r--r--drivers/video/mxc/Makefile2
-rw-r--r--drivers/video/mxc/ldb.c272
-rw-r--r--drivers/video/mxc/mxc_dvi.c380
-rw-r--r--drivers/video/mxc/mxc_edid.c103
-rw-r--r--drivers/video/mxc/mxc_ipuv3_fb.c163
-rw-r--r--drivers/video/mxc/mxcfb_sii902x.c8
-rw-r--r--drivers/video/mxc/tve.c13
-rw-r--r--drivers/video/mxc_hdmi.c1975
-rw-r--r--include/linux/fsl_devices.h21
-rw-r--r--include/linux/iram_alloc.h35
-rw-r--r--include/linux/mfd/mxc-hdmi-core.h39
56 files changed, 13650 insertions, 225 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ee8eaa5db58..456cff6be8e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1700,7 +1700,7 @@ config FORCE_MAX_ZONEORDER
range 11 64 if ARCH_SHMOBILE
default "9" if SA1111
default "14" if ARCH_MX5
- default "14" if ARCH_MX6Q
+ default "14" if SOC_IMX6Q
default "11"
help
The kernel memory allocator divides physically contiguous memory
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 3011d3d2859..5883e308ba0 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -26,6 +26,15 @@
};
soc {
+ aips-bus@02000000 { /* AIPS1 */
+ ldb@020e0000 {
+ disp-pwr-gpios = <&gpio1 0 0>; /* gpio2 0 */
+ mode = "sin0";
+ ext_ref = "true";
+ lvds0 = <1 0>;
+ };
+ };
+
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
phy-mode = "rgmii";
@@ -46,6 +55,21 @@
uart1: uart@021e8000 { /* UART2 */
status = "okay";
};
+
+ i2c@021a4000 { /* I2C2 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ddc: ddc@50 {
+ compatible = "fsl,imx6q-hdmi-ddc";
+ reg = <0x50>;
+ };
+ };
+ };
+
+ hdmi@0x00120000 { /* HDMI */
+ ipu = <0>;
+ di = <0>;
};
};
@@ -58,4 +82,47 @@
linux,default-trigger = "heartbeat";
};
};
+
+ backlight {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-bus";
+
+ pwm_bl {
+ compatible = "pwm-bl";
+ pwm-parent = <&pwm4>;
+ max_brightness = <255>;
+ dft_brightness = <128>;
+ pwm_period_ns = <50000>;
+ };
+ };
+
+ displays {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ disp1: fb@0 {
+ compatible = "fsl,mxcfb-ipuv3";
+ disp_dev = "hdmi";
+ interface_pix_fmt = "RGB24";
+ mode_str = "1280x720M@60";
+ internal_clk = "false";
+ reg = <0x00000000 0x0>; /* reserve fb mem */
+ };
+
+ disp2: fb@1 {
+ compatible = "fsl,mxcfb-ipuv3";
+ disp_dev = "ldb";
+ interface_pix_fmt = "RGB666";
+ mode_str = "LDB-XGA";
+ internal_clk = "false";
+ reg = <0x00000001 0x0>; /* reserve fb mem */
+ };
+
+ v4l2-out@0 {
+ compatible = "fsl,vout_ipuv3";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599558c..7dabaee87e0 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -203,30 +203,35 @@
};
vpu@02040000 {
+ compatible = "fsl,vpu";
reg = <0x02040000 0x3c000>;
- interrupts = <0 3 0x04 0 12 0x04>;
+ interrupts = <0 12 0x04 0 3 0x04>;
};
aipstz@0207c000 { /* AIPSTZ1 */
reg = <0x0207c000 0x4000>;
};
- pwm@02080000 { /* PWM1 */
+ pwm1: pwm@02080000 { /* PWM1 */
+ compatible = "fsl,imx6q-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
};
- pwm@02084000 { /* PWM2 */
+ pwm2: pwm@02084000 { /* PWM2 */
+ compatible = "fsl,imx6q-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
};
- pwm@02088000 { /* PWM3 */
+ pwm3: pwm@02088000 { /* PWM3 */
+ compatible = "fsl,imx6q-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
};
- pwm@0208c000 { /* PWM4 */
+ pwm4: pwm@0208c000 { /* PWM4 */
+ compatible = "fsl,imx6q-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
};
@@ -389,6 +394,11 @@
reg = <0x020e0000 0x4000>;
};
+ ldb@020e0000 {
+ compatible = "fsl,imx6q-ldb";
+ reg = <0x020e0000 0x4>;
+ };
+
dcic@020e4000 { /* DCIC1 */
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
@@ -571,5 +581,25 @@
status = "disabled";
};
};
+
+ hdmi@0x00120000 { /* HDMI */
+ compatible = "fsl,imx6q-hdmi-core";
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04 0 116 0x04>;
+ };
+
+ ipu@0x02400000 { /* IPU1 */
+ compatible = "fsl,ipuv3";
+ reg = <0x02400000 0x400000>;
+ interrupts = <0 5 0x04 0 6 0x04>;
+ revision = <4>;
+ };
+
+ ipu@0x02800000 { /* IPU2 */
+ compatible = "fsl,ipuv3";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 7 0x04 0 8 0x04>;
+ revision = <4>;
+ };
};
};
diff --git a/arch/arm/configs/imx6q_sabrelite_defconfig b/arch/arm/configs/imx6q_sabrelite_defconfig
index 7190595a9c2..163e04dd8f3 100644
--- a/arch/arm/configs/imx6q_sabrelite_defconfig
+++ b/arch/arm/configs/imx6q_sabrelite_defconfig
@@ -128,6 +128,7 @@ CONFIG_HAVE_DMA_API_DEBUG=y
#
# GCOV-based kernel profiling
#
+# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
@@ -257,6 +258,7 @@ CONFIG_ARCH_IMX_V6_V7=y
CONFIG_HAVE_IMX_GPC=y
CONFIG_HAVE_IMX_MMDC=y
CONFIG_HAVE_IMX_SRC=y
+CONFIG_ARCH_MX6Q=y
#
# MX31 platforms:
@@ -287,6 +289,8 @@ CONFIG_SOC_IMX6Q=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_MXC_DEBUG_BOARD=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
+CONFIG_CLK_DEBUG=y
#
# System MMU
@@ -383,7 +387,7 @@ CONFIG_VIRT_TO_BUS=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CLEANCACHE is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_MAX_ZONEORDER=14
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
@@ -856,7 +860,12 @@ CONFIG_KEYBOARD_IMX=y
#
# Character devices
#
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@@ -1079,7 +1088,7 @@ CONFIG_BCMA_POSSIBLE=y
#
# Multifunction device drivers
#
-# CONFIG_MFD_CORE is not set
+CONFIG_MFD_CORE=y
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
@@ -1119,6 +1128,7 @@ CONFIG_MFD_WM8350_I2C=y
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_AAT2870_CORE is not set
+CONFIG_MFD_MXC_HDMI=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
@@ -1153,29 +1163,59 @@ CONFIG_VIDEO_MEDIA=y
#
# Multimedia drivers
#
-# CONFIG_RC_CORE is not set
+CONFIG_RC_CORE=y
+CONFIG_LIRC=y
+CONFIG_RC_MAP=y
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+CONFIG_IR_RC5_SZ_DECODER=y
+CONFIG_IR_MCE_KBD_DECODER=y
+CONFIG_IR_LIRC_CODEC=y
+# CONFIG_RC_ATI_REMOTE is not set
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_REDRAT3 is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_RC_LOOPBACK is not set
# CONFIG_MEDIA_ATTACH is not set
CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA827X=y
-CONFIG_MEDIA_TUNER_TDA18271=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_XC4000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+
+#
+# Customize TV tuners
+#
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+CONFIG_VIDEO_IR_I2C=y
#
# Encoders, decoders, sensors and other helper chips
@@ -1262,27 +1302,12 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y
#
# CONFIG_VIDEO_THS7303 is not set
# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_VIDEO_TIMBERDALE is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_IMX074 is not set
-CONFIG_SOC_CAMERA_MT9M001=y
-CONFIG_SOC_CAMERA_MT9M111=y
-CONFIG_SOC_CAMERA_MT9T031=y
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-CONFIG_SOC_CAMERA_MT9V022=y
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-CONFIG_SOC_CAMERA_TW9910=y
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV2640 is not set
-# CONFIG_SOC_CAMERA_OV5642 is not set
-# CONFIG_SOC_CAMERA_OV6650 is not set
-CONFIG_SOC_CAMERA_OV772X=y
-# CONFIG_SOC_CAMERA_OV9640 is not set
-# CONFIG_SOC_CAMERA_OV9740 is not set
-# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_SOC_CAMERA is not set
CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
CONFIG_V4L_USB_DRIVERS=y
# CONFIG_USB_VIDEO_CLASS is not set
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
@@ -1335,6 +1360,8 @@ CONFIG_USB_GSPCA=m
# CONFIG_VIDEO_PVRUSB2 is not set
# CONFIG_VIDEO_HDPVR is not set
# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_TM6000 is not set
# CONFIG_VIDEO_USBVISION is not set
# CONFIG_USB_ET61X251 is not set
# CONFIG_USB_SN9C102 is not set
@@ -1343,7 +1370,20 @@ CONFIG_USB_GSPCA=m
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_RADIO_WL1273 is not set
+
+#
+# Texas Instruments WL128x FM driver (ST based)
+#
#
# Graphics support
@@ -1355,9 +1395,9 @@ CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
@@ -1368,25 +1408,70 @@ CONFIG_FB=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_BROADSHEET is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_LOGO is not set
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_EDID=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_TVOUT_TVE=y
+CONFIG_FB_MXC_SII902X=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=y
# CONFIG_SOUND_OSS_CORE is not set
CONFIG_SND=y
@@ -1582,6 +1667,7 @@ CONFIG_USB_EHCI_MXC=y
CONFIG_USB_GADGET=m
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_USB_FSL_USB2=m
@@ -1752,7 +1838,9 @@ CONFIG_IOMMU_SUPPORT=y
#
# MXC support drivers
#
-# CONFIG_MXC_IPU is not set
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3H=y
#
# MXC VPU(Video Processing Unit) support
@@ -1924,7 +2012,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
#
# Kernel hacking
#
-# CONFIG_PRINTK_TIME is not set
+CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
@@ -1932,7 +2020,7 @@ CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_DEBUG_KERNEL=y
@@ -1974,6 +2062,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
@@ -1995,6 +2084,7 @@ CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c44aa974e79..b477b55155d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -603,6 +603,7 @@ config SOC_IMX6Q
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select USE_OF
+ select ARCH_MXC_IOMUX_V3
help
This enables support for Freescale i.MX6 Quad processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aba73214c2a..8c33917c41f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -70,4 +70,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o suspend-imx6q.o
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 039a7abb165..3ee5edb497e 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/suspend.h>
#include <asm/div64.h>
#include <asm/mach/map.h>
#include <mach/clock.h>
@@ -335,6 +336,12 @@
#define FREQ_650M 650000000
#define FREQ_1300M 1300000000
+#ifdef CONFIG_CLK_DEBUG
+#define __INIT_CLK_DEBUG(n) .name = #n,
+#else
+#define __INIT_CLK_DEBUG(n)
+#endif
+
static struct clk pll1_sys;
static struct clk pll2_bus;
static struct clk pll3_usb_otg;
@@ -415,14 +422,17 @@ static unsigned long get_low_reference_clock_rate(struct clk *clk)
}
static struct clk ckil_clk = {
+ __INIT_CLK_DEBUG(ckil_clk)
.get_rate = get_low_reference_clock_rate,
};
static struct clk ckih_clk = {
+ __INIT_CLK_DEBUG(ckih_clk)
.get_rate = get_high_reference_clock_rate,
};
static struct clk osc_clk = {
+ __INIT_CLK_DEBUG(osc_clk)
.get_rate = get_oscillator_reference_clock_rate,
};
@@ -677,6 +687,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
#define DEF_PLL(name) \
static struct clk name = { \
+ __INIT_CLK_DEBUG(name) \
.enable = pll_enable, \
.disable = pll_disable, \
.get_rate = name##_get_rate, \
@@ -796,6 +807,7 @@ static void pfd_disable(struct clk *clk)
#define DEF_PFD(name, er, es, p) \
static struct clk name = { \
+ __INIT_CLK_DEBUG(name) \
.enable_reg = er, \
.enable_shift = es, \
.enable = pfd_enable, \
@@ -820,6 +832,7 @@ static unsigned long pll2_200m_get_rate(struct clk *clk)
}
static struct clk pll2_200m = {
+ __INIT_CLK_DEBUG(pll2_200m)
.parent = &pll2_pfd_400m,
.get_rate = pll2_200m_get_rate,
};
@@ -830,6 +843,7 @@ static unsigned long pll3_120m_get_rate(struct clk *clk)
}
static struct clk pll3_120m = {
+ __INIT_CLK_DEBUG(pll3_120m)
.parent = &pll3_usb_otg,
.get_rate = pll3_120m_get_rate,
};
@@ -840,6 +854,7 @@ static unsigned long pll3_80m_get_rate(struct clk *clk)
}
static struct clk pll3_80m = {
+ __INIT_CLK_DEBUG(pll3_80m)
.parent = &pll3_usb_otg,
.get_rate = pll3_80m_get_rate,
};
@@ -850,6 +865,7 @@ static unsigned long pll3_60m_get_rate(struct clk *clk)
}
static struct clk pll3_60m = {
+ __INIT_CLK_DEBUG(pll3_60m)
.parent = &pll3_usb_otg,
.get_rate = pll3_60m_get_rate,
};
@@ -877,6 +893,7 @@ static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
}
static struct clk pll1_sw_clk = {
+ __INIT_CLK_DEBUG(pll1_sw_clk)
.parent = &pll1_sys,
.set_parent = pll1_sw_clk_set_parent,
};
@@ -1696,6 +1713,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent)
#define DEF_NG_CLK(name, p) \
static struct clk name = { \
+ __INIT_CLK_DEBUG(name) \
.get_rate = _clk_get_rate, \
.set_rate = _clk_set_rate, \
.round_rate = _clk_round_rate, \
@@ -1723,6 +1741,7 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg);
#define DEF_CLK(name, er, es, p, s) \
static struct clk name = { \
+ __INIT_CLK_DEBUG(name) \
.enable_reg = er, \
.enable_shift = es, \
.enable = _clk_enable, \
@@ -1777,6 +1796,7 @@ DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk, &mmdc_ch0_ipg_clk);
DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk, NULL);
DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk, &mmdc_ch1_ipg_clk);
DEF_CLK(openvg_axi_clk, CCGR3, CG13, &axi_clk, NULL);
+DEF_CLK(ocram_clk, CCGR3, CG14, &ahb_clk, NULL);
DEF_CLK(pwm1_clk, CCGR4, CG8, &ipg_perclk, NULL);
DEF_CLK(pwm2_clk, CCGR4, CG9, &ipg_perclk, NULL);
DEF_CLK(pwm3_clk, CCGR4, CG10, &ipg_perclk, NULL);
@@ -1800,7 +1820,7 @@ DEF_CLK(usdhc3_clk, CCGR6, CG3, &pll2_pfd_400m, NULL);
DEF_CLK(usdhc4_clk, CCGR6, CG4, &pll2_pfd_400m, NULL);
DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL);
DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL);
-DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL);
+DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, &ocram_clk);
static int pcie_clk_enable(struct clk *clk)
{
@@ -1825,6 +1845,7 @@ static void pcie_clk_disable(struct clk *clk)
}
static struct clk pcie_clk = {
+ __INIT_CLK_DEBUG(pcie_clk)
.enable_reg = CCGR4,
.enable_shift = CG0,
.enable = pcie_clk_enable,
@@ -1857,6 +1878,7 @@ static void sata_clk_disable(struct clk *clk)
}
static struct clk sata_clk = {
+ __INIT_CLK_DEBUG(sata_clk)
.enable_reg = CCGR5,
.enable_shift = CG2,
.enable = sata_clk_enable,
@@ -1904,15 +1926,65 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
_REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
_REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
- _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
- _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
- _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
- _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
+ _REGISTER_CLOCK("2080000.pwm", NULL, pwm1_clk),
+ _REGISTER_CLOCK("2084000.pwm", NULL, pwm2_clk),
+ _REGISTER_CLOCK("2088000.pwm", NULL, pwm3_clk),
+ _REGISTER_CLOCK("208c000.pwm", NULL, pwm4_clk),
_REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
_REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+ _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
+ _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
+ _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di0_clk),
+ _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di1_clk),
+ _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di0_clk),
+ _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di1_clk),
+ _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_iahb_clk),
+ _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
+ _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
+ _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk),
+ _REGISTER_CLOCK(NULL, "gpt_clk", gpt_clk),
};
+static u32 ccr, clpcr, ccgr1, ccgr6;
+#define BP_CCR_RBC_EN 27
+void imx6q_ccm_pre_suspend(suspend_state_t state)
+{
+ ccr = readl_relaxed(CCR);
+ if (state == PM_SUSPEND_MEM) {
+ writel_relaxed(ccr | (1 << BP_CCR_RBC_EN), CCR);
+ }
+ clpcr = readl_relaxed(CLPCR);
+
+ /* for GPU */
+ ccgr1 = readl_relaxed(CCGR1);
+ ccgr6 = readl_relaxed(CCGR6);
+}
+
+void imx6q_ccm_gpu_pre_suspend(void)
+{
+ /* disable clocks */
+ writel_relaxed(ccgr1 & 0xf0ffffff, CCGR1);
+ writel_relaxed(ccgr6 & 0x00003fff, CCGR6);
+}
+
+void imx6q_ccm_gpu_post_resume(void)
+{
+ /* enable clocks */
+ writel_relaxed(ccgr1 | 0x0f000000, CCGR1);
+ writel_relaxed(ccgr6 | 0x0000c000, CCGR6);
+}
+
+void imx6q_ccm_post_resume(void)
+{
+ writel_relaxed(ccr, CCR);
+ writel_relaxed(clpcr, CLPCR);
+
+ /* for GPU */
+ writel_relaxed(ccgr1, CCGR1);
+ writel_relaxed(ccgr6, CCGR6);
+}
+
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
u32 val = readl_relaxed(CLPCR);
@@ -1940,9 +2012,18 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
val |= BM_CLPCR_SBYOS;
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
break;
+ case ARM_POWER_OFF:
+ val |= 0x2 << BP_CLPCR_LPM;
+ val |= 0x3 << BP_CLPCR_STBY_COUNT;
+ val |= BM_CLPCR_VSTBY;
+ val |= BM_CLPCR_SBYOS;
+ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+ val |= BM_CLPCR_WB_PER_AT_LPM;
+ break;
default:
return -EINVAL;
}
+
writel_relaxed(val, CLPCR);
return 0;
@@ -1978,13 +2059,15 @@ int __init mx6q_clocks_init(void)
oscillator_reference = rate;
}
- for (i = 0; i < ARRAY_SIZE(lookups); i++)
+ for (i = 0; i < ARRAY_SIZE(lookups); i++) {
clkdev_add(&lookups[i]);
+ clk_debug_register(lookups[i].clk);
+ }
/* only keep necessary clocks on */
- writel_relaxed(0x3 << CG0 | 0x3 << CG1 | 0x3 << CG2, CCGR0);
+ writel_relaxed(0x3 << CG0 | 0x3 << CG1 | 0x3 << CG2, CCGR0);
writel_relaxed(0x3 << CG8 | 0x3 << CG9 | 0x3 << CG10, CCGR2);
- writel_relaxed(0x3 << CG10 | 0x3 << CG12, CCGR3);
+ writel_relaxed(0x3 << CG10 | 0x3 << CG12 | 0x1 << CG14, CCGR3);
writel_relaxed(0x3 << CG4 | 0x3 << CG6 | 0x3 << CG7, CCGR4);
writel_relaxed(0x3 << CG0, CCGR5);
writel_relaxed(0, CCGR6);
@@ -2005,6 +2088,9 @@ int __init mx6q_clocks_init(void)
clk_set_rate(&asrc_serial_clk, 1500000);
clk_set_rate(&enfc_clk, 11000000);
+ /* Lower the ipg_perclk frequency to 8.25MHz. */
+ clk_set_rate(&ipg_perclk, 8250000);
+
/*
* Before pinctrl API is available, we have to rely on the pad
* configuration set up by bootloader. For usdhc example here,
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index e1537f9e45b..3462bb4443c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -15,41 +15,95 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/suspend.h>
#include <asm/hardware/gic.h>
+#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
+#define GPC_ISR1 0x018
+#define GPC_ISR2 0x01c
+#define GPC_ISR3 0x020
+#define GPC_ISR4 0x024
+#define GPC_PGC_GPU_PGCR 0x260
#define GPC_PGC_CPU_PDN 0x2a0
+#define GPC_PGC_CPU_PUPSCR 0x2a4
+#define GPC_PGC_CPU_PDNSCR 0x2a8
#define IMR_NUM 4
+#define ISR_NUM 4
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
+static u32 gpc_saved_cntr;
+static u32 gpc_saved_cpu_pdn;
+static u32 gpc_saved_cpu_pupscr;
+static u32 gpc_saved_cpu_pdnscr;
-void imx_gpc_pre_suspend(void)
+bool imx_gpc_wake_irq_pending(void)
+{
+ void __iomem *reg_isr1 = gpc_base + GPC_ISR1;
+ int i;
+ u32 val;
+
+ for (i = 0; i < ISR_NUM; i++) {
+ val = readl_relaxed(reg_isr1 + i * 4);
+ if (val & gpc_wake_irqs[i])
+ return true;
+ }
+
+ return false;
+}
+
+void imx_gpc_pre_suspend(suspend_state_t state)
{
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
int i;
- /* Tell GPC to power off ARM core when suspend */
- writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+ gpc_saved_cntr = readl_relaxed(gpc_base + GPC_CNTR);
+ gpc_saved_cpu_pdn = readl_relaxed(gpc_base + GPC_PGC_CPU_PDN);
+ gpc_saved_cpu_pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);
+ gpc_saved_cpu_pdnscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR);
for (i = 0; i < IMR_NUM; i++) {
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
}
+
+ /* Power down and power up sequence */
+ writel_relaxed(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PUPSCR);
+ writel_relaxed(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PDNSCR);
+
+ if (state == PM_SUSPEND_MEM) {
+ /* Tell GPC to power off ARM core when suspend */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+
+ /* GPU PGCR */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PGCR);
+ /* GPU/VPU power down request */
+ writel_relaxed(0x1, gpc_base + GPC_CNTR);
+ }
}
-void imx_gpc_post_resume(void)
+void imx_gpc_post_resume(suspend_state_t state)
{
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
int i;
- /* Keep ARM core powered on for other low-power modes */
- writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
+ writel_relaxed(gpc_saved_cpu_pdnscr, gpc_base + GPC_PGC_CPU_PDNSCR);
+ writel_relaxed(gpc_saved_cpu_pupscr, gpc_base + GPC_PGC_CPU_PUPSCR);
+ writel_relaxed(gpc_saved_cpu_pdn, gpc_base + GPC_PGC_CPU_PDN);
+ writel_relaxed(gpc_saved_cntr, gpc_base + GPC_CNTR);
for (i = 0; i < IMR_NUM; i++)
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+
+ if (state == PM_SUSPEND_MEM) {
+ /* GPU PGCR */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PGCR);
+ /* GPU/VPU power down request */
+ writel_relaxed(gpc_saved_cntr | 0x2, gpc_base + GPC_CNTR);
+ }
}
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 240fad03927..940a91e9bb6 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -17,27 +17,136 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/dma-mapping.h>
+#include <linux/iram_alloc.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/hardware.h>
+#include <mach/ipu-v3.h>
+#include <mach/mxc_vpu.h>
+#include <mach/iomux-mx6q.h>
+
+static iomux_v3_cfg_t mx6q_sabr_pads[] = {
+ /* DISPLAY */
+ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ /* PWM1 */
+ MX6Q_PAD_SD1_CMD__PWM4_PWMO,
+ /* I2C2 */
+ MX6Q_PAD_KEY_COL3__I2C2_SCL,
+ MX6Q_PAD_KEY_ROW3__I2C2_SDA,
+ /* GPIO */
+ MX6Q_PAD_NANDF_D0__GPIO_2_0,
+ MX6Q_PAD_EIM_D23__GPIO_3_23,
+};
+
+static int mx6q_ipuv3_init(int id)
+{
+ imx_reset_ipu(id);
+ return 0;
+}
+
+static void mx6q_ipuv3_pg(int enable)
+{
+ /*TODO*/
+}
+
+static struct imx_ipuv3_platform_data ipuv3_pdata = {
+ .rev = 4,
+ .init = mx6q_ipuv3_init,
+ .pg = mx6q_ipuv3_pg,
+};
+
+static void mx6q_vpu_reset(void)
+{
+ imx_reset_vpu();
+}
+
+static struct mxc_vpu_platform_data vpu_pdata = {
+ .iram_enable = true,
+ .iram_size = 0x21000,
+ .reset = mx6q_vpu_reset,
+};
+
+static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("fsl,ipuv3", MX6Q_IPU1_BASE_ADDR, "imx-ipuv3.0", &ipuv3_pdata),
+ OF_DEV_AUXDATA("fsl,ipuv3", MX6Q_IPU2_BASE_ADDR, "imx-ipuv3.1", &ipuv3_pdata),
+ OF_DEV_AUXDATA("fsl,vpu", MX6Q_VPU_BASE_ADDR, "mxc_vpu.0", &vpu_pdata),
+};
static void __init imx6q_init_machine(void)
{
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ mxc_iomux_v3_setup_multiple_pads(mx6q_sabr_pads,
+ ARRAY_SIZE(mx6q_sabr_pads));
+
+ iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE);
+
+ of_platform_populate(NULL, of_default_bus_match_table, imx6q_auxdata_lookup, NULL);
imx6q_pm_init();
}
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+void __iomem *iomux_base;
+static struct map_desc imx_mx6q_fix_desc[] = {
+ {
+ .virtual = MX6Q_IO_P2V(MX6Q_IOMUXC_BASE_ADDR),
+ .pfn = __phys_to_pfn(MX6Q_IOMUXC_BASE_ADDR),
+ .length = MX6Q_IOMUXC_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init mx6q_fix_map_io(void)
+{
+ iotable_init(imx_mx6q_fix_desc, ARRAY_SIZE(imx_mx6q_fix_desc));
+ iomux_base = (void __iomem *)MX6Q_IO_P2V(MX6Q_IOMUXC_BASE_ADDR);
+ mxc_iomux_v3_init(iomux_base);
+}
+
static void __init imx6q_map_io(void)
{
+ mx6q_fix_map_io();
imx_lluart_map_io();
imx_scu_map_io();
imx6q_clock_map_io();
init_consistent_dma_size(SZ_64M);
+
+ if (!system_rev)
+ system_rev = 0x63000;
}
static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index c461e98496c..28575b77c0d 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -21,6 +21,9 @@
#define BP_MMDC_MAPSR_PSD 0
#define BP_MMDC_MAPSR_PSS 4
+static int idx;
+void __iomem *mmdc_base_array[2];
+
static int __devinit imx_mmdc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -31,6 +34,8 @@ static int __devinit imx_mmdc_probe(struct platform_device *pdev)
mmdc_base = of_iomap(np, 0);
WARN_ON(!mmdc_base);
+ mmdc_base_array[idx++] = mmdc_base;
+
reg = mmdc_base + MMDC_MAPSR;
/* Enable automatic power saving */
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f20f191d7cc..3819789e741 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -14,32 +14,111 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/suspend.h>
+#include <linux/iram_alloc.h>
+#include <linux/delay.h>
#include <asm/cacheflush.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/tlb.h>
+#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/hardware.h>
+#define ANATOP_REG_2P5 0x130
+#define ANATOP_REG_CORE 0x140
+
extern unsigned long phys_l2x0_saved_regs;
-static int imx6q_suspend_finish(unsigned long val)
+static void __iomem *anatop_base;
+static u32 anatop[2];
+
+static void *suspend_iram_base;
+static unsigned long iram_paddr, cpaddr;
+static void (*suspend_in_iram)(suspend_state_t state,
+ unsigned long iram_paddr, unsigned long suspend_iram_base) = NULL;
+
+extern void mx6q_suspend(suspend_state_t state);
+
+static void imx6q_anatop_pre_suspend(void)
{
- cpu_do_idle();
- return 0;
+ u32 reg;
+
+ /* save registers */
+ anatop[0] = readl_relaxed(anatop_base + ANATOP_REG_2P5);
+ anatop[1] = readl_relaxed(anatop_base + ANATOP_REG_CORE);
+
+ /* Enable weak 2P5 linear regulator */
+ reg = readl_relaxed(anatop_base + ANATOP_REG_2P5);
+ reg |= 1 << 18;
+ writel_relaxed(reg, anatop_base + ANATOP_REG_2P5);
+ /* Make sure ARM and SOC domain has same voltage */
+ reg = readl_relaxed(anatop_base + ANATOP_REG_CORE);
+ reg &= ~(0x1f << 18);
+ reg |= (reg & 0x1f) << 18;
+ writel_relaxed(reg, anatop_base + ANATOP_REG_CORE);
+
+ /* gpu: power off pu reg1 */
+ reg = readl_relaxed(anatop_base + ANATOP_REG_CORE);
+ reg &= ~0x0003fe00;
+ writel_relaxed(reg, anatop_base + ANATOP_REG_CORE);
+}
+
+static void imx6q_anatop_post_resume(void)
+{
+ u32 reg;
+
+ /* restore registers */
+ writel_relaxed(anatop[0], anatop_base + ANATOP_REG_2P5);
+ writel_relaxed(anatop[1], anatop_base + ANATOP_REG_CORE);
+
+ /*gpu: power on pu reg1 */
+ reg = readl_relaxed(anatop_base + ANATOP_REG_CORE);
+ reg &= ~0x0003fe00;
+ reg |= 0x10 << 9; /* 1.1v */
+ writel_relaxed(reg, anatop_base + ANATOP_REG_CORE);
+ mdelay(10);
}
static int imx6q_pm_enter(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_MEM:
+ if (imx_gpc_wake_irq_pending())
+ return 0;
+
+ imx6q_ccm_pre_suspend(state);
+ imx6q_set_lpm(ARM_POWER_OFF);
+ imx_gpc_pre_suspend(state);
+ imx6q_ccm_gpu_pre_suspend();
+ imx6q_anatop_pre_suspend();
+
+ suspend_in_iram(state, (unsigned long)iram_paddr,
+ (unsigned long)suspend_iram_base);
+
+ imx_smp_prepare();
+
+ imx6q_anatop_post_resume();
+ imx6q_ccm_gpu_post_resume();
+ imx_gpc_post_resume(state);
+ udelay(10);
+ imx6q_ccm_post_resume();
+ break;
+ case PM_SUSPEND_STANDBY:
+ if (imx_gpc_wake_irq_pending())
+ return 0;
+
+ imx6q_ccm_pre_suspend(state);
imx6q_set_lpm(STOP_POWER_OFF);
- imx_gpc_pre_suspend();
- imx_set_cpu_jump(0, v7_cpu_resume);
- /* Zzz ... */
- cpu_suspend(0, imx6q_suspend_finish);
+ imx_gpc_pre_suspend(state);
+
+ suspend_in_iram(state, (unsigned long)iram_paddr,
+ (unsigned long)suspend_iram_base);
+
imx_smp_prepare();
- imx_gpc_post_resume();
+
+ imx_gpc_post_resume(state);
+ imx6q_ccm_post_resume();
break;
default:
return -EINVAL;
@@ -48,9 +127,14 @@ static int imx6q_pm_enter(suspend_state_t state)
return 0;
}
+static int imx6q_pm_valid(suspend_state_t state)
+{
+ return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
static const struct platform_suspend_ops imx6q_pm_ops = {
.enter = imx6q_pm_enter,
- .valid = suspend_valid_only_mem,
+ .valid = imx6q_pm_valid,
};
void __init imx6q_pm_init(void)
@@ -63,8 +147,29 @@ void __init imx6q_pm_init(void)
* have to take care of restoring on its own. So we save physical
* address of the data structure used by l2x0 core to save registers,
* and later restore the necessary ones in imx6q resume entry.
+ * Need to run the suspend code from IRAM as the DDR needs
+ * to be put into low power mode manually.
*/
phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+ anatop_base = IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR);
+
suspend_set_ops(&imx6q_pm_ops);
+
+ /* Move suspend routine into iRAM */
+ cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr);
+ /* Need to remap the area here since we want the memory region
+ to be executable. */
+ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
+ MT_MEMORY_NONCACHED);
+ pr_info("cpaddr = %x suspend_iram_base=%x\n",
+ (unsigned int)cpaddr, (unsigned int)suspend_iram_base);
+
+ /*
+ * Need to run the suspend code from IRAM as the DDR needs
+ * to be put into low power mode manually.
+ */
+ memcpy((void *)cpaddr, mx6q_suspend, SZ_4K);
+
+ suspend_in_iram = (void *)suspend_iram_base;
}
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index a8e33681b73..54cf7e18d7a 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -18,16 +18,61 @@
#include <asm/unified.h>
#define SRC_SCR 0x000
+#define SRC_SIMR 0x018
#define SRC_GPR1 0x020
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE 22
+#define BP_SRC_SCR_VPU_RST 2
+#define BP_SRC_SCR_IPU1_RST 3
+#define BP_SRC_SCR_IPU2_RST 12
+#define BP_SRC_SIMR_VPU_MASK 1
+#define BP_SRC_SIMR_IPU1_MASK 2
+#define BP_SRC_SIMR_IPU2_MASK 4
-static void __iomem *src_base;
+void __iomem *src_base;
#ifndef CONFIG_SMP
#define cpu_logical_map(cpu) 0
#endif
+void imx_reset_vpu(void)
+{
+ u32 val;
+
+ /* mask interrupt due to vpu passed reset */
+ val = readl_relaxed(src_base + SRC_SIMR);
+ val |= (1 << BP_SRC_SIMR_VPU_MASK);
+ writel_relaxed(val, src_base + SRC_SIMR);
+
+ val = readl_relaxed(src_base + SRC_SCR);
+ val |= (1 << BP_SRC_SCR_VPU_RST); /* reset vpu */
+ writel_relaxed(val, src_base + SRC_SCR);
+ while (readl_relaxed(src_base + SRC_SCR) &
+ (1 << BP_SRC_SCR_VPU_RST))
+ ;
+}
+
+void imx_reset_ipu(int ipu)
+{
+ u32 val;
+ u32 scr_off = ipu ? BP_SRC_SCR_IPU2_RST : BP_SRC_SCR_IPU1_RST;
+ u32 simr_off = ipu ? BP_SRC_SIMR_IPU2_MASK : BP_SRC_SIMR_IPU1_MASK;
+
+ /* mask interrupt due to ipu passed reset */
+ val = readl_relaxed(src_base + SRC_SIMR);
+ val |= (1 << simr_off);
+ writel_relaxed(val, src_base + SRC_SIMR);
+
+ /* reset the IPU */
+ val = readl_relaxed(src_base + SRC_SCR);
+ val |= (1 << scr_off);
+ writel_relaxed(val, src_base + SRC_SCR);
+
+ while (readl_relaxed(src_base + SRC_SCR) &
+ (1 << scr_off))
+ ;
+}
+
void imx_enable_cpu(int cpu, bool enable)
{
u32 mask, val;
diff --git a/arch/arm/mach-imx/suspend-imx6q.S b/arch/arm/mach-imx/suspend-imx6q.S
new file mode 100644
index 00000000000..11a78631838
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-imx6q.S
@@ -0,0 +1,695 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+#include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define MX6Q_PHYS_OFFSET UL(0x10000000)
+
+#define ARM_CTRL_DCACHE (1 << 2)
+#define ARM_CTRL_ICACHE (1 << 12)
+#define ARM_AUXCR_L2EN (1 << 1)
+#define TTRBIT_MASK 0xffffc000
+#define TABLE_INDEX_MASK 0xfff00000
+#define TABLE_ENTRY 0x00000c02
+#define CACHE_DISABLE_MASK 0xffffe7fb
+#define MMDC_MAPSR_OFFSET 0x404
+#define MMDC_MAPSR_PSS (1 << 4)
+#define MMDC_MAPSR_PSD (1 << 0)
+#define IRAM_SUSPEND_SIZE (1 << 12)
+
+#define SRC_SCR_OFFSET 0x000
+#define SRC_SBMR_OFFSET 0x004
+#define SRC_SRSR_OFFSET 0x008
+#define SRC_SAIAR_OFFSET 0x00c
+#define SRC_SAIRAR_OFFSET 0x010
+#define SRC_SISR_OFFSET 0x014
+#define SRC_SIMR_OFFSET 0x018
+#define SRC_SBMR2_OFFSET 0x01c
+#define SRC_GPR1_OFFSET 0x020
+#define SRC_GPR2_OFFSET 0x024
+#define SRC_GPR3_OFFSET 0x028
+#define SRC_GPR4_OFFSET 0x02c
+#define SRC_GPR5_OFFSET 0x030
+#define SRC_GPR6_OFFSET 0x034
+#define SRC_GPR7_OFFSET 0x038
+#define SRC_GPR8_OFFSET 0x03c
+#define SRC_GPR9_OFFSET 0x040
+#define SRC_GPR10_OFFSET 0x044
+
+#define BP_SRC_SCR_CORE0_RST 13
+#define BP_SRC_SCR_CORES_DBG_RST 21
+#define BP_SRC_SCR_CORE1_ENABLE 22
+
+/*************************************************************
+mx6q_suspend:
+
+Suspend the processor (eg, wait for interrupt).
+Set the DDR into Self Refresh
+IRQs are already disabled.
+
+The following code contain both standby and
+dormant mode for MX6, decided by the parameter
+passed in r0:
+see define in include/linux/suspend.h
+1 -> cpu enter stop mode;
+3 -> cpu enter dormant mode.
+r1: iram_paddr
+r2: suspend_iram_base
+*************************************************************/
+ .macro ddr_io_save
+
+ ldr r4, [r1, #0x5ac] /* DRAM_DQM0 */
+ ldr r5, [r1, #0x5b4] /* DRAM_DQM1 */
+ ldr r6, [r1, #0x528] /* DRAM_DQM2 */
+ ldr r7, [r1, #0x520] /* DRAM_DQM3 */
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r1, #0x514] /* DRAM_DQM4 */
+ ldr r5, [r1, #0x510] /* DRAM_DQM5 */
+ ldr r6, [r1, #0x5bc] /* DRAM_DQM6 */
+ ldr r7, [r1, #0x5c4] /* DRAM_DQM7 */
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r1, #0x56c] /* DRAM_CAS */
+ ldr r5, [r1, #0x578] /* DRAM_RAS */
+ ldr r6, [r1, #0x588] /* DRAM_SDCLK_0 */
+ ldr r7, [r1, #0x594] /* DRAM_SDCLK_1 */
+ stmfd r0!, {r4-r7}
+
+ ldr r5, [r1, #0x750] /* DDRMODE_CTL */
+ ldr r6, [r1, #0x774] /* DDRMODE */
+ stmfd r0!, {r5-r6}
+
+ ldr r4, [r1, #0x5a8] /* DRAM_SDQS0 */
+ ldr r5, [r1, #0x5b0] /* DRAM_SDQS1 */
+ ldr r6, [r1, #0x524] /* DRAM_SDQS2 */
+ ldr r7, [r1, #0x51c] /* DRAM_SDQS3 */
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r1, #0x518] /* DRAM_SDQS4 */
+ ldr r5, [r1, #0x50c] /* DRAM_SDQS5 */
+ ldr r6, [r1, #0x5b8] /* DRAM_SDQS6 */
+ ldr r7, [r1, #0x5c0] /* DRAM_SDQS7 */
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r1, #0x784] /* GPR_B0DS */
+ ldr r5, [r1, #0x788] /* GPR_B1DS */
+ ldr r6, [r1, #0x794] /* GPR_B2DS */
+ ldr r7, [r1, #0x79c] /* GPR_B3DS */
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r1, #0x7a0] /* GPR_B4DS */
+ ldr r5, [r1, #0x7a4] /* GPR_B5DS */
+ ldr r6, [r1, #0x7a8] /* GPR_B6DS */
+ ldr r7, [r1, #0x748] /* GPR_B7DS */
+ stmfd r0!, {r4-r7}
+
+ ldr r5, [r1, #0x74c] /* GPR_ADDS*/
+ ldr r6, [r1, #0x59c] /* DRAM_SODT0*/
+ ldr r7, [r1, #0x5a0] /* DRAM_SODT1*/
+ stmfd r0!, {r5-r7}
+
+ .endm
+
+ .macro ddr_io_restore
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x5ac] /* DRAM_DQM0 */
+ str r5, [r1, #0x5b4] /* DRAM_DQM1 */
+ str r6, [r1, #0x528] /* DRAM_DQM2 */
+ str r7, [r1, #0x520] /* DRAM_DQM3 */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x514] /* DRAM_DQM4 */
+ str r5, [r1, #0x510] /* DRAM_DQM5 */
+ str r6, [r1, #0x5bc] /* DRAM_DQM6 */
+ str r7, [r1, #0x5c4] /* DRAM_DQM7 */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x56c] /* DRAM_CAS */
+ str r5, [r1, #0x578] /* DRAM_RAS */
+ str r6, [r1, #0x588] /* DRAM_SDCLK_0 */
+ str r7, [r1, #0x594] /* DRAM_SDCLK_1 */
+
+ ldmea r0!, {r5-r6}
+ str r5, [r1, #0x750] /* DDRMODE_CTL */
+ str r6, [r1, #0x774] /* DDRMODE */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x5a8] /* DRAM_SDQS0 */
+ str r5, [r1, #0x5b0] /* DRAM_SDQS1 */
+ str r6, [r1, #0x524] /* DRAM_SDQS2 */
+ str r7, [r1, #0x51c] /* DRAM_SDQS3 */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x518] /* DRAM_SDQS4 */
+ str r5, [r1, #0x50c] /* DRAM_SDQS5 */
+ str r6, [r1, #0x5b8] /* DRAM_SDQS6 */
+ str r7, [r1, #0x5c0] /* DRAM_SDQS7 */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x784] /* GPR_B0DS */
+ str r5, [r1, #0x788] /* GPR_B1DS */
+ str r6, [r1, #0x794] /* GPR_B2DS */
+ str r7, [r1, #0x79c] /* GPR_B3DS */
+
+ ldmea r0!, {r4-r7}
+ str r4, [r1, #0x7a0] /* GPR_B4DS */
+ str r5, [r1, #0x7a4] /* GPR_B5DS */
+ str r6, [r1, #0x7a8] /* GPR_B6DS */
+ str r7, [r1, #0x748] /* GPR_B7DS */
+
+ ldmea r0!, {r5-r7}
+ str r5, [r1, #0x74c] /* GPR_ADDS*/
+ str r6, [r1, #0x59c] /* DRAM_SODT0*/
+ str r7, [r1, #0x5a0] /* DRAM_SODT1*/
+
+ .endm
+
+ .macro ddr_io_set_lpm
+
+ mov r0, #0
+ str r0, [r1, #0x5ac] /* DRAM_DQM0 */
+ str r0, [r1, #0x5b4] /* DRAM_DQM1 */
+ str r0, [r1, #0x528] /* DRAM_DQM2 */
+ str r0, [r1, #0x520] /* DRAM_DQM3 */
+
+ str r0, [r1, #0x514] /* DRAM_DQM4 */
+ str r0, [r1, #0x510] /* DRAM_DQM5 */
+ str r0, [r1, #0x5bc] /* DRAM_DQM6 */
+ str r0, [r1, #0x5c4] /* DRAM_DQM7 */
+
+ str r0, [r1, #0x56c] /* DRAM_CAS */
+ str r0, [r1, #0x578] /* DRAM_RAS */
+ str r0, [r1, #0x588] /* DRAM_SDCLK_0 */
+ str r0, [r1, #0x594] /* DRAM_SDCLK_1 */
+
+ str r0, [r1, #0x750] /* DDRMODE_CTL */
+ str r0, [r1, #0x774] /* DDRMODE */
+
+ str r0, [r1, #0x5a8] /* DRAM_SDQS0 */
+ str r0, [r1, #0x5b0] /* DRAM_SDQS1 */
+ str r0, [r1, #0x524] /* DRAM_SDQS2 */
+ str r0, [r1, #0x51c] /* DRAM_SDQS3 */
+
+ str r0, [r1, #0x518] /* DRAM_SDQS4 */
+ str r0, [r1, #0x50c] /* DRAM_SDQS5 */
+ str r0, [r1, #0x5b8] /* DRAM_SDQS6 */
+ str r0, [r1, #0x5c0] /* DRAM_SDQS7 */
+
+ str r0, [r1, #0x784] /* GPR_B0DS */
+ str r0, [r1, #0x788] /* GPR_B1DS */
+ str r0, [r1, #0x794] /* GPR_B2DS */
+ str r0, [r1, #0x79c] /* GPR_B3DS */
+
+ str r0, [r1, #0x7a0] /* GPR_B4DS */
+ str r0, [r1, #0x7a4] /* GPR_B5DS */
+ str r0, [r1, #0x7a8] /* GPR_B6DS */
+ str r0, [r1, #0x748] /* GPR_B7DS */
+
+ str r0, [r1, #0x74c] /* GPR_ADDS*/
+ str r0, [r1, #0x59c] /* DRAM_SODT0*/
+ str r0, [r1, #0x5a0] /* DRAM_SODT1*/
+
+ .endm
+
+ENTRY(mx6q_suspend)
+ stmfd sp!, {r0-r12} @ Save registers
+/*************************************************************
+suspend mode entry
+*************************************************************/
+
+ cmp r0, #0x1
+ bne dormant /* dormant mode */
+
+ dsb
+ wfi
+
+ nop
+ nop
+ nop
+ nop
+ /* Due to the L2 cache errata(TKT065875)
+ , need to wait at least 170ns, each IO read
+ takes about 76ns, but the actual wait time
+ to make system more stable is about 380ns */
+ ldr r1, =src_base
+ ldr r0, [r1]
+ ldr r1, [r0]
+ ldr r1, [r0, #0x4]
+ ldr r1, [r0, #0x8]
+ ldr r1, [r0, #0xc]
+ ldr r1, [r0, #0x10]
+/***********************************************************
+never run to here
+************************************************************/
+ b out /* exit standby */
+
+/************************************************************
+dormant entry, data save in stack, save sp in the src_gpr2
+************************************************************/
+dormant:
+ mov r3, r1
+ mov r0, r1
+ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */
+ ldr r5, =src_base
+ ldr r4, [r5]
+ str r0, [r4, #SRC_GPR2_OFFSET] /* set src_gpr2 */
+/************************************************************
+saved register and context as below:
+ ddr_iomux set
+ sp
+ spsr
+ lr
+ CPACR
+ TTBR0
+ TTBR1
+ TTBCR
+ DACR
+ PRRR
+ NMRR
+ ACTLR
+ Context ID
+ User r/w thread ID
+ Secure or NS VBAR
+ CPSR
+ SCTLR
+************************************************************/
+ddr_iomux_save:
+ /* save mmdc iomux setting, stack is from the tail of
+ iram_suspend base */
+
+ mov r0, r2 /* get suspend_iram_base */
+ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */
+ ldr r4, =iomux_base
+ ldr r1, [r4]
+
+ ddr_io_save
+
+ mov r4, sp @ Store sp
+ mrs r5, spsr @ Store spsr
+ mov r6, lr @ Store lr
+ stmfd r0!, {r4-r6}
+
+ /* c1 and c2 registers */
+ mrc p15, 0, r4, c1, c0, 2 @ CPACR
+ mrc p15, 0, r5, c2, c0, 0 @ TTBR0
+ mrc p15, 0, r6, c2, c0, 1 @ TTBR1
+ mrc p15, 0, r7, c2, c0, 2 @ TTBCR
+ stmfd r0!, {r4-r7}
+
+ /* c3 and c10 registers */
+ mrc p15, 0, r4, c3, c0, 0 @ DACR
+ mrc p15, 0, r5, c10, c2, 0 @ PRRR
+ mrc p15, 0, r6, c10, c2, 1 @ NMRR
+ mrc p15, 0, r7, c1, c0, 1 @ ACTLR
+ stmfd r0!,{r4-r7}
+
+ /* c12, c13 and CPSR registers */
+ mrc p15, 0, r4, c13, c0, 1 @ Context ID
+ mrc p15, 0, r5, c13, c0, 2 @ User r/w thread ID
+ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS VBAR
+ mrs r7, cpsr @ Store CPSR
+ stmfd r0!, {r4-r7}
+
+ /* c1 control register */
+ mrc p15, 0, r4, c1, c0, 0 @ SCTLR
+ stmfd r0!, {r4}
+
+#ifdef CONFIG_CACHE_L2X0
+ ldr r4, =l2x0_base
+ ldr r2, [r4]
+
+ ldr r4, [r2, #L2X0_CTRL]
+ ldr r5, [r2, #L2X0_AUX_CTRL]
+ ldr r6, [r2, #L2X0_TAG_LATENCY_CTRL]
+ ldr r7, [r2, #L2X0_DATA_LATENCY_CTRL]
+ stmfd r0!, {r4-r7}
+
+ ldr r4, [r2, #L2X0_PREFETCH_CTRL]
+ ldr r5, [r2, #L2X0_POWER_CTRL]
+ stmfd r0!, {r4-r5}
+#endif
+ /*
+ * Flush all data from the L1 data cache before disabling
+ * SCTLR.C bit.
+ */
+ push {r0-r12, lr}
+ ldr r0, =v7_flush_dcache_all
+ mov lr, pc
+ mov pc, r0
+ pop {r0-r12, lr}
+
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /*
+ * Invalidate L1 data cache. Even though only invalidate is
+ * necessary exported flush API is used here. Doing clean
+ * on already clean cache would be almost NOP.
+ */
+ push {r0-r12, lr}
+ ldr r0, =v7_flush_dcache_all
+ mov lr, pc
+ mov pc, r0
+ pop {r0-r12, lr}
+
+ /*
+ * Execute an ISB instruction to ensure that all of the
+ * CP15 register changes have been committed.
+ */
+ isb
+
+ /*
+ * Execute a barrier instruction to ensure that all cache,
+ * TLB and branch predictor maintenance operations issued
+ * by any CPU in the cluster have completed.
+ */
+ dsb
+ dmb
+
+ /* Clean L2 cache to write the dirty data into DRAM to make
+ sure the data alignment between DRAM and L2 cache.
+ */
+#ifdef CONFIG_CACHE_L2X0
+ /* Clean L2 cache here */
+ ldr r0, =l2x0_base
+ ldr r1, [r0]
+ /* Make way to 0xFFFF 16 ways */
+ mov r0, #0x10000
+ sub r0, r0, #0x1
+ /* 0x7BC is L2X0_CLEAN_WAY */
+ mov r4, #0x700
+ orr r4, #0xBC
+ str r0, [r1, r4]
+
+wait:
+ ldr r2, [r1, r4]
+ ands r2, r2, r0
+ bne wait
+l2x0_sync:
+ mov r2, #0x0
+ /* 0x730 is L2X0_CACHE_SYNC */
+ mov r4, #0x700
+ orr r4, #0x30
+ str r2, [r1, r4]
+sync:
+ ldr r2, [r1, r4]
+ ands r2, r2, #0x1
+ bne sync
+#endif
+/****************************************************************
+set ddr iomux to low power mode
+****************************************************************/
+ ldr r0, =mmdc_base_array
+ ldr r1, [r0]
+ ldr r0, [r1, #MMDC_MAPSR_OFFSET]
+ bic r0, #MMDC_MAPSR_PSD /* enable lpm */
+ str r0, [r1, #MMDC_MAPSR_OFFSET]
+refresh:
+ ldr r0, [r1, #MMDC_MAPSR_OFFSET] /* MMDC_MAPSR */
+ and r0, r0, #MMDC_MAPSR_PSS /* PSS bit */
+ cmp r0, #0
+ beq refresh
+
+ /* set mmdc iomux to low power mode */
+ ldr r0, =iomux_base
+ ldr r1, [r0]
+
+ ddr_io_set_lpm
+/****************************************************************
+save resume pointer into SRC_GPR1
+****************************************************************/
+ ldr r0, =mx6q_suspend
+ ldr r1, =resume
+ sub r1, r1, r0
+ add r3, r3, r1
+ ldr r0, =src_base
+ ldr r1, [r0]
+ str r3, [r1, #SRC_GPR1_OFFSET]
+/****************************************************************
+execute a wfi instruction to let SOC go into stop mode.
+****************************************************************/
+ wfi
+
+ nop
+ nop
+ nop
+ nop
+
+/****************************************************************
+if go here, means there is a wakeup irq pending, we should resume
+system immediately.
+****************************************************************/
+ mov r0, r2 /* get suspend_iram_base */
+ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */
+
+ ldr r3, =iomux_base
+ ldr r1, [r3]
+
+ ddr_io_restore
+
+ mrc p15, 0, r1, c1, c0, 0
+ orr r1, r1, #(1 << 2) @ Enable the C bit
+ mcr p15, 0, r1, c1, c0, 0
+
+ b out /* exit standby */
+
+/****************************************************************
+when SOC exit stop mode, arm core restart from here, currently
+are running with MMU off.
+****************************************************************/
+resume:
+ ldr r0, =MX6Q_SRC_BASE_ADDR
+ /* Due to the L2 cache errata(TKT065875)
+ , need to wait at least 170ns, each IO read
+ takes about 76ns, but the actual wait time
+ to make system more stable is about 380ns */
+ ldr r1, [r0]
+ ldr r1, [r0, #0x4]
+ ldr r1, [r0, #0x8]
+ ldr r1, [r0, #0xc]
+ ldr r1, [r0, #0x10]
+ mov r1, #0x0
+ str r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */
+ ldr r0, [r0, #SRC_GPR2_OFFSET]
+
+ ldr r1, =MX6Q_IOMUXC_BASE_ADDR
+ ddr_io_restore
+
+ /* Restore cp15 registers */
+ ldmea r0!, {r4-r6}
+ mov sp, r4
+ msr spsr_cxsf, r5 @ Restore spsr
+ mov lr, r6 @ Restore lr
+
+ /* c1 and c2 registers */
+ ldmea r0!, {r4-r7}
+ mcr p15, 0, r4, c1, c0, 2 @ CPACR
+ mcr p15, 0, r5, c2, c0, 0 @ TTBR0
+ mcr p15, 0, r6, c2, c0, 1 @ TTBR1
+ mcr p15, 0, r7, c2, c0, 2 @ TTBCR
+
+ /* c3 and c10 registers */
+ ldmea r0!,{r4-r7}
+ mcr p15, 0, r4, c3, c0, 0 @ DACR
+ mcr p15, 0, r5, c10, c2, 0 @ PRRR
+ mcr p15, 0, r6, c10, c2, 1 @ NMRR
+ mcr p15, 0, r7, c1, c0, 1 @ ACTLR
+
+ /* c12, c13 and CPSR registers */
+ ldmea r0!,{r4-r7}
+ mcr p15, 0, r4, c13, c0, 1 @ Context ID
+ mcr p15, 0, r5, c13, c0, 2 @ User r/w thread ID
+ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS VBAR
+ msr cpsr, r7 @ store cpsr
+
+ /*
+ * Enabling MMU here. Page entry needs to be altered
+ * to create temporary 1:1 map and then resore the entry
+ * ones MMU is enabled
+ */
+ mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
+ and r7, #0x7 @ Extract N (0:2) to decide
+ cmp r7, #0x0 @ TTBR0/TTBR1
+ beq use_ttbr0
+ttbr_error:
+ b ttbr_error @ Only N = 0 supported
+use_ttbr0:
+ mrc p15, 0, r2, c2, c0, 0 @ Read TTBR0
+ ldr r5, =TTRBIT_MASK
+ and r2, r5
+ mov r4, pc
+ ldr r5, =TABLE_INDEX_MASK
+ and r4, r5 @ r4 = 31 to 20 bits of pc
+ ldr r1, =TABLE_ENTRY
+ add r1, r1, r4 @ r1 has value of table entry
+ lsr r4, #18 @ Address of table entry
+ add r2, r4 @ r2 - location to be modified
+
+ /* Storing previous entry of location being modified */
+ ldr r4, [r2]
+ mov r9, r4
+ str r1, [r2]
+
+ /*
+ * Storing address of entry being modified
+ * It will be restored after enabling MMU
+ */
+ mov r10, r2
+
+ mov r1, #0
+ mcr p15, 0, r1, c7, c5, 4 @ Flush prefetch buffer
+ mcr p15, 0, r1, c7, c5, 6 @ Invalidate BTB
+ mcr p15, 0, r1, c8, c5, 0 @ Invalidate ITLB
+ mcr p15, 0, r1, c8, c6, 0 @ Invalidate DTLB
+
+ /*
+ * Restore control register but don't enable Data caches here.
+ * Caches will be enabled after restoring MMU table entry.
+ */
+ ldmea r0!, {r4}
+ mov r11, r4
+ ldr r2, =CACHE_DISABLE_MASK
+ and r4, r4, r2
+ mcr p15, 0, r4, c1, c0, 0
+ isb
+ dsb
+ ldr r1, =mmu_on_label
+ bx r1
+mmu_on_label:
+ mov r8, lr
+ /* Set up the per-CPU stacks */
+
+ /* protect r0 */
+ push {r0}
+ bl cpu_init
+ pop {r0}
+
+#ifdef CONFIG_CACHE_L2X0
+ ldr r4, =l2x0_base
+ ldr r2, [r4]
+
+ ldmea r0!, {r4-r7}
+ /* L2 will be enabled after L1 is enabled */
+ mov r4, #0x0
+ str r4, [r2, #L2X0_CTRL]
+ str r5, [r2, #L2X0_AUX_CTRL]
+ str r6, [r2, #L2X0_TAG_LATENCY_CTRL]
+ str r7, [r2, #L2X0_DATA_LATENCY_CTRL]
+
+ ldmea r0!, {r4-r5}
+ str r4, [r2, #L2X0_PREFETCH_CTRL]
+ str r5, [r2, #L2X0_POWER_CTRL]
+#endif
+ /*
+ * Restore the MMU table entry that was modified for
+ * enabling MMU.
+ */
+ ldr r4, =PAGE_OFFSET
+ ldr r5, =MX6Q_PHYS_OFFSET
+ sub r4, r4, r5
+ add r4, r4, r10
+ str r9, [r4]
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c1, 6 @ flush TLB and issue barriers
+ mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
+ mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
+ mcr p15, 0, r0, c8, c5, 0 @ Invalidate ITLB
+ mcr p15, 0, r0, c8, c6, 0 @ Invalidate DTLB
+ dsb
+ isb
+
+/******************************************************************
+invalidate l1 dcache, r0-r4, r6, r7 used
+******************************************************************/
+ mov r0, #0
+ mcr p15, 2, r0, c0, c0, 0
+ mrc p15, 1, r0, c0, c0, 0
+
+ ldr r1, =0x7fff
+ and r2, r1, r0, lsr #13
+
+ ldr r1, =0x3ff
+
+ and r3, r1, r0, lsr #3 @ NumWays - 1
+ add r2, r2, #1 @ NumSets
+
+ and r0, r0, #0x7
+ add r0, r0, #4 @ SetShift
+
+ clz r1, r3 @ WayShift
+ add r4, r3, #1 @ NumWays
+1:
+ sub r2, r2, #1 @ NumSets--
+ mov r3, r4 @ Temp = NumWays
+2:
+ subs r3, r3, #1 @ Temp--
+ mov r7, r3, lsl r1
+ mov r6, r2, lsl r0
+ orr r7, r7, r6
+ mcr p15, 0, r7, c7, c6, 2
+ bgt 2b
+ cmp r2, #0
+ bgt 1b
+ dsb
+ isb
+
+/************************************************************
+restore control register to enable cache
+************************************************************/
+ mov r0, r11
+ mcr p15, 0, r0, c1, c0, 0 @ with caches enabled.
+ dsb
+ isb
+
+#ifdef CONFIG_CACHE_L2X0
+ /* Enable L2 cache here */
+ ldr r4, =l2x0_base
+ ldr r2, [r4]
+ mov r4, #0x1
+ str r4, [r2, #L2X0_CTRL]
+#endif
+/***********************************************************
+return back to mx6_suspend_enter for dormant
+***********************************************************/
+ mov lr, r8
+ ldmfd sp!, {r0-r12}
+ mov pc, lr
+/************************************************
+return back to mx6_suspend_enter for suspend
+*************************************************/
+out:
+ ldmfd sp!, {r0-r12}
+ mov pc, lr
+
+ .type mx6q_do_suspend, #object
+ENTRY(mx6q_do_suspend)
+ .word mx6q_suspend
+ .size mx6q_suspend, . - mx6q_suspend
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b1e192ba8c2..9c92706eeec 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -28,7 +28,7 @@
#define CACHE_LINE_SIZE 32
-static void __iomem *l2x0_base;
+void __iomem *l2x0_base;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static uint32_t l2x0_size;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 1c920b2b881..c7cccdacf9b 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -110,6 +110,7 @@ config ARCH_MXC_AUDMUX_V2
config IRAM_ALLOC
bool
+ default y
select GENERIC_ALLOCATOR
config CLK_DEBUG
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 787c2688eb0..d32afc98667 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -11,6 +11,8 @@
#ifndef __ASM_ARCH_MXC_COMMON_H__
#define __ASM_ARCH_MXC_COMMON_H__
+#include <linux/suspend.h>
+
struct platform_device;
struct clk;
enum mxc_cpu_pwr_mode;
@@ -82,6 +84,7 @@ enum mxc_cpu_pwr_mode {
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
STOP_POWER_ON, /* just STOP */
STOP_POWER_OFF, /* STOP + SRPG */
+ ARM_POWER_OFF, /* STOP + SRPG + ARM power off */
};
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
@@ -121,12 +124,14 @@ extern void imx_smp_prepare(void);
static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
-extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_reset_ipu(int ipu);
+extern void imx_reset_vpu(void);
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
extern void imx_src_init(void);
extern void imx_gpc_init(void);
-extern void imx_gpc_pre_suspend(void);
-extern void imx_gpc_post_resume(void);
+extern bool imx_gpc_wake_irq_pending(void);
+extern void imx_gpc_pre_suspend(suspend_state_t state);
+extern void imx_gpc_post_resume(suspend_state_t state);
extern void imx51_babbage_common_init(void);
extern void imx53_ard_common_init(void);
extern void imx53_evk_common_init(void);
@@ -135,4 +140,8 @@ extern void imx53_smd_common_init(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_pm_init(void);
extern void imx6q_clock_map_io(void);
+extern void imx6q_ccm_pre_suspend(suspend_state_t state);
+extern void imx6q_ccm_gpu_pre_suspend(void);
+extern void imx6q_ccm_gpu_post_resume(void);
+extern void imx6q_ccm_post_resume(void);
#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 6e192c4a391..e0945a2b813 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -25,7 +25,7 @@
#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
#define UART_PADDR MX53_UART1_BASE_ADDR
#elif defined (CONFIG_DEBUG_IMX6Q_UART)
-#define UART_PADDR MX6Q_UART4_BASE_ADDR
+#define UART_PADDR MX6Q_UART2_BASE_ADDR
#endif
#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
new file mode 100644
index 00000000000..c0e228790ca
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -0,0 +1,7359 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __MACH_IOMUX_MX6Q_H__
+#define __MACH_IOMUX_MX6Q_H__
+
+#include <mach/iomux-v3.h>
+
+/*
+ * various IOMUX alternate output functions (1-7)
+ */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0,
+ IOMUX_CONFIG_ALT1,
+ IOMUX_CONFIG_ALT2,
+ IOMUX_CONFIG_ALT3,
+ IOMUX_CONFIG_ALT4,
+ IOMUX_CONFIG_ALT5,
+ IOMUX_CONFIG_ALT6,
+ IOMUX_CONFIG_ALT7,
+ IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
+ } iomux_pin_cfg_t;
+
+#define NON_MUX_I 0x3FF
+#define NON_PAD_I 0x7FF
+#define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_HIGH_DRV (PAD_CTL_DSE_120ohm)
+#define MX6Q_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define MX6Q_DISP_PAD_CLT MX6Q_HIGH_DRV
+#define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define MX6Q_ESAI_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
+#define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
+#define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1)
+
+#define MX6Q_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+#define MX6Q_USB_HSIC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_40ohm)
+
+#define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
+ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
+ IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
+ IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
+ IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
+ IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
+ IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
+ IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
+ IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
+ IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
+ IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
+ IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ IOMUX_PAD(0x036C, 0x0058, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
+ IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
+ IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
+ IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
+ IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
+ IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ IOMUX_PAD(0x0380, 0x006C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
+ IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ IOMUX_PAD(0x0388, 0x0074, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
+ IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
+ IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
+ IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
+ IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ IOMUX_PAD(0x0398, 0x0084, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
+ IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
+ IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
+ IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
+ IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
+#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
+ IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
+ IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
+ IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
+#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__I2C2_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
+
+#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
+ IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__I2C3_SCL \
+ IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
+ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
+ IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__I2C3_SDA \
+ IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
+ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
+ IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+#define _MX6Q_PAD_EIM_D19__UART1_CTS \
+ IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
+#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
+ IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
+ IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
+ IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_CTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_RTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
+ IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
+ IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__I2C1_SCL \
+ IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
+#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
+ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+
+#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
+ IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
+ IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART3_CTS \
+ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART1_DCD \
+ IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
+ IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_CTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_RTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+#define _MX6Q_PAD_EIM_EB3__UART1_RI \
+ IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_TXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_RXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART1_DTR \
+ IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_TXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_RXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART1_DSR \
+ IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_TXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_RXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
+ IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_TXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_RXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
+ IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__I2C1_SDA \
+ IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
+#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
+ IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_CTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_RTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
+ IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
+ IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_CTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_RTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__UART3_CTS \
+ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
+ IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_CTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_RTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
+ IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
+ IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
+ IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
+ IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
+ IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
+ IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
+ IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
+ IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
+ IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
+ IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
+ IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
+ IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
+ IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
+ IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
+ IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
+ IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
+ IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
+ IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
+ IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
+ IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
+ IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
+ IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
+ IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
+ IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
+ IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
+ IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
+ IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
+#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
+ IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
+ IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
+ IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
+ IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
+#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
+ IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
+ IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
+ IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
+ IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
+ IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
+#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
+ IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
+#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
+ IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
+ IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
+ IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
+ IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
+ IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
+ IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
+ IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
+ IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
+ IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
+ IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
+ IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
+ IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
+ IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
+ IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
+ IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
+ IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
+ IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
+ IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
+ IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
+ IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
+ IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
+#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
+ IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
+#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
+ IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
+#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
+ IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
+#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
+ IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
+ IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
+ IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
+ IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
+ IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
+ IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
+ IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
+ IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
+ IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
+ IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
+ IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
+ IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
+ IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
+ IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
+ IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
+ IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
+ IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
+ IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
+ IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
+ IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
+ IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
+ IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
+ IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
+ IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
+ IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
+ IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
+ IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
+ IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
+ IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
+ IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
+ IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
+ IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
+ IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
+ IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
+ IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
+ IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
+ IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
+ IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
+ IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
+ IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
+ IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
+ IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
+ IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
+ IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
+ IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
+ IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
+ IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
+ IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
+ IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
+ IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
+ IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
+ IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
+ IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
+ IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
+ IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
+ IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
+ IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
+ IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
+ IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
+ IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
+ IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
+ IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
+ IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
+ IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
+ IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
+ IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
+ IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
+ IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
+ IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
+ IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
+ IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
+ IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
+ IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
+ IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
+ IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
+ IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
+ IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
+ IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
+ IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
+ IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
+ IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
+ IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
+ IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
+ IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
+ IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
+ IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
+ IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
+ IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
+ IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
+ IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
+ IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
+ IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
+ IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
+ IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
+ IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
+ IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
+ IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
+ IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
+ IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
+ IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
+ IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
+ IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
+ IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
+ IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_MDC \
+ IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
+ IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
+ IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
+ IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
+ IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
+ IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_TXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_RXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
+ IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
+ IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
+ IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
+ IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
+ IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
+ IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_TXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_RXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
+ IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
+ IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
+ IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
+#define _MX6Q_PAD_KEY_ROW1__ENET_COL \
+ IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
+ IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
+ IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
+ IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
+ IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
+ IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
+#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
+ IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_MDC \
+ IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
+ IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
+ IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
+ IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
+ IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
+ IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
+ IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
+ IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
+ IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__ENET_CRS \
+ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
+ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
+ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
+ IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
+#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
+ IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
+ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
+ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
+ IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
+ IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
+ IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
+#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_CTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_RTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
+ IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
+ IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
+ IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
+ IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
+ IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
+ IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
+ IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_0__CCM_CLKO \
+ IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
+ IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
+ IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
+ IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
+#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
+ IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
+ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+#define MX6Q_PAD_GPIO_1__USBOTG_ID \
+ IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
+#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
+ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
+ IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__USDHC1_CD \
+ IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
+ IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
+ IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
+ IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
+ IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
+ IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
+ IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
+ IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__USDHC1_WP \
+ IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
+ IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
+ IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
+#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__I2C3_SCL \
+ IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
+#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
+ IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
+ IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
+#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
+ IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
+
+#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
+ IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
+#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__I2C3_SDA \
+ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
+#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
+ IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
+ IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
+ IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
+
+#define _MX6Q_PAD_GPIO_2__ESAI1_FST \
+ IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
+#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
+ IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
+#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
+ IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__USDHC2_WP \
+ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
+ IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
+
+#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
+ IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
+#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
+ IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
+#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
+ IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__USDHC2_CD \
+ IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
+#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
+ IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
+#define _MX6Q_PAD_GPIO_5__CCM_CLKO \
+ IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
+ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__I2C3_SCL \
+ IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
+#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
+ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
+#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
+ IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
+ IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
+ IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_TXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_RXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
+#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
+ IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
+ IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
+#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
+ IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
+ IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_TXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_RXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
+#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
+ IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
+ IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
+#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
+ IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
+ IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
+#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
+ IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__I2C3_SDA \
+ IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
+#define _MX6Q_PAD_GPIO_16__SJC_DE_B \
+ IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
+ IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
+#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
+ IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
+ IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
+ IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
+ IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
+ IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
+#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
+#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
+ IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
+#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
+#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
+ IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
+ IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
+ IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
+ IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__CCM_CLKO \
+ IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
+ IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
+ IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
+ IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
+ IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
+ IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
+ IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
+ IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
+ IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
+ IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
+ IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
+ IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
+ IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
+ IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
+ IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
+ IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
+ IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
+ IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
+ IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
+ IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
+ IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
+ IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
+ IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
+ IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
+ IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
+ IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
+ IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
+ IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
+ IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
+ IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
+ IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
+ IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
+ IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
+ IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
+ IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
+ IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
+ IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
+ IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
+ IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
+ IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
+ IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
+ IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
+ IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
+ IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
+ IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
+ IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
+ IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
+ IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
+ IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
+ IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
+ IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
+ IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
+ IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
+ IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
+ IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
+ IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
+ IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
+ IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
+ IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
+ IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
+ IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_POR_B__SRC_POR_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
+ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
+#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
+ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
+ IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
+#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
+ IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
+ IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
+#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
+ IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
+ IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
+#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
+ IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
+ IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__UART2_CTS \
+ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
+ IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
+ IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
+ IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_CTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_RTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
+ IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
+ IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
+ IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
+ IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
+ IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
+ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
+ IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
+ IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
+ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
+ IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
+ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
+ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
+ IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_RST__USDHC3_RST \
+ IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_CTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_RTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
+ IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
+ IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
+ IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
+ IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
+ IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
+ IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
+ IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
+ IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
+ IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
+ IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
+ IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
+ IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
+ IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
+ IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
+ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
+ IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
+ IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
+ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
+ IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
+ IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
+ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
+ IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
+ IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
+ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
+ IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
+ IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
+ IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
+ IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_TXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_RXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
+ IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
+ IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
+ IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
+ IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_TXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_RXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
+ IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
+ IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
+ IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
+ IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
+ IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
+ IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
+ IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
+ IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
+ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
+ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
+ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
+ IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
+ IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
+ IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
+ IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
+ IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
+ IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
+ IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
+ IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
+ IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
+ IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
+ IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
+ IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
+ IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
+ IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
+ IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
+ IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
+ IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
+ IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
+ IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
+ IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
+ IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
+ IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
+ IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
+ IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
+#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
+ IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
+ IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
+ IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
+#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
+ IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
+ IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
+ IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
+ IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
+ IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
+ IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
+ IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
+ IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
+ IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
+ IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
+ IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
+ IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
+ IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
+ IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
+ IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
+ IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
+ IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
+ IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
+#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
+ IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
+ IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
+ IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
+#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
+ IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
+ IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
+ IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
+#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
+#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
+ IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
+ IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
+
+
+
+#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
+ (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
+ (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
+ (_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
+ (_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__CCM_WAIT \
+ (_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
+ (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
+ (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
+ (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
+ (_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__CCM_STOP \
+ (_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
+ (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
+ (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
+ (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
+ (_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
+ (_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
+ (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
+ (_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
+ (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
+ (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
+ (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+
+#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START \
+ (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | \
+ MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)\
+ )
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
+ (_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__SJC_FAIL \
+ (_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
+ (_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
+ (_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START \
+ (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP))
+#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
+ (_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
+ (_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__ECSPI2_RDY \
+ (_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__GPIO_5_2 \
+ (_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
+ (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
+ (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
+ (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__GPIO_2_30 \
+ (_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__I2C2_SCL \
+ (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
+ (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
+ (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__GPIO_3_16 \
+ (_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__I2C2_SDA \
+ (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__ECSPI1_MISO \
+ (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
+ (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__GPIO_3_17 \
+ (_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__I2C3_SCL \
+ (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
+ (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
+ (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
+ (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__GPIO_3_18 \
+ (_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__I2C3_SDA \
+ (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
+ (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
+ (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
+ (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__UART1_CTS \
+ (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__GPIO_3_19 \
+ (_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__EPIT1_EPITO \
+ (_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
+ (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
+ (_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
+ (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__UART1_CTS \
+ (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__UART1_RTS \
+ (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__GPIO_3_20 \
+ (_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__EPIT2_EPITO \
+ (_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
+ (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
+ (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__GPIO_3_21 \
+ (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__I2C1_SCL \
+ (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__SPDIF_IN1 \
+ (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__ECSPI4_MISO \
+ (_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
+ (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__GPIO_3_22 \
+ (_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
+ (_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
+ (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__UART3_CTS \
+ (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__UART1_DCD \
+ (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
+ (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__GPIO_3_23 \
+ (_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
+ (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART3_CTS \
+ (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART3_RTS \
+ (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART1_RI \
+ (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
+ (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__GPIO_2_31 \
+ (_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART3_TXD \
+ (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART3_RXD \
+ (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
+ (_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__GPIO_3_24 \
+ (_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART1_DTR \
+ (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART3_TXD \
+ (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART3_RXD \
+ (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
+ (_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__GPIO_3_25 \
+ (_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART1_DSR \
+ (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
+ (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__UART2_TXD \
+ (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__UART2_RXD \
+ (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__GPIO_3_26 \
+ (_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
+ (_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
+ (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__UART2_TXD \
+ (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__UART2_RXD \
+ (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__GPIO_3_27 \
+ (_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
+ (_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__I2C1_SDA \
+ (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
+ (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
+ (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__UART2_CTS \
+ (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__UART2_RTS \
+ (_MX6Q_PAD_EIM_D28__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__GPIO_3_28 \
+ (_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
+ (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
+ (_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__UART2_CTS \
+ (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__UART2_RTS \
+ (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__GPIO_3_29 \
+ (_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
+ (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__UART3_CTS \
+ (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__GPIO_3_30 \
+ (_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
+ (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
+ (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__UART3_CTS \
+ (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__UART3_RTS \
+ (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__GPIO_3_31 \
+ (_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
+ (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
+ (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
+ (_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
+ (_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__GPIO_5_4 \
+ (_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
+ (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
+ (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
+ (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
+ (_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
+ (_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__GPIO_6_6 \
+ (_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
+ (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
+ (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
+ (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__GPIO_2_16 \
+ (_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
+ (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
+ (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
+ (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__GPIO_2_17 \
+ (_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
+ (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
+ (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
+ (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__GPIO_2_18 \
+ (_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
+ (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
+ (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
+ (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__GPIO_2_19 \
+ (_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
+ (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
+ (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
+ (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__GPIO_2_20 \
+ (_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
+ (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
+ (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
+ (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__RESERVED_RESERVED \
+ (_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__GPIO_2_21 \
+ (_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
+ (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
+ (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
+ (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__GPIO_2_22 \
+ (_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
+ (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
+ (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
+ (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__GPIO_2_23 \
+ (_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
+ (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__GPIO_2_24 \
+ (_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
+ (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__ECSPI2_MISO \
+ (_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__GPIO_2_25 \
+ (_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
+ (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
+ (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
+ (_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__GPIO_2_26 \
+ (_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
+ (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
+ (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
+ (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__GPIO_2_27 \
+ (_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
+ (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
+ (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__GPIO_2_28 \
+ (_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
+ (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__GPIO_2_29 \
+ (_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
+ (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__GPIO_3_0 \
+ (_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
+ (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__GPIO_3_1 \
+ (_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
+ (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__GPIO_3_2 \
+ (_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
+ (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__GPIO_3_3 \
+ (_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
+ (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__GPIO_3_4 \
+ (_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
+ (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__GPIO_3_5 \
+ (_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
+ (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__GPIO_3_6 \
+ (_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
+ (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__GPIO_3_7 \
+ (_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
+ (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__GPIO_3_8 \
+ (_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
+ (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__GPIO_3_9 \
+ (_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
+ (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__GPIO_3_10 \
+ (_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
+ (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__GPIO_3_11 \
+ (_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
+ (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__GPIO_3_12 \
+ (_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__GPIO_3_13 \
+ (_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__GPIO_3_14 \
+ (_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__GPIO_3_15 \
+ (_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
+ (_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
+ (_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
+ (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
+ (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
+ (_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
+ (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
+ (_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
+ (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
+ (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
+ (_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
+ (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
+ (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__USDHC1_WP \
+ (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
+ (_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
+ (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
+ (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
+ (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
+ (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
+ (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
+ (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
+ (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
+ (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
+ (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
+ (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
+ (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
+ (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
+ (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
+ (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
+ (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
+ (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
+ (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
+ (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
+ (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
+ (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
+ (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
+ (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
+ (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
+ (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
+ (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
+ (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
+ (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
+ (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
+ (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
+ (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
+ (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
+ (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
+ (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
+ (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
+ (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
+ (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
+ (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
+ (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
+ (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
+ (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
+ (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED \
+ (_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
+ (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
+ (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
+ (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
+ (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
+ (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
+ (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
+ (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
+ (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
+ (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
+ (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
+ (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
+ (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
+ (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
+ (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
+ (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
+ (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
+ (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
+ (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
+ (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
+ (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
+ (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
+ (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
+ (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
+ (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
+ (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
+ (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
+ (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
+ (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
+ (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
+ (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
+ (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
+ (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
+#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
+ (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
+ (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ENET_MDIO \
+ (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \
+ MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
+ (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
+ (_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
+ (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
+ (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
+ (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
+ (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
+ (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
+ (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
+ (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__PHY_TDI \
+ (_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
+ (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
+ (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
+ (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
+ (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
+ (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ESAI1_FST \
+ (_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
+ (_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__PHY_TCK \
+ (_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
+ (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
+ (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
+ (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
+ (_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__PHY_TMS \
+ (_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
+ (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
+ (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
+ (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
+ (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
+ (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
+ (_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
+ (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED \
+ (_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
+ (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
+ (_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
+ (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
+ (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ENET_MDC \
+ (_MX6Q_PAD_ENET_MDC__ENET_MDC | \
+ MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__GPIO_1_31 \
+ (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
+ (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
+ (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
+ (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__KPP_COL_0 \
+ (_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__UART4_TXD \
+ (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__UART4_RXD \
+ (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__GPIO_4_6 \
+ (_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
+ (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
+ (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
+ (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__UART4_TXD \
+ (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__UART4_RXD \
+ (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
+ (_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
+ (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
+ (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__ENET_MDIO \
+ (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__KPP_COL_1 \
+ (_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__UART5_TXD \
+ (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__UART5_RXD \
+ (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__GPIO_4_8 \
+ (_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
+ (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
+ (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
+ (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__ENET_COL \
+ (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
+ (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__UART5_TXD \
+ (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__UART5_RXD \
+ (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
+ (_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
+ (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
+ (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
+ (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
+ (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
+ (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__KPP_COL_2 \
+ (_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__ENET_MDC \
+ (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__GPIO_4_10 \
+ (_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
+ (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
+ (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
+ (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
+ (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
+ (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
+ (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
+ (_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
+ (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
+ (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__ENET_CRS \
+ (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
+ (_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__I2C2_SCL \
+ (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
+ (_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
+ (_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
+ (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
+ (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
+ (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
+ (_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
+ (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
+ (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
+ (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
+ (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__KPP_COL_4 \
+ (_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__UART5_CTS \
+ (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__UART5_RTS \
+ (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__GPIO_4_14 \
+ (_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
+ (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
+ (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
+ (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
+ (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__UART5_CTS \
+ (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
+ (_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
+ (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_0__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__KPP_COL_5 \
+ (_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__EPIT1_EPITO \
+ (_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__GPIO_1_0 \
+ (_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_1__ESAI1_SCKR \
+ (_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
+ (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__KPP_ROW_5 \
+ (_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__PWM2_PWMO \
+ (_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__GPIO_1_1 \
+ (_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__USDHC1_CD \
+ (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
+ (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_9__ESAI1_FSR \
+ (_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
+ (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__KPP_COL_6 \
+ (_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
+ (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__PWM1_PWMO \
+ (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_9__GPIO_1_9 \
+ (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_9__USDHC1_WP \
+ (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
+ (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_3__ESAI1_HCKR \
+ (_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__I2C3_SCL \
+ (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__CCM_CLKO2 \
+ (_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__GPIO_1_3 \
+ (_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
+ (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__MLB_MLBCLK \
+ (_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_6__ESAI1_SCKT \
+ (_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__I2C3_SDA \
+ (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__GPIO_1_6 \
+ (_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__USDHC2_LCTL \
+ (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__MLB_MLBSIG \
+ (_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_2__ESAI1_FST \
+ (_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__KPP_ROW_6 \
+ (_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__GPIO_1_2 \
+ (_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__USDHC2_WP \
+ (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__MLB_MLBDAT \
+ (_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_4__ESAI1_HCKT \
+ (_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__KPP_COL_7 \
+ (_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__GPIO_1_4 \
+ (_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__USDHC2_CD \
+ (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__KPP_ROW_7 \
+ (_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__GPIO_1_5 \
+ (_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__I2C3_SCL \
+ (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
+ (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__ECSPI5_RDY \
+ (_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__EPIT1_EPITO \
+ (_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__CAN1_TXCAN \
+ (_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__UART2_TXD \
+ (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__UART2_RXD \
+ (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__GPIO_1_7 \
+ (_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
+ (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__EPIT2_EPITO \
+ (_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__CAN1_RXCAN \
+ (_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__UART2_TXD \
+ (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__UART2_RXD \
+ (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__GPIO_1_8 \
+ (_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
+ (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__USDHC1_LCTL \
+ (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SPDIF_IN1 \
+ (_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__GPIO_7_11 \
+ (_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__I2C3_SDA \
+ (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SJC_DE_B \
+ (_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_17__ESAI1_TX0 \
+ (_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
+ (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
+ (_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(MX6Q_SPDIF_OUT_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__GPIO_7_12 \
+ (_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
+ (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_18__ESAI1_TX1 \
+ (_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__ENET_RX_CLK \
+ (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
+ (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__GPIO_7_13 \
+ (_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
+ (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_GPIO_19__KPP_COL_5 \
+ (_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
+ (_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__CCM_CLKO \
+ (_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__ECSPI1_RDY \
+ (_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__GPIO_4_5 \
+ (_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_19__ENET_TX_ER \
+ (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
+ (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
+ (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
+ (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
+ (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
+ (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
+ (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
+ (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
+ (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
+ (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
+ (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
+ (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
+ (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
+ (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
+ (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
+ (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
+ (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
+ (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
+ (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
+ (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
+ (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
+ (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
+ (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
+ (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
+ (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
+ (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
+ (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
+ (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
+ (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
+ (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
+ (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__UART1_TXD \
+ (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__UART1_RXD \
+ (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
+ (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
+ (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__UART1_TXD \
+ (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__UART1_RXD \
+ (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
+ (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
+ (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__UART4_TXD \
+ (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__UART4_RXD \
+ (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
+ (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
+ (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__UART4_TXD \
+ (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__UART4_RXD \
+ (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
+ (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
+ (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__UART5_TXD \
+ (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__UART5_RXD \
+ (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
+ (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
+ (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__UART5_TXD \
+ (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__UART5_RXD \
+ (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
+ (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
+ (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__UART4_CTS \
+ (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__UART4_RTS \
+ (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
+ (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
+ (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__UART4_CTS \
+ (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
+ (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
+ (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__UART5_CTS \
+ (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__UART5_RTS \
+ (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
+ (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
+ (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__UART5_CTS \
+ (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
+ (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TMS__SJC_TMS \
+ (_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_MOD__SJC_MOD \
+ (_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
+ (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TDI__SJC_TDI \
+ (_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TCK__SJC_TCK \
+ (_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_JTAG_TDO__SJC_TDO \
+ (_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_POR_B__SRC_POR_B \
+ (_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
+ (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ \
+ (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT7__UART1_TXD \
+ (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__UART1_RXD \
+ (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
+ (_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ \
+ (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT6__UART1_TXD \
+ (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__UART1_RXD \
+ (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
+ (_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ \
+ (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT5__UART2_TXD \
+ (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__UART2_RXD \
+ (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
+ (_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ \
+ (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT4__UART2_TXD \
+ (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__UART2_RXD \
+ (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
+ (_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ \
+ (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_CMD__UART2_CTS \
+ (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
+ (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__GPIO_7_2 \
+ (_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ \
+ (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_CLK__UART2_CTS \
+ (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__UART2_RTS \
+ (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
+ (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__GPIO_7_3 \
+ (_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ \
+ (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT0__UART1_CTS \
+ (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
+ (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
+ (_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ \
+ (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT1__UART1_CTS \
+ (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__UART1_RTS \
+ (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
+ (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
+ (_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ \
+ (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
+ (_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ \
+ (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD3_DAT3__UART3_CTS \
+ (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
+ (_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD3_RST__USDHC3_RST \
+ (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_CTS \
+ (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_RTS \
+ (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__GPIO_7_8 \
+ (_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
+ (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
+ (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
+ (_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
+ (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
+ (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_ALE__USDHC4_RST \
+ (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
+ (_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
+ (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
+ (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
+ (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
+ (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
+ (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0))
+#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
+ (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
+ (_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
+ (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
+ (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
+ (_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
+ (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
+ (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
+ (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
+ (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
+ (_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
+ (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
+ (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
+ (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
+ (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
+ (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
+ (_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
+ (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
+ (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
+ (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
+ (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
+ (_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
+ (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
+ (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ \
+ (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
+ (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_SD4_CMD__UART3_TXD \
+ (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__UART3_RXD \
+ (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__GPIO_7_9 \
+ (_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
+ (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ \
+ (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
+ (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_SD4_CLK__UART3_TXD \
+ (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__UART3_RXD \
+ (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__GPIO_7_10 \
+ (_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
+ (_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
+ (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__GPIO_2_0 \
+ (_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
+ (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
+ (_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
+ (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__GPIO_2_1 \
+ (_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
+ (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
+ (_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
+ (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__GPIO_2_2 \
+ (_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
+ (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
+ (_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
+ (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__GPIO_2_3 \
+ (_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
+ (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
+ (_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
+ (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__GPIO_2_4 \
+ (_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
+ (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
+ (_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
+ (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__GPIO_2_5 \
+ (_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
+ (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
+ (_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
+ (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__GPIO_2_6 \
+ (_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
+ (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
+ (_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
+#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
+ (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__GPIO_2_7 \
+ (_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
+ (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
+ (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ \
+ (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
+ (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
+ (_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
+ (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
+ (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ \
+ (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
+ (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
+ (_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
+ (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
+ (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ \
+ (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
+ (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
+ (_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
+ (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
+ (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ \
+ (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
+ (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
+ (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
+ (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ \
+ (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT4__UART2_TXD \
+ (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__UART2_RXD \
+ (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
+ (_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
+ (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
+ (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ \
+ (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT5__UART2_CTS \
+ (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__UART2_RTS \
+ (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
+ (_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
+ (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
+ (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ \
+ (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT6__UART2_CTS \
+ (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
+ (_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
+ (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
+ (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ \
+ (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+#define MX6Q_PAD_SD4_DAT7__UART2_TXD \
+ (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__UART2_RXD \
+ (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
+ (_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
+ (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
+ (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
+ (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
+ (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
+ (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
+ (_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
+ (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
+ (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
+ (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
+ (_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
+ (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
+ (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
+ (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
+ (_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_CMD__USDHC1_CMD \
+ (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
+ (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__PWM4_PWMO \
+ (_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
+ (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__GPIO_1_18 \
+ (_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
+ (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
+ (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
+ (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
+ (_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD1_CLK__USDHC1_CLK \
+ (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
+ (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
+ (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__GPT_CLKIN \
+ (_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__GPIO_1_20 \
+ (_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
+ (_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
+ (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_CLK__USDHC2_CLK \
+ (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
+ (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__KPP_COL_5 \
+ (_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__GPIO_1_10 \
+ (_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
+ (_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
+ (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_CMD__USDHC2_CMD \
+ (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
+ (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
+ (_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__GPIO_1_11 \
+ (_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
+ (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
+ (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
+ (_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
+ (_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__SJC_DONE \
+ (_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 2fa3b543010..181510c633f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -48,8 +48,8 @@
* PAD_CTRL_OFS: 12..23 (12)
* SEL_INPUT_OFS: 24..35 (12)
* MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
- * SEL_INP: 58..61 (4)
+ * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
+ * SEL_INP: 59..62 (4)
* reserved: 63 (1)
*/
@@ -65,8 +65,8 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_SHIFT 36
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 58
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
@@ -80,21 +80,50 @@ typedef u64 iomux_v3_cfg_t;
((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
-#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
/*
* Use to set PAD control
*/
+#define NO_PAD_CTRL (1 << 17)
+#ifdef CONFIG_SOC_IMX6Q
+#define PAD_CTL_HYS (1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
-#define NO_PAD_CTRL (1 << 16)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#else
#define PAD_CTL_DVS (1 << 13)
#define PAD_CTL_HYS (1 << 8)
#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUE (1 << 6)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4)
+#define PAD_CTL_PUS_47K_UP (1 << 4)
+#define PAD_CTL_PUS_100K_UP (2 << 4)
+#define PAD_CTL_PUS_22K_UP (3 << 4)
#define PAD_CTL_ODE (1 << 3)
@@ -105,7 +134,7 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
-
+#endif
#define IOMUX_CONFIG_SION (0x1 << 4)
#define MX51_NUM_GPIO_PORT 4
@@ -138,5 +167,9 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
*/
void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+/*
+ * Set bits for general purpose registers
+ */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value);
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h
index 0816ae9b4c4..bccb8811673 100644
--- a/arch/arm/plat-mxc/include/mach/ipu-v3.h
+++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h
@@ -125,6 +125,7 @@ typedef union {
struct {
uint32_t csi;
uint32_t mipi_id;
+ uint32_t mipi_vc;
bool mipi_en;
bool interlaced;
} csi_mem;
@@ -690,7 +691,7 @@ uint32_t bytes_per_pixel(uint32_t fmt);
struct ipuv3_fb_platform_data {
char disp_dev[32];
u32 interface_pix_fmt;
- char *mode_str;
+ char mode_str[32];
int default_bpp;
bool int_clk;
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
index f9adfeb5ef4..596c10d98fe 100644
--- a/arch/arm/plat-mxc/include/mach/mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -30,5 +30,17 @@
#define MX6Q_UART2_BASE_ADDR 0x021e8000
#define MX6Q_UART4_BASE_ADDR 0x021f0000
#define MX6Q_UART_SIZE 0x4000
+#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000
+#define MX6Q_IOMUXC_SIZE 0x4000
+
+#define MX6Q_IRAM_BASE_ADDR 0x00900000
+/* The last 4K is for cpu hotplug to workaround wdog issue*/
+#define MX6Q_IRAM_SIZE (SZ_256K - SZ_4K)
+
+#define MX6Q_VPU_BASE_ADDR 0x02040000
+#define MX6Q_IPU1_BASE_ADDR 0x02400000
+#define MX6Q_IPU2_BASE_ADDR 0x02800000
+
+#define MX6Q_SRC_BASE_ADDR 0x020d8000
#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index eb49d7114ca..a74b87db893 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -192,6 +192,7 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx53() (0)
#endif
+#define cpu_is_mx37() (0)
#define cpu_is_mx6q() (0)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h
new file mode 100644
index 00000000000..59688f657a2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxc_edid.h
+ *
+ * @brief MXC EDID tools
+ *
+ * @ingroup Framebuffer
+ */
+
+#ifndef MXC_EDID_H
+#define MXC_EDID_H
+
+#define FB_VMODE_ASPECT_4_3 0x10
+#define FB_VMODE_ASPECT_16_9 0x20
+
+struct mxc_edid_cfg {
+ bool cea_underscan;
+ bool cea_basicaudio;
+ bool cea_ycbcr444;
+ bool cea_ycbcr422;
+ bool hdmi_cap;
+
+ /*VSD*/
+ bool vsd_dc_48bit;
+ bool vsd_dc_36bit;
+ bool vsd_dc_30bit;
+ bool vsd_dc_y444;
+ bool vsd_dvi_dual;
+};
+
+int mxc_edid_var_to_vic(struct fb_var_screeninfo *var);
+int mxc_edid_mode_to_vic(const struct fb_videomode *mode);
+int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
+ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc_hdmi.h b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h
new file mode 100644
index 00000000000..a7f22de9b40
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_hdmi.h
@@ -0,0 +1,1028 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MXC_HDMI_H__
+#define __MXC_HDMI_H__
+
+/*
+ * Hdmi controller registers
+ */
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID 0x0000
+#define HDMI_REVISION_ID 0x0001
+#define HDMI_PRODUCT_ID0 0x0002
+#define HDMI_PRODUCT_ID1 0x0003
+#define HDMI_CONFIG0_ID 0x0004
+#define HDMI_CONFIG1_ID 0x0005
+#define HDMI_CONFIG2_ID 0x0006
+#define HDMI_CONFIG3_ID 0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0 0x0100
+#define HDMI_IH_FC_STAT1 0x0101
+#define HDMI_IH_FC_STAT2 0x0102
+#define HDMI_IH_AS_STAT0 0x0103
+#define HDMI_IH_PHY_STAT0 0x0104
+#define HDMI_IH_I2CM_STAT0 0x0105
+#define HDMI_IH_CEC_STAT0 0x0106
+#define HDMI_IH_VP_STAT0 0x0107
+#define HDMI_IH_I2CMPHY_STAT0 0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0 0x0180
+#define HDMI_IH_MUTE_FC_STAT1 0x0181
+#define HDMI_IH_MUTE_FC_STAT2 0x0182
+#define HDMI_IH_MUTE_AS_STAT0 0x0183
+#define HDMI_IH_MUTE_PHY_STAT0 0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0 0x0186
+#define HDMI_IH_MUTE_VP_STAT0 0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
+#define HDMI_IH_MUTE 0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0 0x0200
+#define HDMI_TX_INSTUFFING 0x0201
+#define HDMI_TX_GYDATA0 0x0202
+#define HDMI_TX_GYDATA1 0x0203
+#define HDMI_TX_RCRDATA0 0x0204
+#define HDMI_TX_RCRDATA1 0x0205
+#define HDMI_TX_BCBDATA0 0x0206
+#define HDMI_TX_BCBDATA1 0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS 0x0800
+#define HDMI_VP_PR_CD 0x0801
+#define HDMI_VP_STUFF 0x0802
+#define HDMI_VP_REMAP 0x0803
+#define HDMI_VP_CONF 0x0804
+#define HDMI_VP_STAT 0x0805
+#define HDMI_VP_INT 0x0806
+#define HDMI_VP_MASK 0x0807
+#define HDMI_VP_POL 0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF 0x1000
+#define HDMI_FC_INHACTV0 0x1001
+#define HDMI_FC_INHACTV1 0x1002
+#define HDMI_FC_INHBLANK0 0x1003
+#define HDMI_FC_INHBLANK1 0x1004
+#define HDMI_FC_INVACTV0 0x1005
+#define HDMI_FC_INVACTV1 0x1006
+#define HDMI_FC_INVBLANK 0x1007
+#define HDMI_FC_HSYNCINDELAY0 0x1008
+#define HDMI_FC_HSYNCINDELAY1 0x1009
+#define HDMI_FC_HSYNCINWIDTH0 0x100A
+#define HDMI_FC_HSYNCINWIDTH1 0x100B
+#define HDMI_FC_VSYNCINDELAY 0x100C
+#define HDMI_FC_VSYNCINWIDTH 0x100D
+#define HDMI_FC_INFREQ0 0x100E
+#define HDMI_FC_INFREQ1 0x100F
+#define HDMI_FC_INFREQ2 0x1010
+#define HDMI_FC_CTRLDUR 0x1011
+#define HDMI_FC_EXCTRLDUR 0x1012
+#define HDMI_FC_EXCTRLSPAC 0x1013
+#define HDMI_FC_CH0PREAM 0x1014
+#define HDMI_FC_CH1PREAM 0x1015
+#define HDMI_FC_CH2PREAM 0x1016
+#define HDMI_FC_AVICONF3 0x1017
+#define HDMI_FC_GCP 0x1018
+#define HDMI_FC_AVICONF0 0x1019
+#define HDMI_FC_AVICONF1 0x101A
+#define HDMI_FC_AVICONF2 0x101B
+#define HDMI_FC_AVIVID 0x101C
+#define HDMI_FC_AVIETB0 0x101D
+#define HDMI_FC_AVIETB1 0x101E
+#define HDMI_FC_AVISBB0 0x101F
+#define HDMI_FC_AVISBB1 0x1020
+#define HDMI_FC_AVIELB0 0x1021
+#define HDMI_FC_AVIELB1 0x1022
+#define HDMI_FC_AVISRB0 0x1023
+#define HDMI_FC_AVISRB1 0x1024
+#define HDMI_FC_AUDICONF0 0x1025
+#define HDMI_FC_AUDICONF1 0x1026
+#define HDMI_FC_AUDICONF2 0x1027
+#define HDMI_FC_AUDICONF3 0x1028
+#define HDMI_FC_VSDIEEEID0 0x1029
+#define HDMI_FC_VSDSIZE 0x102A
+#define HDMI_FC_VSDIEEEID1 0x1030
+#define HDMI_FC_VSDIEEEID2 0x1031
+#define HDMI_FC_VSDPAYLOAD0 0x1032
+#define HDMI_FC_VSDPAYLOAD1 0x1033
+#define HDMI_FC_VSDPAYLOAD2 0x1034
+#define HDMI_FC_VSDPAYLOAD3 0x1035
+#define HDMI_FC_VSDPAYLOAD4 0x1036
+#define HDMI_FC_VSDPAYLOAD5 0x1037
+#define HDMI_FC_VSDPAYLOAD6 0x1038
+#define HDMI_FC_VSDPAYLOAD7 0x1039
+#define HDMI_FC_VSDPAYLOAD8 0x103A
+#define HDMI_FC_VSDPAYLOAD9 0x103B
+#define HDMI_FC_VSDPAYLOAD10 0x103C
+#define HDMI_FC_VSDPAYLOAD11 0x103D
+#define HDMI_FC_VSDPAYLOAD12 0x103E
+#define HDMI_FC_VSDPAYLOAD13 0x103F
+#define HDMI_FC_VSDPAYLOAD14 0x1040
+#define HDMI_FC_VSDPAYLOAD15 0x1041
+#define HDMI_FC_VSDPAYLOAD16 0x1042
+#define HDMI_FC_VSDPAYLOAD17 0x1043
+#define HDMI_FC_VSDPAYLOAD18 0x1044
+#define HDMI_FC_VSDPAYLOAD19 0x1045
+#define HDMI_FC_VSDPAYLOAD20 0x1046
+#define HDMI_FC_VSDPAYLOAD21 0x1047
+#define HDMI_FC_VSDPAYLOAD22 0x1048
+#define HDMI_FC_VSDPAYLOAD23 0x1049
+#define HDMI_FC_SPDVENDORNAME0 0x104A
+#define HDMI_FC_SPDVENDORNAME1 0x104B
+#define HDMI_FC_SPDVENDORNAME2 0x104C
+#define HDMI_FC_SPDVENDORNAME3 0x104D
+#define HDMI_FC_SPDVENDORNAME4 0x104E
+#define HDMI_FC_SPDVENDORNAME5 0x104F
+#define HDMI_FC_SPDVENDORNAME6 0x1050
+#define HDMI_FC_SPDVENDORNAME7 0x1051
+#define HDMI_FC_SDPPRODUCTNAME0 0x1052
+#define HDMI_FC_SDPPRODUCTNAME1 0x1053
+#define HDMI_FC_SDPPRODUCTNAME2 0x1054
+#define HDMI_FC_SDPPRODUCTNAME3 0x1055
+#define HDMI_FC_SDPPRODUCTNAME4 0x1056
+#define HDMI_FC_SDPPRODUCTNAME5 0x1057
+#define HDMI_FC_SDPPRODUCTNAME6 0x1058
+#define HDMI_FC_SDPPRODUCTNAME7 0x1059
+#define HDMI_FC_SDPPRODUCTNAME8 0x105A
+#define HDMI_FC_SDPPRODUCTNAME9 0x105B
+#define HDMI_FC_SDPPRODUCTNAME10 0x105C
+#define HDMI_FC_SDPPRODUCTNAME11 0x105D
+#define HDMI_FC_SDPPRODUCTNAME12 0x105E
+#define HDMI_FC_SDPPRODUCTNAME13 0x105F
+#define HDMI_FC_SDPPRODUCTNAME14 0x1060
+#define HDMI_FC_SPDPRODUCTNAME15 0x1061
+#define HDMI_FC_SPDDEVICEINF 0x1062
+#define HDMI_FC_AUDSCONF 0x1063
+#define HDMI_FC_AUDSSTAT 0x1064
+#define HDMI_FC_DATACH0FILL 0x1070
+#define HDMI_FC_DATACH1FILL 0x1071
+#define HDMI_FC_DATACH2FILL 0x1072
+#define HDMI_FC_CTRLQHIGH 0x1073
+#define HDMI_FC_CTRLQLOW 0x1074
+#define HDMI_FC_ACP0 0x1075
+#define HDMI_FC_ACP28 0x1076
+#define HDMI_FC_ACP27 0x1077
+#define HDMI_FC_ACP26 0x1078
+#define HDMI_FC_ACP25 0x1079
+#define HDMI_FC_ACP24 0x107A
+#define HDMI_FC_ACP23 0x107B
+#define HDMI_FC_ACP22 0x107C
+#define HDMI_FC_ACP21 0x107D
+#define HDMI_FC_ACP20 0x107E
+#define HDMI_FC_ACP19 0x107F
+#define HDMI_FC_ACP18 0x1080
+#define HDMI_FC_ACP17 0x1081
+#define HDMI_FC_ACP16 0x1082
+#define HDMI_FC_ACP15 0x1083
+#define HDMI_FC_ACP14 0x1084
+#define HDMI_FC_ACP13 0x1085
+#define HDMI_FC_ACP12 0x1086
+#define HDMI_FC_ACP11 0x1087
+#define HDMI_FC_ACP10 0x1088
+#define HDMI_FC_ACP9 0x1089
+#define HDMI_FC_ACP8 0x108A
+#define HDMI_FC_ACP7 0x108B
+#define HDMI_FC_ACP6 0x108C
+#define HDMI_FC_ACP5 0x108D
+#define HDMI_FC_ACP4 0x108E
+#define HDMI_FC_ACP3 0x108F
+#define HDMI_FC_ACP2 0x1090
+#define HDMI_FC_ACP1 0x1091
+#define HDMI_FC_ISCR1_0 0x1092
+#define HDMI_FC_ISCR1_16 0x1093
+#define HDMI_FC_ISCR1_15 0x1094
+#define HDMI_FC_ISCR1_14 0x1095
+#define HDMI_FC_ISCR1_13 0x1096
+#define HDMI_FC_ISCR1_12 0x1097
+#define HDMI_FC_ISCR1_11 0x1098
+#define HDMI_FC_ISCR1_10 0x1099
+#define HDMI_FC_ISCR1_9 0x109A
+#define HDMI_FC_ISCR1_8 0x109B
+#define HDMI_FC_ISCR1_7 0x109C
+#define HDMI_FC_ISCR1_6 0x109D
+#define HDMI_FC_ISCR1_5 0x109E
+#define HDMI_FC_ISCR1_4 0x109F
+#define HDMI_FC_ISCR1_3 0x10A0
+#define HDMI_FC_ISCR1_2 0x10A1
+#define HDMI_FC_ISCR1_1 0x10A2
+#define HDMI_FC_ISCR2_15 0x10A3
+#define HDMI_FC_ISCR2_14 0x10A4
+#define HDMI_FC_ISCR2_13 0x10A5
+#define HDMI_FC_ISCR2_12 0x10A6
+#define HDMI_FC_ISCR2_11 0x10A7
+#define HDMI_FC_ISCR2_10 0x10A8
+#define HDMI_FC_ISCR2_9 0x10A9
+#define HDMI_FC_ISCR2_8 0x10AA
+#define HDMI_FC_ISCR2_7 0x10AB
+#define HDMI_FC_ISCR2_6 0x10AC
+#define HDMI_FC_ISCR2_5 0x10AD
+#define HDMI_FC_ISCR2_4 0x10AE
+#define HDMI_FC_ISCR2_3 0x10AF
+#define HDMI_FC_ISCR2_2 0x10B0
+#define HDMI_FC_ISCR2_1 0x10B1
+#define HDMI_FC_ISCR2_0 0x10B2
+#define HDMI_FC_DATAUTO0 0x10B3
+#define HDMI_FC_DATAUTO1 0x10B4
+#define HDMI_FC_DATAUTO2 0x10B5
+#define HDMI_FC_DATMAN 0x10B6
+#define HDMI_FC_DATAUTO3 0x10B7
+#define HDMI_FC_RDRB0 0x10B8
+#define HDMI_FC_RDRB1 0x10B9
+#define HDMI_FC_RDRB2 0x10BA
+#define HDMI_FC_RDRB3 0x10BB
+#define HDMI_FC_RDRB4 0x10BC
+#define HDMI_FC_RDRB5 0x10BD
+#define HDMI_FC_RDRB6 0x10BE
+#define HDMI_FC_RDRB7 0x10BF
+#define HDMI_FC_STAT0 0x10D0
+#define HDMI_FC_INT0 0x10D1
+#define HDMI_FC_MASK0 0x10D2
+#define HDMI_FC_POL0 0x10D3
+#define HDMI_FC_STAT1 0x10D4
+#define HDMI_FC_INT1 0x10D5
+#define HDMI_FC_MASK1 0x10D6
+#define HDMI_FC_POL1 0x10D7
+#define HDMI_FC_STAT2 0x10D8
+#define HDMI_FC_INT2 0x10D9
+#define HDMI_FC_MASK2 0x10DA
+#define HDMI_FC_POL2 0x10DB
+#define HDMI_FC_PRCONF 0x10E0
+
+#define HDMI_FC_GMD_STAT 0x1100
+#define HDMI_FC_GMD_EN 0x1101
+#define HDMI_FC_GMD_UP 0x1102
+#define HDMI_FC_GMD_CONF 0x1103
+#define HDMI_FC_GMD_HB 0x1104
+#define HDMI_FC_GMD_PB0 0x1105
+#define HDMI_FC_GMD_PB1 0x1106
+#define HDMI_FC_GMD_PB2 0x1107
+#define HDMI_FC_GMD_PB3 0x1108
+#define HDMI_FC_GMD_PB4 0x1109
+#define HDMI_FC_GMD_PB5 0x110A
+#define HDMI_FC_GMD_PB6 0x110B
+#define HDMI_FC_GMD_PB7 0x110C
+#define HDMI_FC_GMD_PB8 0x110D
+#define HDMI_FC_GMD_PB9 0x110E
+#define HDMI_FC_GMD_PB10 0x110F
+#define HDMI_FC_GMD_PB11 0x1110
+#define HDMI_FC_GMD_PB12 0x1111
+#define HDMI_FC_GMD_PB13 0x1112
+#define HDMI_FC_GMD_PB14 0x1113
+#define HDMI_FC_GMD_PB15 0x1114
+#define HDMI_FC_GMD_PB16 0x1115
+#define HDMI_FC_GMD_PB17 0x1116
+#define HDMI_FC_GMD_PB18 0x1117
+#define HDMI_FC_GMD_PB19 0x1118
+#define HDMI_FC_GMD_PB20 0x1119
+#define HDMI_FC_GMD_PB21 0x111A
+#define HDMI_FC_GMD_PB22 0x111B
+#define HDMI_FC_GMD_PB23 0x111C
+#define HDMI_FC_GMD_PB24 0x111D
+#define HDMI_FC_GMD_PB25 0x111E
+#define HDMI_FC_GMD_PB26 0x111F
+#define HDMI_FC_GMD_PB27 0x1120
+
+#define HDMI_FC_DBGFORCE 0x1200
+#define HDMI_FC_DBGAUD0CH0 0x1201
+#define HDMI_FC_DBGAUD1CH0 0x1202
+#define HDMI_FC_DBGAUD2CH0 0x1203
+#define HDMI_FC_DBGAUD0CH1 0x1204
+#define HDMI_FC_DBGAUD1CH1 0x1205
+#define HDMI_FC_DBGAUD2CH1 0x1206
+#define HDMI_FC_DBGAUD0CH2 0x1207
+#define HDMI_FC_DBGAUD1CH2 0x1208
+#define HDMI_FC_DBGAUD2CH2 0x1209
+#define HDMI_FC_DBGAUD0CH3 0x120A
+#define HDMI_FC_DBGAUD1CH3 0x120B
+#define HDMI_FC_DBGAUD2CH3 0x120C
+#define HDMI_FC_DBGAUD0CH4 0x120D
+#define HDMI_FC_DBGAUD1CH4 0x120E
+#define HDMI_FC_DBGAUD2CH4 0x120F
+#define HDMI_FC_DBGAUD0CH5 0x1210
+#define HDMI_FC_DBGAUD1CH5 0x1211
+#define HDMI_FC_DBGAUD2CH5 0x1212
+#define HDMI_FC_DBGAUD0CH6 0x1213
+#define HDMI_FC_DBGAUD1CH6 0x1214
+#define HDMI_FC_DBGAUD2CH6 0x1215
+#define HDMI_FC_DBGAUD0CH7 0x1216
+#define HDMI_FC_DBGAUD1CH7 0x1217
+#define HDMI_FC_DBGAUD2CH7 0x1218
+#define HDMI_FC_DBGTMDS0 0x1219
+#define HDMI_FC_DBGTMDS1 0x121A
+#define HDMI_FC_DBGTMDS2 0x121B
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0 0x3000
+#define HDMI_PHY_TST0 0x3001
+#define HDMI_PHY_TST1 0x3002
+#define HDMI_PHY_TST2 0x3003
+#define HDMI_PHY_STAT0 0x3004
+#define HDMI_PHY_INT0 0x3005
+#define HDMI_PHY_MASK0 0x3006
+#define HDMI_PHY_POL0 0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
+#define HDMI_PHY_I2CM_INT_ADDR 0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0 0x3100
+#define HDMI_AUD_CONF1 0x3101
+#define HDMI_AUD_INT 0x3102
+#define HDMI_AUD_CONF2 0x3103
+#define HDMI_AUD_N1 0x3200
+#define HDMI_AUD_N2 0x3201
+#define HDMI_AUD_N3 0x3202
+#define HDMI_AUD_CTS1 0x3203
+#define HDMI_AUD_CTS2 0x3204
+#define HDMI_AUD_CTS3 0x3205
+#define HDMI_AUD_INPUTCLKFS 0x3206
+#define HDMI_AUD_CONF0_HBR 0x3400
+#define HDMI_AUD_HBR_STATUS 0x3401
+#define HDMI_AUD_HBR_INT 0x3402
+#define HDMI_AUD_HBR_POL 0x3403
+#define HDMI_AUD_HBR_MASK 0x3404
+
+/* Generic Parallel Audio Interface Registers */
+/* Not used as GPAUD interface is not enabled in hw */
+#define HDMI_GP_CONF0 0x3500
+#define HDMI_GP_CONF1 0x3501
+#define HDMI_GP_CONF2 0x3502
+#define HDMI_GP_STAT 0x3503
+#define HDMI_GP_INT 0x3504
+#define HDMI_GP_MASK 0x3505
+#define HDMI_GP_POL 0x3506
+
+/* Audio DMA Registers */
+#define HDMI_AHB_DMA_CONF0 0x3600
+#define HDMI_AHB_DMA_START 0x3601
+#define HDMI_AHB_DMA_STOP 0x3602
+#define HDMI_AHB_DMA_THRSLD 0x3603
+#define HDMI_AHB_DMA_STRADDR0 0x3604
+#define HDMI_AHB_DMA_STRADDR1 0x3605
+#define HDMI_AHB_DMA_STRADDR2 0x3606
+#define HDMI_AHB_DMA_STRADDR3 0x3607
+#define HDMI_AHB_DMA_STPADDR0 0x3608
+#define HDMI_AHB_DMA_STPADDR1 0x3609
+#define HDMI_AHB_DMA_STPADDR2 0x360a
+#define HDMI_AHB_DMA_STPADDR3 0x360b
+#define HDMI_AHB_DMA_BSTADDR0 0x360c
+#define HDMI_AHB_DMA_BSTADDR1 0x360d
+#define HDMI_AHB_DMA_BSTADDR2 0x360e
+#define HDMI_AHB_DMA_BSTADDR3 0x360f
+#define HDMI_AHB_DMA_MBLENGTH0 0x3610
+#define HDMI_AHB_DMA_MBLENGTH1 0x3611
+#define HDMI_AHB_DMA_STAT 0x3612
+#define HDMI_AHB_DMA_INT 0x3613
+#define HDMI_AHB_DMA_MASK 0x3614
+#define HDMI_AHB_DMA_POL 0x3615
+#define HDMI_AHB_DMA_CONF1 0x3616
+#define HDMI_AHB_DMA_BUFFSTAT 0x3617
+#define HDMI_AHB_DMA_BUFFINT 0x3618
+#define HDMI_AHB_DMA_BUFFMASK 0x3619
+#define HDMI_AHB_DMA_BUFFPOL 0x361a
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV 0x4000
+#define HDMI_MC_CLKDIS 0x4001
+#define HDMI_MC_SWRSTZ 0x4002
+#define HDMI_MC_OPCTRL 0x4003
+#define HDMI_MC_FLOWCTRL 0x4004
+#define HDMI_MC_PHYRSTZ 0x4005
+#define HDMI_MC_LOCKONCLOCK 0x4006
+#define HDMI_MC_HEACPHY_RST 0x4007
+
+/* Color Space Converter Registers */
+#define HDMI_CSC_CFG 0x4100
+#define HDMI_CSC_SCALE 0x4101
+#define HDMI_CSC_COEF_A1_MSB 0x4102
+#define HDMI_CSC_COEF_A1_LSB 0x4103
+#define HDMI_CSC_COEF_A2_MSB 0x4104
+#define HDMI_CSC_COEF_A2_LSB 0x4105
+#define HDMI_CSC_COEF_A3_MSB 0x4106
+#define HDMI_CSC_COEF_A3_LSB 0x4107
+#define HDMI_CSC_COEF_A4_MSB 0x4108
+#define HDMI_CSC_COEF_A4_LSB 0x4109
+#define HDMI_CSC_COEF_B1_MSB 0x410A
+#define HDMI_CSC_COEF_B1_LSB 0x410B
+#define HDMI_CSC_COEF_B2_MSB 0x410C
+#define HDMI_CSC_COEF_B2_LSB 0x410D
+#define HDMI_CSC_COEF_B3_MSB 0x410E
+#define HDMI_CSC_COEF_B3_LSB 0x410F
+#define HDMI_CSC_COEF_B4_MSB 0x4110
+#define HDMI_CSC_COEF_B4_LSB 0x4111
+#define HDMI_CSC_COEF_C1_MSB 0x4112
+#define HDMI_CSC_COEF_C1_LSB 0x4113
+#define HDMI_CSC_COEF_C2_MSB 0x4114
+#define HDMI_CSC_COEF_C2_LSB 0x4115
+#define HDMI_CSC_COEF_C3_MSB 0x4116
+#define HDMI_CSC_COEF_C3_LSB 0x4117
+#define HDMI_CSC_COEF_C4_MSB 0x4118
+#define HDMI_CSC_COEF_C4_LSB 0x4119
+
+/* HDCP Encryption Engine Registers */
+#define HDMI_A_HDCPCFG0 0x5000
+#define HDMI_A_HDCPCFG1 0x5001
+#define HDMI_A_HDCPOBS0 0x5002
+#define HDMI_A_HDCPOBS1 0x5003
+#define HDMI_A_HDCPOBS2 0x5004
+#define HDMI_A_HDCPOBS3 0x5005
+#define HDMI_A_APIINTCLR 0x5006
+#define HDMI_A_APIINTSTAT 0x5007
+#define HDMI_A_APIINTMSK 0x5008
+#define HDMI_A_VIDPOLCFG 0x5009
+#define HDMI_A_OESSWCFG 0x500A
+#define HDMI_A_TIMER1SETUP0 0x500B
+#define HDMI_A_TIMER1SETUP1 0x500C
+#define HDMI_A_TIMER2SETUP0 0x500D
+#define HDMI_A_TIMER2SETUP1 0x500E
+#define HDMI_A_100MSCFG 0x500F
+#define HDMI_A_2SCFG0 0x5010
+#define HDMI_A_2SCFG1 0x5011
+#define HDMI_A_5SCFG0 0x5012
+#define HDMI_A_5SCFG1 0x5013
+#define HDMI_A_SRMVERLSB 0x5014
+#define HDMI_A_SRMVERMSB 0x5015
+#define HDMI_A_SRMCTRL 0x5016
+#define HDMI_A_SFRSETUP 0x5017
+#define HDMI_A_I2CHSETUP 0x5018
+#define HDMI_A_INTSETUP 0x5019
+#define HDMI_A_PRESETUP 0x501A
+#define HDMI_A_SRM_BASE 0x5020
+
+/* CEC Engine Registers */
+#define HDMI_CEC_CTRL 0x7D00
+#define HDMI_CEC_STAT 0x7D01
+#define HDMI_CEC_MASK 0x7D02
+#define HDMI_CEC_POLARITY 0x7D03
+#define HDMI_CEC_INT 0x7D04
+#define HDMI_CEC_ADDR_L 0x7D05
+#define HDMI_CEC_ADDR_H 0x7D06
+#define HDMI_CEC_TX_CNT 0x7D07
+#define HDMI_CEC_RX_CNT 0x7D08
+#define HDMI_CEC_TX_DATA0 0x7D10
+#define HDMI_CEC_TX_DATA1 0x7D11
+#define HDMI_CEC_TX_DATA2 0x7D12
+#define HDMI_CEC_TX_DATA3 0x7D13
+#define HDMI_CEC_TX_DATA4 0x7D14
+#define HDMI_CEC_TX_DATA5 0x7D15
+#define HDMI_CEC_TX_DATA6 0x7D16
+#define HDMI_CEC_TX_DATA7 0x7D17
+#define HDMI_CEC_TX_DATA8 0x7D18
+#define HDMI_CEC_TX_DATA9 0x7D19
+#define HDMI_CEC_TX_DATA10 0x7D1a
+#define HDMI_CEC_TX_DATA11 0x7D1b
+#define HDMI_CEC_TX_DATA12 0x7D1c
+#define HDMI_CEC_TX_DATA13 0x7D1d
+#define HDMI_CEC_TX_DATA14 0x7D1e
+#define HDMI_CEC_TX_DATA15 0x7D1f
+#define HDMI_CEC_RX_DATA0 0x7D20
+#define HDMI_CEC_RX_DATA1 0x7D21
+#define HDMI_CEC_RX_DATA2 0x7D22
+#define HDMI_CEC_RX_DATA3 0x7D23
+#define HDMI_CEC_RX_DATA4 0x7D24
+#define HDMI_CEC_RX_DATA5 0x7D25
+#define HDMI_CEC_RX_DATA6 0x7D26
+#define HDMI_CEC_RX_DATA7 0x7D27
+#define HDMI_CEC_RX_DATA8 0x7D28
+#define HDMI_CEC_RX_DATA9 0x7D29
+#define HDMI_CEC_RX_DATA10 0x7D2a
+#define HDMI_CEC_RX_DATA11 0x7D2b
+#define HDMI_CEC_RX_DATA12 0x7D2c
+#define HDMI_CEC_RX_DATA13 0x7D2d
+#define HDMI_CEC_RX_DATA14 0x7D2e
+#define HDMI_CEC_RX_DATA15 0x7D2f
+#define HDMI_CEC_LOCK 0x7D30
+#define HDMI_CEC_WKUPCTRL 0x7D31
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE 0x7E00
+#define HDMI_I2CMESS 0x7E01
+#define HDMI_I2CM_DATAO 0x7E02
+#define HDMI_I2CM_DATAI 0x7E03
+#define HDMI_I2CM_OPERATION 0x7E04
+#define HDMI_I2CM_INT 0x7E05
+#define HDMI_I2CM_CTLINT 0x7E06
+#define HDMI_I2CM_DIV 0x7E07
+#define HDMI_I2CM_SEGADDR 0x7E08
+#define HDMI_I2CM_SOFTRSTZ 0x7E09
+#define HDMI_I2CM_SEGPTR 0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
+
+/* Random Number Generator Registers (RNG) */
+#define HDMI_RNG_BASE 0x8000
+
+
+/*
+ * Register field definitions
+ */
+enum {
+/* IH_PHY_STAT0 field values */
+ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
+ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
+ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
+ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
+ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
+ HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+/* IH_MUTE_I2CMPHY_STAT0 field values */
+ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
+ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
+
+/* IH_AHBDMAAUD_STAT0 field values */
+ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
+ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
+ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
+ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
+ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE_AHBDMAAUD_STAT0 field values */
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE field values */
+ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+/* TX_INVID0 field values */
+ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
+ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
+ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
+ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+/* TX_INSTUFFING field values */
+ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
+ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
+ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
+ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
+ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
+ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
+
+/* VP_PR_CD field values */
+ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
+ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
+ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+/* VP_STUFF field values */
+ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
+ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
+ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
+ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
+ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
+ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
+ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
+
+/* VP_CONF field values */
+ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
+ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
+ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+ HDMI_VP_CONF_PR_EN_MASK = 0x10,
+ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
+ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
+ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
+ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
+ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
+
+/* VP_REMAP field values */
+ HDMI_VP_REMAP_MASK = 0x3,
+ HDMI_VP_REMAP_YCC422_24bit = 0x2,
+ HDMI_VP_REMAP_YCC422_20bit = 0x1,
+ HDMI_VP_REMAP_YCC422_16bit = 0x0,
+
+/* FC_INVIDCONF field values */
+ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+/* FC_AUDICONF0 field values */
+ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
+ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
+ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
+ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
+
+/* FC_AUDICONF1 field values */
+ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
+ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
+ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
+ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
+
+/* FC_AUDICONF3 field values */
+ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
+ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
+ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
+ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
+ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
+ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
+
+/* FC_AUDSCHNLS0 field values */
+ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
+ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
+ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
+
+/* FC_AUDSCHNLS3-6 field values */
+ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
+ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
+ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
+ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
+ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
+ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
+
+ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
+ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
+ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
+ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
+ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
+ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
+
+/* HDMI_FC_AUDSCHNLS7 field values */
+ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
+
+/* HDMI_FC_AUDSCHNLS8 field values */
+ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
+ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
+ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
+ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
+
+/* FC_AUDSCONF field values */
+ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
+ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
+ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
+ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
+ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
+ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
+
+/* FC_PRCONF field values */
+ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
+ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
+ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
+ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
+
+/* FC_AVICONF0-FC_AVICONF2 field values */
+ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x60,
+ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x20,
+ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x40,
+ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x10,
+ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x10,
+ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
+ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x40,
+ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x80,
+ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0xC0,
+ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x03,
+ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x01,
+ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x02,
+ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
+ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x09,
+ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
+ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
+ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
+ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
+
+ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
+ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
+ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+ HDMI_FC_AVICONF2_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+ HDMI_FC_AVICONF2_IT_CONTENT_TYPE_PHOTO = 0x01,
+ HDMI_FC_AVICONF2_IT_CONTENT_TYPE_CINEMA = 0x02,
+ HDMI_FC_AVICONF2_IT_CONTENT_TYPE_GAME = 0x03,
+ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
+ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+/* FC_DBGFORCE field values */
+ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+
+/* PHY_CONF0 field values */
+ HDMI_PHY_CONF0_PDZ = 0x80,
+ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+ HDMI_PHY_CONF0_ENTMDS = 0x40,
+ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+ HDMI_PHY_CONF0_SPARECTRL = 0x20,
+ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+ HDMI_PHY_CONF0_GEN2_PDDQ_ENABLE = 0x10,
+ HDMI_PHY_CONF0_GEN2_PDDQ_DISABLE = 0x00,
+ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+ HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_ON = 0x8,
+ HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_OFF = 0x0,
+ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE = 0x4,
+ HDMI_PHY_CONF0_SELDATAENPOL = 0x2,
+ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+ HDMI_PHY_CONF0_SELDIPIF = 0x1,
+ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+/* PHY_TST0 field values */
+ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
+ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
+ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
+ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
+
+/* PHY_STAT0 field values */
+ HDMI_PHY_RX_SENSE3 = 0x80,
+ HDMI_PHY_RX_SENSE2 = 0x40,
+ HDMI_PHY_RX_SENSE1 = 0x20,
+ HDMI_PHY_RX_SENSE0 = 0x10,
+ HDMI_PHY_HPD = 0x02,
+ HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+/* PHY_I2CM_SLAVE_ADDR field values */
+ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
+
+/* PHY_I2CM_OPERATION_ADDR field values */
+ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
+
+/* AUD_CTS3 field values */
+ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+ /* note that the CTS3 MANUAL bit has been removed
+ from our part. Can't set it, will read as 0. */
+ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+/* AHB_DMA_CONF0 field values */
+ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
+ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
+ HDMI_AHB_DMA_CONF0_HBR = 0x10,
+ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
+ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
+ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
+ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
+ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
+ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
+ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
+ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
+
+/* HDMI_AHB_DMA_START field values */
+ HDMI_AHB_DMA_START_START_OFFSET = 0,
+ HDMI_AHB_DMA_START_START_MASK = 0x01,
+
+/* HDMI_AHB_DMA_STOP field values */
+ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
+ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
+
+/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
+ HDMI_AHB_DMA_DONE = 0x80,
+ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
+ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
+ HDMI_AHB_DMA_ERROR = 0x10,
+ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
+ HDMI_AHB_DMA_FIFO_FULL = 0x02,
+ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
+
+/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
+ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
+ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
+
+/* MC_CLKDIS field values */
+ HDMI_MC_CLKDIS_HDCPCLK_DISABLE_MASK = 0x40,
+ HDMI_MC_CLKDIS_HDCPCLK_DISABLE_DISABLE = 0x40,
+ HDMI_MC_CLKDIS_HDCPCLK_DISABLE_ENABLE = 0x00,
+ HDMI_MC_CLKDIS_CECCLK_DISABLE_MASK = 0x20,
+ HDMI_MC_CLKDIS_CECCLK_DISABLE_DISABLE = 0x20,
+ HDMI_MC_CLKDIS_CECCLK_DISABLE_ENABLE = 0x00,
+ HDMI_MC_CLKDIS_CSCCLK_DISABLE_MASK = 0x10,
+ HDMI_MC_CLKDIS_CSCCLK_DISABLE_DISABLE = 0x10,
+ HDMI_MC_CLKDIS_CSCCLK_DISABLE_ENABLE = 0x00,
+ HDMI_MC_CLKDIS_AUDCLK_DISABLE_MASK = 0x8,
+ HDMI_MC_CLKDIS_AUDCLK_DISABLE_DISABLE = 0x8,
+ HDMI_MC_CLKDIS_AUDCLK_DISABLE_ENABLE = 0x0,
+ HDMI_MC_CLKDIS_PREPCLK_DISABLE_MASK = 0x4,
+ HDMI_MC_CLKDIS_PREPCLK_DISABLE_DISABLE = 0x4,
+ HDMI_MC_CLKDIS_PREPCLK_DISABLE_ENABLE = 0x0,
+ HDMI_MC_CLKDIS_TMDSCLK_DISABLE_MASK = 0x2,
+ HDMI_MC_CLKDIS_TMDSCLK_DISABLE_DISABLE = 0x2,
+ HDMI_MC_CLKDIS_TMDSCLK_DISABLE_ENABLE = 0x0,
+ HDMI_MC_CLKDIS_PIXELCLK_DISABLE_MASK = 0x1,
+ HDMI_MC_CLKDIS_PIXELCLK_DISABLE_DISABLE = 0x1,
+ HDMI_MC_CLKDIS_PIXELCLK_DISABLE_ENABLE = 0x0,
+
+/* MC_FLOWCTRL field values */
+ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
+ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+/* MC_PHYRSTZ field values */
+ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+/* MC_HEACPHY_RST field values */
+ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
+
+/* CSC_CFG field values */
+ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+/* CSC_SCALE field values */
+ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+
+/* A_HDCPCFG0 field values */
+ HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
+ HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
+ HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
+ HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
+ HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
+ HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
+ HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
+ HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
+ HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
+ HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
+ HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
+ HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
+ HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
+ HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
+ HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
+ HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
+ HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
+ HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
+ HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
+ HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
+ HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
+ HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
+ HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
+ HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
+
+/* A_HDCPCFG1 field values */
+ HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
+ HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
+ HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
+ HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
+ HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
+ HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
+ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
+ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
+ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
+ HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
+ HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
+
+/* A_VIDPOLCFG field values */
+ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
+ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
+ HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
+ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
+ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
+ HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
+ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
+ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
+ HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
+ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
+ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
+};
+
+#endif /* __MXC_HDMI_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
index 0f81fb9eb7d..dd162a22dfe 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
@@ -55,11 +55,14 @@ struct vpu_mem_desc {
#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
+#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
+#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
#define BIT_CODE_RUN 0x000
#define BIT_CODE_DOWN 0x004
#define BIT_INT_CLEAR 0x00C
#define BIT_INT_STATUS 0x010
+#define BIT_INT_REASON 0x174
#define MJPEG_PIC_STATUS_REG 0x3004
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 99a9cdb9d6b..f7bc8718684 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
@@ -72,6 +72,21 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value)
+{
+ int i = 0;
+ u32 reg;
+ reg = __raw_readl(base + group * 4);
+ while (num_bits) {
+ reg &= ~(1<<(start_bit + i));
+ i++;
+ num_bits--;
+ }
+ reg |= (value << start_bit);
+ __raw_writel(reg, base + group * 4);
+}
+EXPORT_SYMBOL(mxc_iomux_set_gpr_register);
+
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
base = iomux_v3_base;
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 2b8c0c3c0bb..6b78490c632 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -157,6 +157,9 @@ struct pwm_device *pwm_request(int pwm_id, const char *label)
if (pwm->pwm_id == pwm_id) {
found = 1;
break;
+ } else if ((int)pwm->pdev->dev.of_node == pwm_id) {
+ found = 1;
+ break;
}
}
@@ -274,9 +277,15 @@ static int __devexit mxc_pwm_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id mxc_pwm_dt_ids[] = {
+ { .compatible = "fsl,imx6q-pwm", },
+ { /* sentinel */ }
+};
+
static struct platform_driver mxc_pwm_driver = {
.driver = {
.name = "mxc_pwm",
+ .of_match_table = mxc_pwm_dt_ids,
},
.probe = mxc_pwm_probe,
.remove = __devexit_p(mxc_pwm_remove),
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 58832e578ff..08432ce7c67 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -130,6 +130,7 @@ struct imx_i2c_struct {
static const struct of_device_id i2c_imx_dt_ids[] = {
{ .compatible = "fsl,imx1-i2c", },
+ { .compatible = "fsl,imx6q-i2c", },
{ /* sentinel */ }
};
diff --git a/drivers/media/video/mxc/output/Kconfig b/drivers/media/video/mxc/output/Kconfig
index 72b32879697..4f747509792 100644
--- a/drivers/media/video/mxc/output/Kconfig
+++ b/drivers/media/video/mxc/output/Kconfig
@@ -1,6 +1,7 @@
config VIDEO_MXC_IPU_OUTPUT
bool "IPU v4l2 support"
depends on VIDEO_MXC_OUTPUT && MXC_IPU && FB_MXC
+ select VIDEOBUF_DMA_CONTIG
default y
---help---
This is the video4linux2 driver for IPU post processing video output.
diff --git a/drivers/media/video/mxc/output/mxc_vout.c b/drivers/media/video/mxc/output/mxc_vout.c
index 08edfb3087e..8092e670114 100644
--- a/drivers/media/video/mxc/output/mxc_vout.c
+++ b/drivers/media/video/mxc/output/mxc_vout.c
@@ -772,9 +772,10 @@ static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
return 0;
}
-static inline int ipu_try_task(struct ipu_task *task)
+static inline int ipu_try_task(struct mxc_vout_output *vout)
{
int ret;
+ struct ipu_task *task = &vout->task;
again:
ret = ipu_check_task(task);
@@ -789,11 +790,19 @@ again:
goto again;
}
if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
- task->output.crop.w -= 8;
+ if (vout->disp_support_windows) {
+ task->output.width -= 8;
+ task->output.crop.w = task->output.width;
+ } else
+ task->output.crop.w -= 8;
goto again;
}
if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
- task->output.crop.h -= 8;
+ if (vout->disp_support_windows) {
+ task->output.height -= 8;
+ task->output.crop.h = task->output.height;
+ } else
+ task->output.crop.h -= 8;
goto again;
}
ret = -EINVAL;
@@ -830,7 +839,7 @@ static int mxc_vout_try_task(struct mxc_vout_output *vout)
else
vout->task.output.format = IPU_PIX_FMT_RGB565;
}
- ret = ipu_try_task(&vout->task);
+ ret = ipu_try_task(vout);
}
return ret;
@@ -1575,7 +1584,7 @@ static int __init mxc_vout_setup_output(struct mxc_vout_dev *dev)
return ret;
}
-static int __init mxc_vout_probe(struct platform_device *pdev)
+static int mxc_vout_probe(struct platform_device *pdev)
{
int ret;
struct mxc_vout_dev *dev;
@@ -1621,9 +1630,15 @@ static int mxc_vout_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id mxc_vout_dt_ids[] = {
+ { .compatible = "fsl,vout_ipuv3", },
+ { /* sentinel */ }
+};
+
static struct platform_driver mxc_vout_driver = {
.driver = {
.name = "mxc_v4l2_output",
+ .of_match_table = mxc_vout_dt_ids,
},
.probe = mxc_vout_probe,
.remove = mxc_vout_remove,
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 7726c728a7f..6db8fb5a186 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -809,6 +809,15 @@ config MFD_INTEL_MSIC
Passage) chip. This chip embeds audio, battery, GPIO, etc.
devices used in Intel Medfield platforms.
+config MFD_MXC_HDMI
+ tristate "MXC HDMI Core"
+ depends on MXC_IPU
+ select MFD_CORE
+ default y
+ help
+ This is the core driver for the i.Mx on-chip HDMI. This MFD
+ driver connects with the video and audio drivers for HDMI.
+
endmenu
endif
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index abad5831ac5..9da178bf2e5 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -106,3 +106,4 @@ obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
+obj-$(CONFIG_MFD_MXC_HDMI) += mxc-hdmi-core.o
diff --git a/drivers/mfd/mxc-hdmi-core.c b/drivers/mfd/mxc-hdmi-core.c
new file mode 100644
index 00000000000..f9cb48b5ffe
--- /dev/null
+++ b/drivers/mfd/mxc-hdmi-core.c
@@ -0,0 +1,590 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <asm/mach-types.h>
+
+#include <mach/clock.h>
+#include <mach/mxc_hdmi.h>
+#include <mach/ipu-v3.h>
+#include <mach/iomux-v3.h>
+#include "../mxc/ipu3/ipu_prv.h"
+#include <linux/mfd/mxc-hdmi-core.h>
+#include <linux/fsl_devices.h>
+
+struct mxc_hdmi_data {
+ struct platform_device *pdev;
+ unsigned long __iomem *reg_base;
+ unsigned long reg_phys_base;
+ struct device *dev;
+};
+
+static unsigned long hdmi_base;
+struct clk *isfr_clk;
+struct clk *iahb_clk;
+static unsigned int irq_enable_cnt;
+spinlock_t irq_spinlock;
+bool irq_initialized;
+bool irq_enabled;
+unsigned int sample_rate;
+unsigned long pixel_clk_rate;
+struct clk *pixel_clk;
+int hdmi_ratio;
+int mxc_hdmi_ipu_id;
+int mxc_hdmi_disp_id;
+
+u8 hdmi_readb(unsigned int reg)
+{
+ u8 value;
+
+ value = __raw_readb(hdmi_base + reg);
+
+ pr_debug("hdmi rd: 0x%04x = 0x%02x\n", reg, value);
+
+ return value;
+}
+
+void hdmi_writeb(u8 value, unsigned int reg)
+{
+ pr_debug("hdmi wr: 0x%04x = 0x%02x\n", reg, value);
+ __raw_writeb(value, hdmi_base + reg);
+}
+
+void hdmi_mask_writeb(u8 data, unsigned int reg, u8 shift, u8 mask)
+{
+ u8 value = hdmi_readb(reg) & ~mask;
+ value |= (data << shift) & mask;
+ hdmi_writeb(value, reg);
+}
+
+unsigned int hdmi_read4(unsigned int reg)
+{
+ /* read a four byte address from registers */
+ return (hdmi_readb(reg + 3) << 24) |
+ (hdmi_readb(reg + 2) << 16) |
+ (hdmi_readb(reg + 1) << 8) |
+ hdmi_readb(reg);
+}
+
+void hdmi_write4(unsigned int value, unsigned int reg)
+{
+ /* write a four byte address to hdmi regs */
+ hdmi_writeb(value & 0xff, reg);
+ hdmi_writeb((value >> 8) & 0xff, reg + 1);
+ hdmi_writeb((value >> 16) & 0xff, reg + 2);
+ hdmi_writeb((value >> 24) & 0xff, reg + 3);
+}
+
+void hdmi_irq_init()
+{
+ /* First time IRQ is initialized, set enable_cnt to 1,
+ * since IRQ starts out enabled after request_irq */
+ if (!irq_initialized) {
+ irq_enable_cnt = 1;
+ irq_initialized = true;
+ irq_enabled = true;
+ }
+}
+
+void hdmi_irq_enable(int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_spinlock, flags);
+
+ if (!irq_enabled) {
+ enable_irq(irq);
+ irq_enabled = true;
+ }
+
+ irq_enable_cnt++;
+
+ spin_unlock_irqrestore(&irq_spinlock, flags);
+}
+
+unsigned int hdmi_irq_disable(int irq)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_spinlock, flags);
+
+ WARN_ON (irq_enable_cnt == 0);
+
+ irq_enable_cnt--;
+
+ /* Only disable HDMI IRQ if IAHB clk is off */
+ if ((irq_enable_cnt == 0) && (clk_get_usecount(iahb_clk) == 0)) {
+ disable_irq_nosync(irq);
+ irq_enabled = false;
+ spin_unlock_irqrestore(&irq_spinlock, flags);
+ return IRQ_DISABLE_SUCCEED;
+ }
+
+ spin_unlock_irqrestore(&irq_spinlock, flags);
+
+ return IRQ_DISABLE_FAIL;
+}
+
+static void initialize_hdmi_ih_mutes(void)
+{
+ u8 ih_mute;
+
+ /*
+ * Boot up defaults are:
+ * HDMI_IH_MUTE = 0x03 (disabled)
+ * HDMI_IH_MUTE_* = 0x00 (enabled)
+ */
+
+ /* Disable top level interrupt bits in HDMI block */
+ ih_mute = hdmi_readb(HDMI_IH_MUTE) |
+ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+
+ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
+
+ /* Disable interrupts in the IH_MUTE_* registers */
+ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT1);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT2);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_AS_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_PHY_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CM_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_CEC_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_VP_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
+ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
+
+ /* Enable top level interrupt bits in HDMI block */
+ ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
+ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
+}
+
+static void hdmi_set_clock_regenerator_n(unsigned int value)
+{
+ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
+ hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
+ hdmi_writeb((value >> 16) & 0xff, HDMI_AUD_N3);
+}
+
+static void hdmi_set_clock_regenerator_cts(unsigned int cts)
+{
+ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
+ hdmi_writeb((cts >> 8) & 0xff, HDMI_AUD_CTS2);
+ hdmi_writeb(((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
+ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+}
+
+static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
+ unsigned int ratio)
+{
+ unsigned int n = (128 * freq) / 1000;
+
+ switch (freq) {
+ case 32000:
+ if (pixel_clk == 25170000)
+ n = (ratio == 150) ? 9152 : 4576;
+ else if (pixel_clk == 27020000)
+ n = (ratio == 150) ? 8192 : 4096;
+ else if (pixel_clk == 74170000 || pixel_clk == 148350000)
+ n = 11648;
+ else
+ n = 4096;
+ break;
+
+ case 44100:
+ if (pixel_clk == 25170000)
+ n = 7007;
+ else if (pixel_clk == 74170000)
+ n = 17836;
+ else if (pixel_clk == 148350000)
+ n = (ratio == 150) ? 17836 : 8918;
+ else
+ n = 6272;
+ break;
+
+ case 48000:
+ if (pixel_clk == 25170000)
+ n = (ratio == 150) ? 9152 : 6864;
+ else if (pixel_clk == 27020000)
+ n = (ratio == 150) ? 8192 : 6144;
+ else if (pixel_clk == 74170000)
+ n = 11648;
+ else if (pixel_clk == 148350000)
+ n = (ratio == 150) ? 11648 : 5824;
+ else
+ n = 6144;
+ break;
+
+ case 88200:
+ n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
+ break;
+
+ case 96000:
+ n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
+ break;
+
+ case 176400:
+ n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
+ break;
+
+ case 192000:
+ n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
+ break;
+
+ default:
+ break;
+ }
+
+ return n;
+}
+
+static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
+ unsigned int ratio)
+{
+ unsigned int cts = 0;
+ switch (freq) {
+ case 32000:
+ if (pixel_clk == 297000000) {
+ cts = 222750;
+ break;
+ }
+ case 48000:
+ case 96000:
+ case 192000:
+ switch (pixel_clk) {
+ case 25200000:
+ case 27000000:
+ case 54000000:
+ case 74250000:
+ case 148500000:
+ cts = pixel_clk / 1000;
+ break;
+ case 297000000:
+ cts = 247500;
+ break;
+ /*
+ * All other TMDS clocks are not supported by
+ * DWC_hdmi_tx. The TMDS clocks divided or
+ * multiplied by 1,001 coefficients are not
+ * supported.
+ */
+ default:
+ break;
+ }
+ break;
+ case 44100:
+ case 88200:
+ case 176400:
+ switch (pixel_clk) {
+ case 25200000:
+ cts = 28000;
+ break;
+ case 27000000:
+ cts = 30000;
+ break;
+ case 54000000:
+ cts = 60000;
+ break;
+ case 74250000:
+ cts = 82500;
+ break;
+ case 148500000:
+ cts = 165000;
+ break;
+ case 297000000:
+ cts = 247500;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ if (ratio == 100)
+ return cts;
+ else
+ return (cts * ratio) / 100;
+}
+
+static void hdmi_get_pixel_clk(void)
+{
+ struct ipu_soc *ipu;
+
+ if (pixel_clk == NULL) {
+ ipu = ipu_get_soc(mxc_hdmi_ipu_id);
+ pixel_clk = clk_get(ipu->dev, "pixel_clk_0");
+ if (IS_ERR(pixel_clk)) {
+ pr_err("%s could not get pixel_clk_0\n", __func__);
+ return;
+ }
+ }
+
+ pixel_clk_rate = clk_get_rate(pixel_clk);
+}
+
+/*
+ * input: audio sample rate and video pixel rate
+ * output: N and cts written to the HDMI regs.
+ */
+void hdmi_set_clk_regenerator(void)
+{
+ unsigned int clk_n, clk_cts;
+
+ /* Get pixel clock from ipu */
+ hdmi_get_pixel_clk();
+
+ pr_debug("%s: sample rate is %d ; ratio is %d ; pixel clk is %d\n",
+ __func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate);
+
+ clk_n = hdmi_compute_n(sample_rate, pixel_clk_rate, hdmi_ratio);
+ clk_cts = hdmi_compute_cts(sample_rate, pixel_clk_rate, hdmi_ratio);
+
+ if (clk_cts == 0) {
+ pr_err("%s: pixel clock not supported: %d\n",
+ __func__, (int)pixel_clk_rate);
+ return;
+ }
+
+ clk_enable(isfr_clk);
+ clk_enable(iahb_clk);
+
+ hdmi_set_clock_regenerator_n(clk_n);
+ hdmi_set_clock_regenerator_cts(clk_cts);
+
+ clk_disable(iahb_clk);
+ clk_disable(isfr_clk);
+}
+
+void hdmi_set_sample_rate(unsigned int rate)
+{
+ sample_rate = rate;
+ hdmi_set_clk_regenerator();
+}
+
+static void hdmi_init(int ipu_id, int disp_id)
+{
+ int hdmi_mux_setting;
+
+ if ((ipu_id > 1) || (ipu_id < 0)) {
+ printk(KERN_ERR"Invalid IPU select for HDMI: %d. Set to 0\n",
+ ipu_id);
+ ipu_id = 0;
+ }
+
+ if ((disp_id > 1) || (disp_id < 0)) {
+ printk(KERN_ERR"Invalid DI select for HDMI: %d. Set to 0\n",
+ disp_id);
+ disp_id = 0;
+ }
+
+ /* Configure the connection between IPU1/2 and HDMI */
+ hdmi_mux_setting = 2*ipu_id + disp_id;
+
+ /* GPR3, bits 2-3 = HDMI_MUX_CTL */
+ mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
+}
+
+static struct fsl_mxc_hdmi_platform_data hdmi_vdata = {
+ .init = hdmi_init,
+};
+
+static int mxc_hdmi_core_probe(struct platform_device *pdev)
+{
+ struct fsl_mxc_hdmi_core_platform_data *pdata = pdev->dev.platform_data;
+ struct mxc_hdmi_data *hdmi_data;
+ struct resource *res;
+ int ret = 0;
+ struct platform_device_info pdevinfo_hdmi_v;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ hdmi_data = kzalloc(sizeof(struct mxc_hdmi_data), GFP_KERNEL);
+ if (!hdmi_data) {
+ dev_err(&pdev->dev, "Couldn't allocate mxc hdmi mfd device\n");
+ return -ENOMEM;
+ }
+ hdmi_data->pdev = pdev;
+
+ pixel_clk = NULL;
+ sample_rate = 48000;
+ pixel_clk_rate = 74250000;
+ hdmi_ratio = 100;
+
+ irq_enable_cnt = 0;
+ irq_initialized = false;
+ irq_enabled = true;
+ spin_lock_init(&irq_spinlock);
+
+ isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr_clk");
+ if (IS_ERR(isfr_clk)) {
+ ret = PTR_ERR(isfr_clk);
+ dev_err(&hdmi_data->pdev->dev,
+ "Unable to get HDMI isfr clk: %d\n", ret);
+ goto eclkg;
+ }
+
+ ret = clk_enable(isfr_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
+ goto eclke;
+ }
+
+ pr_debug("%s isfr_clk:%d\n", __func__,
+ (int)clk_get_rate(isfr_clk));
+
+ iahb_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_iahb_clk");
+ if (IS_ERR(iahb_clk)) {
+ ret = PTR_ERR(iahb_clk);
+ dev_err(&hdmi_data->pdev->dev,
+ "Unable to get HDMI iahb clk: %d\n", ret);
+ goto eclkg2;
+ }
+
+ ret = clk_enable(iahb_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
+ goto eclke2;
+ }
+
+ hdmi_data->reg_phys_base = res->start;
+ if (!request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev))) {
+ dev_err(&pdev->dev, "request_mem_region failed\n");
+ ret = -EBUSY;
+ goto emem;
+ }
+
+ hdmi_data->reg_base = ioremap(res->start, resource_size(res));
+ if (!hdmi_data->reg_base) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto eirq;
+ }
+ hdmi_base = (unsigned long)hdmi_data->reg_base;
+
+ pr_debug("\n%s hdmi hw base = 0x%08x\n\n", __func__, (int)res->start);
+
+ if (pdata) {
+ mxc_hdmi_ipu_id = pdata->ipu_id;
+ mxc_hdmi_disp_id = pdata->disp_id;
+ } else {
+ of_property_read_u32(pdev->dev.of_node, "ipu", &mxc_hdmi_ipu_id);
+ of_property_read_u32(pdev->dev.of_node, "di", &mxc_hdmi_disp_id);
+ }
+
+ initialize_hdmi_ih_mutes();
+
+ /* Disable HDMI clocks until video/audio sub-drivers are initialized */
+ clk_disable(isfr_clk);
+ clk_disable(iahb_clk);
+
+ /* Replace platform data coming in with a local struct */
+ platform_set_drvdata(pdev, hdmi_data);
+
+ /* register hdmi video */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ pdevinfo_hdmi_v.name = "mxc_hdmi";
+ pdevinfo_hdmi_v.res = res;
+ pdevinfo_hdmi_v.num_res = 1;
+ pdevinfo_hdmi_v.data = &hdmi_vdata;
+ pdevinfo_hdmi_v.size_data = sizeof(hdmi_vdata);
+ pdevinfo_hdmi_v.dma_mask = DMA_BIT_MASK(32);
+ platform_device_register_full(&pdevinfo_hdmi_v);
+
+ return ret;
+
+eirq:
+ release_mem_region(res->start, resource_size(res));
+emem:
+ clk_disable(iahb_clk);
+eclke2:
+ clk_put(iahb_clk);
+eclkg2:
+ clk_disable(isfr_clk);
+eclke:
+ clk_put(isfr_clk);
+eclkg:
+ kfree(hdmi_data);
+ return ret;
+}
+
+
+static int __exit mxc_hdmi_core_remove(struct platform_device *pdev)
+{
+ struct mxc_hdmi_data *hdmi_data = platform_get_drvdata(pdev);
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ iounmap(hdmi_data->reg_base);
+ release_mem_region(res->start, resource_size(res));
+
+ kfree(hdmi_data);
+
+ return 0;
+}
+
+static const struct of_device_id mxc_hdmi_core_dt_ids[] = {
+ { .compatible = "fsl,imx6q-hdmi-core", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver mxc_hdmi_core_driver = {
+ .driver = {
+ .name = "mxc_hdmi_core",
+ .owner = THIS_MODULE,
+ .of_match_table = mxc_hdmi_core_dt_ids,
+ },
+ .remove = __exit_p(mxc_hdmi_core_remove),
+};
+
+static int __init mxc_hdmi_core_init(void)
+{
+ return platform_driver_probe(&mxc_hdmi_core_driver,
+ mxc_hdmi_core_probe);
+}
+
+static void __exit mxc_hdmi_core_exit(void)
+{
+ platform_driver_unregister(&mxc_hdmi_core_driver);
+}
+
+subsys_initcall(mxc_hdmi_core_init);
+module_exit(mxc_hdmi_core_exit);
+
+MODULE_DESCRIPTION("Core driver for Freescale i.Mx on-chip HDMI");
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig
index d2b05814832..8b4e6ccd7f7 100644
--- a/drivers/mxc/Kconfig
+++ b/drivers/mxc/Kconfig
@@ -6,13 +6,14 @@ menu "MXC support drivers"
config MXC_IPU
bool "Image Processing Unit Driver"
- depends on !ARCH_MX21
- depends on !ARCH_MX27
- depends on !ARCH_MX25
- select MXC_IPU_V1 if !ARCH_MX37 && !ARCH_MX5
- select MXC_IPU_V3 if ARCH_MX37 || ARCH_MX5
- select MXC_IPU_V3D if ARCH_MX37
- select MXC_IPU_V3EX if ARCH_MX5
+ depends on !SOC_MX21
+ depends on !SOC_MX27
+ depends on !SOC_MX25
+ select MXC_IPU_V1 if !SOC_MX37 && !SOC_MX5 && !SOC_IMX6Q
+ select MXC_IPU_V3 if SOC_MX37 || SOC_MX5 || SOC_IMX6Q
+ select MXC_IPU_V3D if SOC_MX37
+ select MXC_IPU_V3EX if SOC_MX5
+ select MXC_IPU_V3H if SOC_IMX6Q
help
If you plan to use the Image Processing unit, say
Y here. IPU is needed by Framebuffer and V4L2 drivers.
diff --git a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
index 1e05cc5808b..aa9fdaf27cd 100644
--- a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
+++ b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
@@ -52,8 +52,8 @@ static u32 truncate(u32 up, /* 0: down; else: up */
return d;
}
-/*static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
-{[> return input_f <]
+static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
+{/* return input_f */
unsigned int f_calculated = 0;
switch (pfs) {
case IPU_PIX_FMT_YVU422P:
@@ -129,7 +129,7 @@ static unsigned int m_calc(unsigned int pfs)
}
return m_calculated;
-}*/
+}
/* Stripe parameters calculator */
@@ -214,14 +214,14 @@ int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
/* M, F calculations */
/* read back pfs from params */
- input_f = 16;
+ input_f = f_calc(input_pixelformat, 0, NULL);
input_m = 16;
/* BPP should be used in the out_F calc */
/* Temporarily not used */
/* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */
output_f = 16;
- output_m = 16;
+ output_m = m_calc(output_pixelformat);
if ((input_frame_width < 4) || (output_frame_width < 4))
@@ -370,7 +370,6 @@ int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
left->output_column = 0;
right->output_column = onw;
}
-
return status;
}
EXPORT_SYMBOL(ipu_calc_stripes_sizes);
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 014125921c8..3113e7b933b 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -42,6 +42,7 @@
#include "ipu_param_mem.h"
static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
+static int ipu_idx;
int g_ipu_hw_rev;
/* Static functions */
@@ -381,9 +382,12 @@ static int __devinit ipu_probe(struct platform_device *pdev)
unsigned long ipu_base;
int ret = 0;
- if (pdev->id >= MXC_IPU_MAX_NUM)
+ if (ipu_idx >= MXC_IPU_MAX_NUM)
return -ENODEV;
+ pdev->id = ipu_idx;
+ ipu_idx++;
+
ipu = &ipu_array[pdev->id];
memset(ipu, 0, sizeof(struct ipu_soc));
@@ -391,7 +395,10 @@ static int __devinit ipu_probe(struct platform_device *pdev)
mutex_init(&ipu->mutex_lock);
atomic_set(&ipu->ipu_use_count, 0);
- g_ipu_hw_rev = plat_data->rev;
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "revision", &g_ipu_hw_rev);
+ if (ret < 0 && plat_data)
+ g_ipu_hw_rev = plat_data->rev;
ipu->dev = &pdev->dev;
@@ -662,8 +669,10 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel
if (params->csi_mem.mipi_en) {
ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
params->csi_mem.csi));
- _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_id,
+ _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_vc,
params->csi_mem.csi);
+ _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi_vc,
+ params->csi_mem.mipi_id, params->csi_mem.csi);
} else {
ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
params->csi_mem.csi));
@@ -2316,6 +2325,7 @@ int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
return -EINVAL;
}
+ _ipu_get(ipu);
_ipu_lock(ipu);
ipu->csi_use_count[csi]++;
@@ -2327,6 +2337,7 @@ int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
}
_ipu_unlock(ipu);
+ _ipu_put(ipu);
return 0;
}
EXPORT_SYMBOL(ipu_enable_csi);
@@ -2348,7 +2359,7 @@ int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
return -EINVAL;
}
-
+ _ipu_get(ipu);
_ipu_lock(ipu);
ipu->csi_use_count[csi]--;
if (ipu->csi_use_count[csi] == 0) {
@@ -2359,6 +2370,7 @@ int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
}
_ipu_unlock(ipu);
+ _ipu_put(ipu);
return 0;
}
EXPORT_SYMBOL(ipu_disable_csi);
@@ -2928,13 +2940,21 @@ static const struct dev_pm_ops mxcipu_pm_ops = {
.resume_noirq = ipu_resume_noirq,
};
+static const struct of_device_id mxc_ipu_dt_ids[] = {
+ { .compatible = "fsl,ipuv3", },
+ { /* sentinel */ }
+};
+
/*!
* This structure contains pointers to the power management callback functions.
*/
static struct platform_driver mxcipu_driver = {
.driver = {
.name = "imx-ipuv3",
+#ifdef CONFIG_PM
.pm = &mxcipu_pm_ops,
+#endif
+ .of_match_table = mxc_ipu_dt_ids,
},
.probe = ipu_probe,
.remove = ipu_remove,
diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c
index 7387e518deb..c34e65e1317 100644
--- a/drivers/mxc/ipu3/ipu_ic.c
+++ b/drivers/mxc/ipu3/ipu_ic.c
@@ -18,6 +18,7 @@
*
* @ingroup IPU
*/
+#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/errno.h>
diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h
index 7c803a1693d..42060c954a1 100644
--- a/drivers/mxc/ipu3/ipu_prv.h
+++ b/drivers/mxc/ipu3/ipu_prv.h
@@ -319,6 +319,7 @@ int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_
int burst_size, ipu_rotate_mode_t rot);
void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
+int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi);
void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
uint32_t g_value, uint32_t b_value,
uint32_t pix_clk, uint32_t csi);
diff --git a/drivers/mxc/vpu/Kconfig b/drivers/mxc/vpu/Kconfig
index dada2040e2a..f712241fa85 100644
--- a/drivers/mxc/vpu/Kconfig
+++ b/drivers/mxc/vpu/Kconfig
@@ -6,7 +6,7 @@ menu "MXC VPU(Video Processing Unit) support"
config MXC_VPU
tristate "Support for MXC VPU(Video Processing Unit)"
- depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX5 || ARCH_MX6)
+ depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX5 || SOC_IMX6Q)
default y
---help---
The VPU codec device provides codec function for H.264/MPEG4/H.263,
diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c
index 957d0ba0f7f..0f7be85e48f 100644
--- a/drivers/mxc/vpu/mxc_vpu.c
+++ b/drivers/mxc/vpu/mxc_vpu.c
@@ -28,6 +28,7 @@
#include <linux/platform_device.h>
#include <linux/kdev_t.h>
#include <linux/dma-mapping.h>
+#include <linux/iram_alloc.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/clk.h>
@@ -42,7 +43,6 @@
#include <asm/sizes.h>
#include <mach/clock.h>
#include <mach/hardware.h>
-#include <mach/iram.h>
#include <mach/mxc_vpu.h>
@@ -87,6 +87,7 @@ static struct mxc_vpu_platform_data *vpu_plat;
static struct iram_setting iram;
/* implement the blocking ioctl */
+static int irq_status;
static int codec_done;
static wait_queue_head_t vpu_queue;
@@ -212,14 +213,17 @@ static inline void vpu_worker_callback(struct work_struct *w)
if (dev->async_queue)
kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
- codec_done = 1;
- wake_up_interruptible(&vpu_queue);
-
+ irq_status = 1;
/*
* Clock is gated on when dec/enc started, gate it off when
- * interrupt is received.
+ * codec is done.
*/
- clk_disable(vpu_clk);
+ if (codec_done) {
+ clk_disable(vpu_clk);
+ codec_done = 0;
+ }
+
+ wake_up_interruptible(&vpu_queue);
}
/*!
@@ -228,8 +232,11 @@ static inline void vpu_worker_callback(struct work_struct *w)
static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
{
struct vpu_priv *dev = dev_id;
+ unsigned long reg;
- READ_REG(BIT_INT_STATUS);
+ reg = READ_REG(BIT_INT_REASON);
+ if (reg & 0x8)
+ codec_done = 1;
WRITE_REG(0x1, BIT_INT_CLEAR);
queue_work(dev->workqueue, &dev->work);
@@ -244,8 +251,11 @@ static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
static irqreturn_t vpu_jpu_irq_handler(int irq, void *dev_id)
{
struct vpu_priv *dev = dev_id;
+ unsigned long reg;
- WRITE_REG(0, MJPEG_PIC_STATUS_REG);
+ reg = READ_REG(MJPEG_PIC_STATUS_REG);
+ if (reg & 0x3)
+ codec_done = 1;
queue_work(dev->workqueue, &dev->work);
@@ -352,7 +362,7 @@ static long vpu_ioctl(struct file *filp, u_int cmd,
{
u_long timeout = (u_long) arg;
if (!wait_event_interruptible_timeout
- (vpu_queue, codec_done != 0,
+ (vpu_queue, irq_status != 0,
msecs_to_jiffies(timeout))) {
printk(KERN_WARNING "VPU blocking: timeout.\n");
ret = -ETIME;
@@ -361,7 +371,7 @@ static long vpu_ioctl(struct file *filp, u_int cmd,
"VPU interrupt received.\n");
ret = -ERESTARTSYS;
} else
- codec_done = 0;
+ irq_status = 0;
break;
}
case VPU_IOC_IRAM_SETTING:
@@ -471,6 +481,26 @@ static long vpu_ioctl(struct file *filp, u_int cmd,
}
break;
}
+ /*
+ * The following two ioctl is used when user allocates working buffer
+ * and register it to vpu driver.
+ */
+ case VPU_IOC_QUERY_BITWORK_MEM:
+ {
+ if (copy_to_user((void __user *)arg,
+ &bitwork_mem,
+ sizeof(struct vpu_mem_desc)))
+ ret = -EFAULT;
+ break;
+ }
+ case VPU_IOC_SET_BITWORK_MEM:
+ {
+ if (copy_from_user(&bitwork_mem,
+ (struct vpu_mem_desc *)arg,
+ sizeof(struct vpu_mem_desc)))
+ ret = -EFAULT;
+ break;
+ }
case VPU_IOC_SYS_SW_RESET:
{
if (vpu_plat->reset)
@@ -625,7 +655,10 @@ static int vpu_dev_probe(struct platform_device *pdev)
iram.end = addr + vpu_plat->iram_size - 1;
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (pdev->dev.of_node)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ else
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu_regs");
if (!res) {
printk(KERN_ERR "vpu: unable to get vpu base addr\n");
return -ENODEV;
@@ -659,30 +692,33 @@ static int vpu_dev_probe(struct platform_device *pdev)
goto err_out_class;
}
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
+ if (pdev->dev.of_node)
+ vpu_ipi_irq = platform_get_irq(pdev, 0);
+ else
+ vpu_ipi_irq = platform_get_irq_byname(pdev, "vpu_ipi_irq");
+ if (vpu_ipi_irq < 0) {
printk(KERN_ERR "vpu: unable to get vpu interrupt\n");
err = -ENXIO;
goto err_out_class;
}
- vpu_ipi_irq = res->start;
-
err = request_irq(vpu_ipi_irq, vpu_ipi_irq_handler, 0, "VPU_CODEC_IRQ",
(void *)(&vpu_data));
if (err)
goto err_out_class;
#ifdef MXC_VPU_HAS_JPU
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
- if (!res) {
+ if (pdev->dev.of_node)
+ vpu_jpu_irq = platform_get_irq(pdev, 1);
+ else
+ vpu_jpu_irq = platform_get_irq_byname(pdev, "vpu_jpu_irq");
+ if (vpu_jpu_irq < 0) {
printk(KERN_ERR "vpu: unable to get vpu jpu interrupt\n");
err = -ENXIO;
free_irq(vpu_ipi_irq, &vpu_data);
goto err_out_class;
}
- vpu_jpu_irq = res->start;
- err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, 0, "VPU_JPG_IRQ",
- (void *)(&vpu_data));
+ err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, IRQF_TRIGGER_RISING,
+ "VPU_JPG_IRQ", (void *)(&vpu_data));
if (err) {
free_irq(vpu_ipi_irq, &vpu_data);
goto err_out_class;
@@ -847,12 +883,18 @@ recover_clk:
#define vpu_resume NULL
#endif /* !CONFIG_PM */
+static const struct of_device_id mxc_vpu_dt_ids[] = {
+ { .compatible = "fsl,vpu", },
+ { /* sentinel */ }
+};
+
/*! Driver definition
*
*/
static struct platform_driver mxcvpu_driver = {
.driver = {
.name = "mxc_vpu",
+ .of_match_table = mxc_vpu_dt_ids,
},
.probe = vpu_dev_probe,
.remove = vpu_dev_remove,
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 163fc9021f5..e1d1af2c7b5 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -565,6 +565,10 @@ static irqreturn_t imx_int(int irq, void *dev_id)
if (sts & USR1_RTSD)
imx_rtsint(irq, dev_id);
+#ifdef CONFIG_PM
+ if (sts & USR1_AWAKE)
+ writel(USR1_AWAKE, sport->port.membase + USR1);
+#endif
return IRQ_HANDLED;
}
@@ -662,6 +666,7 @@ static int imx_startup(struct uart_port *port)
struct imx_port *sport = (struct imx_port *)port;
int retval;
unsigned long flags, temp;
+ struct tty_struct *tty;
imx_setup_ufcr(sport, 0);
@@ -792,6 +797,10 @@ static int imx_startup(struct uart_port *port)
pdata->irda_enable(1);
}
+ tty = sport->port.state->port.tty;
+#ifdef CONFIG_PM
+ device_set_wakeup_enable(tty->dev, 1);
+#endif
return 0;
error_out3:
@@ -1269,6 +1278,19 @@ static struct uart_driver imx_reg = {
static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
{
struct imx_port *sport = platform_get_drvdata(dev);
+ unsigned int val;
+
+ if (device_may_wakeup(&dev->dev)) {
+ enable_irq_wake(sport->rxirq);
+#ifdef CONFIG_PM
+ if (sport->port.line == 1) {
+ /* enable awake for MX6 */
+ val = readl(sport->port.membase + UCR3);
+ val |= UCR3_AWAKEN;
+ writel(val, sport->port.membase + UCR3);
+ }
+#endif
+ }
if (sport)
uart_suspend_port(&imx_reg, &sport->port);
@@ -1279,10 +1301,22 @@ static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
static int serial_imx_resume(struct platform_device *dev)
{
struct imx_port *sport = platform_get_drvdata(dev);
+ unsigned int val;
if (sport)
uart_resume_port(&imx_reg, &sport->port);
+ if (device_may_wakeup(&dev->dev)) {
+#ifdef CONFIG_PM
+ if (sport->port.line == 1) {
+ val = readl(sport->port.membase + UCR3);
+ val &= ~UCR3_AWAKEN;
+ writel(val, sport->port.membase + UCR3);
+ }
+#endif
+ disable_irq_wake(sport->rxirq);
+ }
+
return 0;
}
@@ -1408,6 +1442,10 @@ static int serial_imx_probe(struct platform_device *pdev)
goto deinit;
platform_set_drvdata(pdev, &sport->port);
+#ifdef CONFIG_PM
+ device_init_wakeup(&pdev->dev, 1);
+#endif
+
return 0;
deinit:
if (pdata && pdata->exit)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index de5806bb9ba..2a5e760b313 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2419,6 +2419,13 @@ if ARCH_MXC
source "drivers/video/mxc/Kconfig"
endif
+config FB_MXC_HDMI
+ depends on FB_MXC_SYNC_PANEL && I2C
+ tristate "MXC HDMI driver support"
+ select MFD_MXC_HDMI
+ help
+ Driver for the on-chip MXC HDMI controller.
+
if VT
source "drivers/video/console/Kconfig"
endif
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index bc77579e8de..9ea192b5cac 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_FB_KYRO) += kyro/
obj-$(CONFIG_FB_SAVAGE) += savage/
obj-$(CONFIG_FB_GEODE) += geode/
obj-$(CONFIG_FB_MBX) += mbx/
+obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o
obj-$(CONFIG_FB_MXC) += mxc/
obj-$(CONFIG_FB_NEOMAGIC) += neofb.o
obj-$(CONFIG_FB_3DFX) += tdfxfb.o
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 8b5b2a4124c..63ca212818a 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -83,6 +83,33 @@ static const struct backlight_ops pwm_backlight_ops = {
.check_fb = pwm_backlight_check_fb,
};
+struct platform_pwm_backlight_data of_data;
+static int of_get_pwm_data(struct platform_device *pdev,
+ struct platform_pwm_backlight_data *data)
+{
+ const __be32 *parp;
+ struct device_node *pwm_np, *np = pdev->dev.of_node;
+
+ if (!np)
+ return -EINVAL;
+
+ parp = of_get_property(np, "pwm-parent", NULL);
+ if (parp == NULL)
+ return -EINVAL;
+ of_node_put(np);
+
+ pwm_np = of_find_node_by_phandle(be32_to_cpup(parp));
+ if (pwm_np)
+ of_node_put(pwm_np);
+ data->pwm_id = (int)pwm_np;
+
+ of_property_read_u32(np, "max_brightness", &data->max_brightness);
+ of_property_read_u32(np, "dft_brightness", &data->dft_brightness);
+ of_property_read_u32(np, "pwm_period_ns", &data->pwm_period_ns);
+
+ return 0;
+}
+
static int pwm_backlight_probe(struct platform_device *pdev)
{
struct backlight_properties props;
@@ -92,8 +119,11 @@ static int pwm_backlight_probe(struct platform_device *pdev)
int ret;
if (!data) {
- dev_err(&pdev->dev, "failed to find platform data\n");
- return -EINVAL;
+ data = pdev->dev.platform_data = &of_data;
+ if (of_get_pwm_data(pdev, data) < 0) {
+ dev_err(&pdev->dev, "failed to find platform data\n");
+ return -EINVAL;
+ }
}
if (data->init) {
@@ -196,10 +226,16 @@ static int pwm_backlight_resume(struct platform_device *pdev)
#define pwm_backlight_resume NULL
#endif
+static const struct of_device_id pwm_bl_dt_ids[] = {
+ { .compatible = "pwm-bl", },
+ { /* sentinel */ }
+};
+
static struct platform_driver pwm_backlight_driver = {
.driver = {
.name = "pwm-backlight",
.owner = THIS_MODULE,
+ .of_match_table = pwm_bl_dt_ids,
},
.probe = pwm_backlight_probe,
.remove = pwm_backlight_remove,
diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig
index bb836c3a63f..053f62b7632 100644
--- a/drivers/video/mxc/Kconfig
+++ b/drivers/video/mxc/Kconfig
@@ -14,6 +14,11 @@ config FB_MXC
If you plan to use the LCD display with your MXC system, say
Y here.
+config FB_MXC_EDID
+ depends on FB_MXC && I2C
+ tristate "MXC EDID support"
+ default y
+
config FB_MXC_SYNC_PANEL
depends on FB_MXC
tristate "Synchronous Panel Framebuffer"
@@ -25,7 +30,7 @@ config FB_MXC_TVOUT_TVE
depends on MXC_IPU_V3
config FB_MXC_SII902X
- depends on FB_MXC_SYNC_PANEL
+ depends on FB_MXC_SYNC_PANEL && I2C
tristate "Si Image SII9022 DVI/HDMI Interface Chip"
config FB_MXC_LDB
diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile
index 4c75e1be2d3..e0d47ed90b4 100644
--- a/drivers/video/mxc/Makefile
+++ b/drivers/video/mxc/Makefile
@@ -1,5 +1,5 @@
obj-$(CONFIG_FB_MXC_TVOUT_TVE) += tve.o
obj-$(CONFIG_FB_MXC_SII902X) += mxcfb_sii902x.o
obj-$(CONFIG_FB_MXC_LDB) += ldb.o
-obj-$(CONFIG_FB_MODE_HELPERS) += mxc_edid.o
+obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o mxc_dvi.o
obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o
diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c
index 180bf7f6f8d..0fbf57444a6 100644
--- a/drivers/video/mxc/ldb.c
+++ b/drivers/video/mxc/ldb.c
@@ -37,6 +37,8 @@
#include <linux/regulator/consumer.h>
#include <linux/spinlock.h>
#include <linux/fsl_devices.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
#include <mach/hardware.h>
#include <mach/clock.h>
#include "mxc_dispdrv.h"
@@ -97,6 +99,30 @@ struct ldb_data {
int di;
} setting[2];
struct notifier_block nb;
+ uint8_t hwtype;
+};
+
+enum mxc_ldb_hwtype {
+ IMX5_LDB,
+ IMX6_LDB,
+};
+
+static struct platform_device_id mxc_ldb_devtype[] = {
+ {
+ .name = "imx5-ldb",
+ .driver_data = IMX5_LDB,
+ }, {
+ .name = "imx6-ldb",
+ .driver_data = IMX6_LDB,
+ }, {
+ /* sentinel */
+ }
+};
+
+static const struct of_device_id mxc_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx5-ldb", .data = &mxc_ldb_devtype[IMX5_LDB], },
+ { .compatible = "fsl,imx6q-ldb", .data = &mxc_ldb_devtype[IMX6_LDB], },
+ { /* sentinel */ }
};
static int g_ldb_mode;
@@ -297,11 +323,200 @@ int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
return 0;
}
+#define LVDS0_MUX_CTL_MASK (3 << 6)
+#define LVDS1_MUX_CTL_MASK (3 << 8)
+#define LVDS0_MUX_CTL_OFFS 6
+#define LVDS1_MUX_CTL_OFFS 8
+#define ROUTE_IPU0_DI0 0
+#define ROUTE_IPU0_DI1 1
+#define ROUTE_IPU1_DI0 2
+#define ROUTE_IPU1_DI1 3
+static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb)
+{
+ uint32_t reg;
+ int mode = ldb->mode;
+
+ reg = readl(ldb->gpr3_reg);
+ if ((mode == LDB_SPL_DI0) || (mode == LDB_DUL_DI0)) {
+ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
+ if (ipu == 0)
+ reg |= (ROUTE_IPU0_DI0 << LVDS0_MUX_CTL_OFFS) |
+ (ROUTE_IPU0_DI0 << LVDS1_MUX_CTL_OFFS);
+ else
+ reg |= (ROUTE_IPU1_DI0 << LVDS0_MUX_CTL_OFFS) |
+ (ROUTE_IPU1_DI0 << LVDS1_MUX_CTL_OFFS);
+ dev_dbg(&ldb->pdev->dev,
+ "Dual/Split mode both channels route to IPU%d-DI0\n", ipu);
+ } else if ((mode == LDB_SPL_DI1) || (mode == LDB_DUL_DI1)) {
+ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
+ if (ipu == 0)
+ reg |= (ROUTE_IPU0_DI1 << LVDS0_MUX_CTL_OFFS) |
+ (ROUTE_IPU0_DI1 << LVDS1_MUX_CTL_OFFS);
+ else
+ reg |= (ROUTE_IPU1_DI1 << LVDS0_MUX_CTL_OFFS) |
+ (ROUTE_IPU1_DI1 << LVDS1_MUX_CTL_OFFS);
+ dev_dbg(&ldb->pdev->dev,
+ "Dual/Split mode both channels route to IPU%d-DI1\n", ipu);
+ } else if (mode == LDB_SIN0) {
+ reg &= ~LVDS0_MUX_CTL_MASK;
+ if ((ipu == 0) && (di == 0))
+ reg |= ROUTE_IPU0_DI0 << LVDS0_MUX_CTL_OFFS;
+ else if ((ipu == 0) && (di == 1))
+ reg |= ROUTE_IPU0_DI1 << LVDS0_MUX_CTL_OFFS;
+ else if ((ipu == 1) && (di == 0))
+ reg |= ROUTE_IPU1_DI0 << LVDS0_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU1_DI1 << LVDS0_MUX_CTL_OFFS;
+ dev_dbg(&ldb->pdev->dev,
+ "Single mode channel 0 route to IPU%d-DI%d\n", ipu, di);
+ } else if (mode == LDB_SIN1) {
+ reg &= ~LVDS1_MUX_CTL_MASK;
+ if ((ipu == 0) && (di == 0))
+ reg |= ROUTE_IPU0_DI0 << LVDS1_MUX_CTL_OFFS;
+ else if ((ipu == 0) && (di == 1))
+ reg |= ROUTE_IPU0_DI1 << LVDS1_MUX_CTL_OFFS;
+ else if ((ipu == 1) && (di == 0))
+ reg |= ROUTE_IPU1_DI0 << LVDS1_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU1_DI1 << LVDS1_MUX_CTL_OFFS;
+ dev_dbg(&ldb->pdev->dev,
+ "Single mode channel 1 route to IPU%d-DI%d\n", ipu, di);
+ } else {
+ static bool first = true;
+ int channel;
+
+ if (first) {
+ if (mode == LDB_SEP0) {
+ reg &= ~LVDS0_MUX_CTL_MASK;
+ channel = 0;
+ } else {
+ reg &= ~LVDS1_MUX_CTL_MASK;
+ channel = 1;
+ }
+ first = false;
+ } else {
+ if (mode == LDB_SEP0) {
+ reg &= ~LVDS1_MUX_CTL_MASK;
+ channel = 1;
+ } else {
+ reg &= ~LVDS0_MUX_CTL_MASK;
+ channel = 0;
+ }
+ }
+
+ if ((ipu == 0) && (di == 0)) {
+ if (channel == 0)
+ reg |= ROUTE_IPU0_DI0 << LVDS0_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU0_DI0 << LVDS1_MUX_CTL_OFFS;
+ } else if ((ipu == 0) && (di == 1)) {
+ if (channel == 0)
+ reg |= ROUTE_IPU0_DI1 << LVDS0_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU0_DI1 << LVDS1_MUX_CTL_OFFS;
+ } else if ((ipu == 1) && (di == 0)) {
+ if (channel == 0)
+ reg |= ROUTE_IPU1_DI0 << LVDS0_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU1_DI0 << LVDS1_MUX_CTL_OFFS;
+ } else {
+ if (channel == 0)
+ reg |= ROUTE_IPU1_DI1 << LVDS0_MUX_CTL_OFFS;
+ else
+ reg |= ROUTE_IPU1_DI1 << LVDS1_MUX_CTL_OFFS;
+ }
+
+ dev_dbg(&ldb->pdev->dev, "Separate mode channel %d route to IPU%d-DI%d\n", channel, ipu, di);
+ }
+ writel(reg, ldb->gpr3_reg);
+
+ return 0;
+}
+
+static int of_get_ldb_data(struct ldb_data *ldb,
+ struct fsl_mxc_ldb_platform_data *plat_data)
+{
+ struct platform_device *pdev = ldb->pdev;
+ const struct of_device_id *of_id =
+ of_match_device(mxc_ldb_dt_ids, &pdev->dev);
+ struct device_node *np = pdev->dev.of_node;
+ uint32_t lvds0[2] = {0}, lvds1[2] = {0};
+ const char *mode, *ext_ref;
+ int ret;
+
+ if (!np)
+ return -EINVAL;
+
+ if (of_id)
+ pdev->id_entry = of_id->data;
+ ldb->hwtype = pdev->id_entry->driver_data;
+
+ ret = of_property_read_string(np, "mode", &mode);
+ if (ret < 0)
+ g_ldb_mode = LDB_SEP0;
+ else {
+ if (!strcmp(mode, "spl0"))
+ g_ldb_mode = LDB_SPL_DI0;
+ else if (!strcmp(mode, "spl1"))
+ g_ldb_mode = LDB_SPL_DI1;
+ else if (!strcmp(mode, "dul0"))
+ g_ldb_mode = LDB_DUL_DI0;
+ else if (!strcmp(mode, "dul1"))
+ g_ldb_mode = LDB_DUL_DI1;
+ else if (!strcmp(mode, "sin0"))
+ g_ldb_mode = LDB_SIN0;
+ else if (!strcmp(mode, "sin1"))
+ g_ldb_mode = LDB_SIN1;
+ else if (!strcmp(mode, "sep0"))
+ g_ldb_mode = LDB_SEP0;
+ else if (!strcmp(mode, "sep1"))
+ g_ldb_mode = LDB_SEP1;
+ }
+
+ ret = of_property_read_string(np, "ext_ref", &ext_ref);
+ if (ret < 0)
+ plat_data->ext_ref = 1;
+ else if (!strcmp(ext_ref, "true"))
+ plat_data->ext_ref = 1;
+
+ of_property_read_u32_array(np, "lvds0",
+ lvds0, ARRAY_SIZE(lvds0));
+ of_property_read_u32_array(np, "lvds1",
+ lvds1, ARRAY_SIZE(lvds1));
+
+ if ((g_ldb_mode == LDB_SPL_DI0) || (g_ldb_mode == LDB_DUL_DI0)) {
+ plat_data->ipu_id = lvds0[0];
+ plat_data->disp_id = 0;
+ } else if ((g_ldb_mode == LDB_SPL_DI1) || (g_ldb_mode == LDB_DUL_DI1)) {
+ plat_data->ipu_id = lvds0[0];
+ plat_data->disp_id = 1;
+ } else if (g_ldb_mode == LDB_SIN0) {
+ plat_data->ipu_id = lvds0[0];
+ plat_data->disp_id = lvds0[1];
+ } else if (g_ldb_mode == LDB_SIN1) {
+ plat_data->ipu_id = lvds1[0];
+ plat_data->disp_id = lvds1[1];
+ } else if (g_ldb_mode == LDB_SEP0) {
+ plat_data->ipu_id = lvds0[0];
+ plat_data->disp_id = lvds0[1];
+ plat_data->sec_ipu_id = lvds1[0];
+ plat_data->sec_disp_id = lvds1[1];
+ } else if (g_ldb_mode == LDB_SEP1) {
+ plat_data->ipu_id = lvds1[0];
+ plat_data->disp_id = lvds1[1];
+ plat_data->sec_ipu_id = lvds0[0];
+ plat_data->sec_disp_id = lvds0[1];
+ }
+
+ return 0;
+}
+
static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
{
int ret = 0, i;
struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+ struct fsl_mxc_ldb_platform_data of_data;
struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data;
struct resource *res;
uint32_t base_addr;
@@ -314,6 +529,14 @@ static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
setting->if_fmt = IPU_PIX_FMT_RGB666;
}
+ if (!plat_data) {
+ plat_data = &of_data;
+ if (of_get_ldb_data(ldb, plat_data) < 0) {
+ dev_err(&ldb->pdev->dev, "no platform data\n");
+ return -EINVAL;
+ }
+ }
+
if (!ldb->inited) {
char di_clk[] = "ipu1_di0_clk";
char ldb_clk[] = "ldb_di0_clk";
@@ -430,7 +653,11 @@ static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
writel(reg, ldb->control_reg);
/* clock setting */
- ldb_clk[6] += setting->disp_id;
+ if ((ldb->hwtype == IMX6_LDB) &&
+ ((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1)))
+ ldb_clk[6] += lvds_channel;
+ else
+ ldb_clk[6] += setting->disp_id;
ldb->ldb_di_clk[0] = clk_get(&ldb->pdev->dev, ldb_clk);
if (IS_ERR(ldb->ldb_di_clk[0])) {
dev_err(&ldb->pdev->dev, "get ldb clk0 failed\n");
@@ -474,8 +701,13 @@ static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
return -EINVAL;
}
- setting->dev_id = plat_data->ipu_id;
- setting->disp_id = !plat_data->disp_id;
+ if (ldb->hwtype == IMX6_LDB) {
+ setting->dev_id = plat_data->sec_ipu_id;
+ setting->disp_id = plat_data->sec_disp_id;
+ } else {
+ setting->dev_id = plat_data->ipu_id;
+ setting->disp_id = !plat_data->disp_id;
+ }
/* second output is LVDS0 or LVDS1 */
if (ldb->mode == LDB_SEP0)
@@ -507,7 +739,10 @@ static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
writel(reg, ldb->control_reg);
/* clock setting */
- ldb_clk[6] += setting->disp_id;
+ if (ldb->hwtype == IMX6_LDB)
+ ldb_clk[6] += lvds_channel;
+ else
+ ldb_clk[6] += setting->disp_id;
ldb->ldb_di_clk[1] = clk_get(&ldb->pdev->dev, ldb_clk);
if (IS_ERR(ldb->ldb_di_clk[1])) {
dev_err(&ldb->pdev->dev, "get ldb clk1 failed\n");
@@ -526,6 +761,14 @@ static int ldb_disp_init(struct mxc_dispdrv_entry *disp)
setting_idx = 1;
}
+ if (ldb->hwtype == IMX6_LDB) {
+ reg = readl(ldb->control_reg);
+ reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
+ reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI1;
+ writel(reg, ldb->control_reg);
+ ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb);
+ }
+
/*
* ldb_di0_clk -> ipux_di0_clk
* ldb_di1_clk -> ipux_di1_clk
@@ -581,6 +824,24 @@ static struct mxc_dispdrv_driver ldb_drv = {
.deinit = ldb_disp_deinit,
};
+static void ldb_disp_pwr_up(struct platform_device *pdev)
+{
+ int ret, gpio_pwr;
+ struct device_node *np = pdev->dev.of_node;
+
+ if (!np)
+ return;
+
+ gpio_pwr = of_get_named_gpio(np, "disp-pwr-gpios", 0);
+ if (gpio_pwr < 0)
+ dev_warn(&pdev->dev, "no pwr gpio defined\n");
+ else {
+ ret = gpio_request_one(gpio_pwr, GPIOF_OUT_INIT_HIGH, "disp-pwr");
+ if (ret)
+ dev_warn(&pdev->dev, "fail to request pwr gpio\n");
+ }
+}
+
/*!
* This function is called by the driver framework to initialize the LDB
* device.
@@ -607,6 +868,8 @@ static int ldb_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, ldb);
+ ldb_disp_pwr_up(pdev);
+
alloc_failed:
return ret;
}
@@ -623,6 +886,7 @@ static int ldb_remove(struct platform_device *pdev)
static struct platform_driver mxcldb_driver = {
.driver = {
.name = "mxc_ldb",
+ .of_match_table = mxc_ldb_dt_ids,
},
.probe = ldb_probe,
.remove = ldb_remove,
diff --git a/drivers/video/mxc/mxc_dvi.c b/drivers/video/mxc/mxc_dvi.c
new file mode 100644
index 00000000000..765670c8098
--- /dev/null
+++ b/drivers/video/mxc/mxc_dvi.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
+ */
+
+/*!
+ * @file mxc_dvi.c
+ *
+ * @brief MXC DVI driver
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/fsl_devices.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/regulator/consumer.h>
+#include <mach/mxc_edid.h>
+#include "mxc_dispdrv.h"
+#include "../edid.h"
+
+#define MXC_EDID_LENGTH (EDID_LENGTH*4)
+
+#define DISPDRV_DVI "dvi"
+
+struct mxc_dvi_data {
+ struct i2c_client *client;
+ struct platform_device *pdev;
+ struct mxc_dispdrv_entry *disp_dvi;
+ struct delayed_work det_work;
+ struct fb_info *fbi;
+ struct mxc_edid_cfg edid_cfg;
+ u8 cable_plugin;
+ u8 edid[MXC_EDID_LENGTH];
+
+ u32 ipu;
+ u32 di;
+ void (*init)(void);
+ int (*update)(void);
+ struct regulator *analog_reg;
+};
+
+static ssize_t mxc_dvi_show_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mxc_dvi_data *dvi = dev_get_drvdata(dev);
+
+ if (dvi->cable_plugin == 0)
+ strcpy(buf, "plugout\n");
+ else
+ strcpy(buf, "plugin\n");
+
+ return strlen(buf);
+}
+
+static DEVICE_ATTR(cable_state, S_IRUGO, mxc_dvi_show_state, NULL);
+
+static ssize_t mxc_dvi_show_name(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mxc_dvi_data *dvi = dev_get_drvdata(dev);
+
+ strcpy(buf, dvi->fbi->fix.id);
+ sprintf(buf+strlen(buf), "\n");
+
+ return strlen(buf);
+}
+
+static DEVICE_ATTR(fb_name, S_IRUGO, mxc_dvi_show_name, NULL);
+
+static ssize_t mxc_dvi_show_edid(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mxc_dvi_data *dvi = dev_get_drvdata(dev);
+ int i, j, len = 0;
+
+ for (j = 0; j < MXC_EDID_LENGTH/16; j++) {
+ for (i = 0; i < 16; i++)
+ len += sprintf(buf+len, "0x%02X ",
+ dvi->edid[j*16 + i]);
+ len += sprintf(buf+len, "\n");
+ }
+
+ return len;
+}
+
+static DEVICE_ATTR(edid, S_IRUGO, mxc_dvi_show_edid, NULL);
+
+static void det_worker(struct work_struct *work)
+{
+ struct delayed_work *delay_work = to_delayed_work(work);
+ struct mxc_dvi_data *dvi =
+ container_of(delay_work, struct mxc_dvi_data, det_work);
+ char event_string[16];
+ char *envp[] = { event_string, NULL };
+
+ /* cable connection changes */
+ if (dvi->update()) {
+ u8 edid_old[MXC_EDID_LENGTH];
+ dvi->cable_plugin = 1;
+ sprintf(event_string, "EVENT=plugin");
+
+ memcpy(edid_old, dvi->edid, MXC_EDID_LENGTH);
+
+ if (mxc_edid_read(dvi->client->adapter, dvi->client->addr,
+ dvi->edid, &dvi->edid_cfg, dvi->fbi) < 0)
+ dev_err(&dvi->client->dev,
+ "MXC dvi: read edid fail\n");
+ else {
+ if (!memcmp(edid_old, dvi->edid, MXC_EDID_LENGTH))
+ dev_info(&dvi->client->dev,
+ "Sii902x: same edid\n");
+ else if (dvi->fbi->monspecs.modedb_len > 0) {
+ int i;
+ const struct fb_videomode *mode;
+ struct fb_videomode m;
+
+ fb_destroy_modelist(&dvi->fbi->modelist);
+
+ for (i = 0; i < dvi->fbi->monspecs.modedb_len; i++)
+ /*FIXME now we do not support interlaced mode */
+ if (!(dvi->fbi->monspecs.modedb[i].vmode & FB_VMODE_INTERLACED))
+ fb_add_videomode(&dvi->fbi->monspecs.modedb[i],
+ &dvi->fbi->modelist);
+
+ fb_var_to_videomode(&m, &dvi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &dvi->fbi->modelist);
+
+ fb_videomode_to_var(&dvi->fbi->var, mode);
+
+ dvi->fbi->var.activate |= FB_ACTIVATE_FORCE;
+ console_lock();
+ dvi->fbi->flags |= FBINFO_MISC_USEREVENT;
+ fb_set_var(dvi->fbi, &dvi->fbi->var);
+ dvi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
+ console_unlock();
+ }
+ }
+ } else {
+ dvi->cable_plugin = 0;
+ sprintf(event_string, "EVENT=plugout");
+ }
+
+ kobject_uevent_env(&dvi->pdev->dev.kobj, KOBJ_CHANGE, envp);
+}
+
+static irqreturn_t mxc_dvi_detect_handler(int irq, void *data)
+{
+ struct mxc_dvi_data *dvi = data;
+ schedule_delayed_work(&(dvi->det_work), msecs_to_jiffies(300));
+ return IRQ_HANDLED;
+}
+
+static int dvi_init(struct mxc_dispdrv_entry *disp)
+{
+ int ret = 0;
+ struct mxc_dvi_data *dvi = mxc_dispdrv_getdata(disp);
+ struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+ struct fsl_mxc_dvi_platform_data *plat = dvi->client->dev.platform_data;
+
+ setting->dev_id = dvi->ipu = plat->ipu_id;
+ setting->disp_id = dvi->di = plat->disp_id;
+ setting->if_fmt = IPU_PIX_FMT_RGB24;
+ dvi->fbi = setting->fbi;
+ dvi->init = plat->init;
+ dvi->update = plat->update;
+
+ dvi->analog_reg = regulator_get(&dvi->pdev->dev, plat->analog_regulator);
+ if (!IS_ERR(dvi->analog_reg)) {
+ regulator_set_voltage(dvi->analog_reg, 2775000, 2775000);
+ regulator_enable(dvi->analog_reg);
+ }
+
+ if (dvi->init)
+ dvi->init();
+
+ /* get video mode from edid */
+ if (!dvi->update)
+ return -EINVAL;
+ else {
+ bool found = false;
+
+ INIT_LIST_HEAD(&dvi->fbi->modelist);
+ if (dvi->update()) {
+ dvi->cable_plugin = 1;
+ /* try to read edid */
+ if (mxc_edid_read(dvi->client->adapter, dvi->client->addr,
+ dvi->edid, &dvi->edid_cfg, dvi->fbi) < 0)
+ dev_warn(&dvi->client->dev, "Can not read edid\n");
+ else if (dvi->fbi->monspecs.modedb_len > 0) {
+ int i;
+ const struct fb_videomode *mode;
+ struct fb_videomode m;
+
+ for (i = 0; i < dvi->fbi->monspecs.modedb_len; i++) {
+ /*FIXME now we do not support interlaced mode */
+ if (!(dvi->fbi->monspecs.modedb[i].vmode
+ & FB_VMODE_INTERLACED))
+ fb_add_videomode(
+ &dvi->fbi->monspecs.modedb[i],
+ &dvi->fbi->modelist);
+ }
+
+ fb_find_mode(&dvi->fbi->var, dvi->fbi, setting->dft_mode_str,
+ NULL, 0, NULL, setting->default_bpp);
+
+ fb_var_to_videomode(&m, &dvi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &dvi->fbi->modelist);
+ fb_videomode_to_var(&dvi->fbi->var, mode);
+ found = 1;
+ }
+ } else
+ dvi->cable_plugin = 0;
+
+ if (!found) {
+ ret = fb_find_mode(&dvi->fbi->var, dvi->fbi, setting->dft_mode_str,
+ NULL, 0, NULL, setting->default_bpp);
+ if (!ret)
+ return -EINVAL;
+ }
+ }
+
+ /* cable detection */
+ if (dvi->client->irq) {
+ ret = request_irq(dvi->client->irq, mxc_dvi_detect_handler,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "dvi_det", dvi);
+ if (ret < 0) {
+ dev_warn(&dvi->client->dev,
+ "MXC dvi: cound not request det irq %d\n",
+ dvi->client->irq);
+ goto err;
+ } else {
+ INIT_DELAYED_WORK(&(dvi->det_work), det_worker);
+ ret = device_create_file(&dvi->pdev->dev, &dev_attr_fb_name);
+ if (ret < 0)
+ dev_warn(&dvi->client->dev,
+ "MXC dvi: cound not create sys node for fb name\n");
+ ret = device_create_file(&dvi->pdev->dev, &dev_attr_cable_state);
+ if (ret < 0)
+ dev_warn(&dvi->client->dev,
+ "MXC dvi: cound not create sys node for cable state\n");
+ ret = device_create_file(&dvi->pdev->dev, &dev_attr_edid);
+ if (ret < 0)
+ dev_warn(&dvi->client->dev,
+ "MXC dvi: cound not create sys node for edid\n");
+
+ dev_set_drvdata(&dvi->pdev->dev, dvi);
+ }
+ }
+
+err:
+ return ret;
+}
+
+static void dvi_deinit(struct mxc_dispdrv_entry *disp)
+{
+ struct mxc_dvi_data *dvi = mxc_dispdrv_getdata(disp);
+
+ if (!IS_ERR(dvi->analog_reg))
+ regulator_disable(dvi->analog_reg);
+
+ free_irq(dvi->client->irq, dvi);
+}
+
+static struct mxc_dispdrv_driver dvi_drv = {
+ .name = DISPDRV_DVI,
+ .init = dvi_init,
+ .deinit = dvi_deinit,
+};
+
+static int __devinit mxc_dvi_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct mxc_dvi_data *dvi;
+ int ret = 0;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
+ return -ENODEV;
+
+ dvi = kzalloc(sizeof(struct mxc_dvi_data), GFP_KERNEL);
+ if (!dvi) {
+ ret = -ENOMEM;
+ goto alloc_failed;
+ }
+
+ dvi->pdev = platform_device_register_simple("mxc_dvi", 0, NULL, 0);
+ if (IS_ERR(dvi->pdev)) {
+ printk(KERN_ERR
+ "Unable to register MXC DVI as a platform device\n");
+ ret = PTR_ERR(dvi->pdev);
+ goto pdev_reg_failed;
+ }
+
+ dvi->client = client;
+ dvi->disp_dvi = mxc_dispdrv_register(&dvi_drv);
+ mxc_dispdrv_setdata(dvi->disp_dvi, dvi);
+
+ i2c_set_clientdata(client, dvi);
+
+ return ret;
+
+pdev_reg_failed:
+ kfree(dvi);
+alloc_failed:
+ return ret;
+}
+
+static int __devexit mxc_dvi_remove(struct i2c_client *client)
+{
+ struct mxc_dvi_data *dvi = i2c_get_clientdata(client);
+
+ mxc_dispdrv_unregister(dvi->disp_dvi);
+ platform_device_unregister(dvi->pdev);
+ kfree(dvi);
+ return 0;
+}
+
+static const struct i2c_device_id mxc_dvi_id[] = {
+ { "mxc_dvi", 0 },
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, mxc_dvi_id);
+
+static struct i2c_driver mxc_dvi_i2c_driver = {
+ .driver = {
+ .name = "mxc_dvi",
+ },
+ .probe = mxc_dvi_probe,
+ .remove = mxc_dvi_remove,
+ .id_table = mxc_dvi_id,
+};
+
+static int __init mxc_dvi_init(void)
+{
+ return i2c_add_driver(&mxc_dvi_i2c_driver);
+}
+
+static void __exit mxc_dvi_exit(void)
+{
+ i2c_del_driver(&mxc_dvi_i2c_driver);
+}
+
+module_init(mxc_dvi_init);
+module_exit(mxc_dvi_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MXC DVI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/mxc/mxc_edid.c b/drivers/video/mxc/mxc_edid.c
index 0fa5cf97602..85a9063037a 100644
--- a/drivers/video/mxc/mxc_edid.c
+++ b/drivers/video/mxc/mxc_edid.c
@@ -29,7 +29,7 @@
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/fb.h>
-#include "mxc_edid.h"
+#include <mach/mxc_edid.h>
#include "../edid.h"
#undef DEBUG /* define this for verbose EDID parsing output */
@@ -41,80 +41,120 @@
#endif
const struct fb_videomode mxc_cea_mode[64] = {
- /* #1: 640x480p@59.94/60Hz */
+ /* #1: 640x480p@59.94/60Hz 4:3 */
[1] = {
NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
},
- /* #3: 720x480p@59.94/60Hz */
+ /* #2: 720x480p@59.94/60Hz 4:3 */
+ [2] = {
+ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
+ },
+ /* #3: 720x480p@59.94/60Hz 16:9 */
[3] = {
NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
- /* #4: 1280x720p@59.94/60Hz */
+ /* #4: 1280x720p@59.94/60Hz 16:9 */
[4] = {
NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
},
- /* #5: 1920x1080i@59.94/60Hz */
+ /* #5: 1920x1080i@59.94/60Hz 16:9 */
[5] = {
NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_INTERLACED, 0,
+ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
+ },
+ /* #6: 720(1440)x480iH@59.94/60Hz 4:3 */
+ [6] = {
+ NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
+ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
},
- /* #7: 720(1440)x480iH@59.94/60Hz */
+ /* #7: 720(1440)x480iH@59.94/60Hz 16:9 */
[7] = {
NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
- FB_VMODE_INTERLACED, 0,
+ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
- /* #9: 720(1440)x240pH@59.94/60Hz */
+ /* #8: 720(1440)x240pH@59.94/60Hz 4:3 */
+ [8] = {
+ NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
+ },
+ /* #9: 720(1440)x240pH@59.94/60Hz 16:9 */
[9] = {
NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
- /* #16: 1920x1080p@60Hz */
+ /* #16: 1920x1080p@60Hz 16:9 */
[16] = {
NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
+ },
+ /* #17: 720x576pH@50Hz 4:3 */
+ [17] = {
+ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
},
- /* #18: 720x576pH@50Hz */
+ /* #18: 720x576pH@50Hz 16:9 */
[18] = {
NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
/* #19: 1280x720p@50Hz */
[19] = {
NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
/* #20: 1920x1080i@50Hz */
[20] = {
NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_INTERLACED, 0,
+ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
/* #31: 1920x1080p@50Hz */
[31] = {
NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
/* #32: 1920x1080p@23.98/24Hz */
[32] = {
NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
},
/* #35: (2880)x480p4x@59.94/60Hz */
[35] = {
NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0,
- FB_VMODE_NONINTERLACED, 0,
+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
},
};
+/*
+ * We have a special version of fb_mode_is_equal that ignores
+ * pixclock, since for many CEA modes, 2 frequencies are supported
+ * e.g. 640x480 @ 60Hz or 59.94Hz
+ */
+int mxc_edid_fb_mode_is_equal(const struct fb_videomode *mode1,
+ const struct fb_videomode *mode2)
+{
+ return (mode1->xres == mode2->xres &&
+ mode1->yres == mode2->yres &&
+ mode1->hsync_len == mode2->hsync_len &&
+ mode1->vsync_len == mode2->vsync_len &&
+ mode1->left_margin == mode2->left_margin &&
+ mode1->right_margin == mode2->right_margin &&
+ mode1->upper_margin == mode2->upper_margin &&
+ mode1->lower_margin == mode2->lower_margin &&
+ mode1->sync == mode2->sync &&
+ mode1->vmode == mode2->vmode);
+}
+
static void get_detailed_timing(unsigned char *block,
struct fb_videomode *mode)
{
@@ -399,7 +439,7 @@ int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
fb_var_to_videomode(&m, var);
- if (fb_mode_is_equal(&m, &mxc_cea_mode[i]))
+ if (mxc_edid_fb_mode_is_equal(&m, &mxc_cea_mode[i]))
break;
}
@@ -408,8 +448,25 @@ int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
return i;
}
+
EXPORT_SYMBOL(mxc_edid_var_to_vic);
+int mxc_edid_mode_to_vic(const struct fb_videomode *mode)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
+ if (mxc_edid_fb_mode_is_equal(mode, &mxc_cea_mode[i]))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(mxc_cea_mode))
+ return 0;
+
+ return i;
+}
+EXPORT_SYMBOL(mxc_edid_mode_to_vic);
+
/* make sure edid has 512 bytes*/
int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi)
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c
index 260b41a3ddf..1447c455202 100644
--- a/drivers/video/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc/mxc_ipuv3_fb.c
@@ -91,6 +91,8 @@ struct mxcfb_info {
void *ipu;
struct fb_info *ovfbi;
+
+ struct ipuv3_fb_platform_data of_data;
};
struct mxcfb_alloc_list {
@@ -109,6 +111,7 @@ enum {
static bool g_dp_in_use[2];
LIST_HEAD(fb_alloc_list);
+static int of_dev_id;
static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
{
@@ -131,6 +134,38 @@ static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
return pixfmt;
}
+static int if_fmt_parse(const char *fmt)
+{
+ int if_fmt;
+
+ if (!strncmp(fmt, "RGB24", 5))
+ if_fmt = IPU_PIX_FMT_RGB24;
+ else if (!strncmp(fmt, "BGR24", 5))
+ if_fmt = IPU_PIX_FMT_BGR24;
+ else if (!strncmp(fmt, "GBR24", 5))
+ if_fmt = IPU_PIX_FMT_GBR24;
+ else if (!strncmp(fmt, "RGB565", 6))
+ if_fmt = IPU_PIX_FMT_RGB565;
+ else if (!strncmp(fmt, "RGB666", 6))
+ if_fmt = IPU_PIX_FMT_RGB666;
+ else if (!strncmp(fmt, "YUV444", 6))
+ if_fmt = IPU_PIX_FMT_YUV444;
+ else if (!strncmp(fmt, "LVDS666", 7))
+ if_fmt = IPU_PIX_FMT_LVDS666;
+ else if (!strncmp(fmt, "YUYV16", 6))
+ if_fmt = IPU_PIX_FMT_YUYV;
+ else if (!strncmp(fmt, "UYVY16", 6))
+ if_fmt = IPU_PIX_FMT_UYVY;
+ else if (!strncmp(fmt, "YVYU16", 6))
+ if_fmt = IPU_PIX_FMT_YVYU;
+ else if (!strncmp(fmt, "VYUY16", 6))
+ if_fmt = IPU_PIX_FMT_VYUY;
+ else
+ if_fmt = IPU_PIX_FMT_RGB24;
+
+ return if_fmt;
+}
+
static struct fb_info *found_registered_fb(ipu_channel_t ipu_ch, int ipu_id)
{
int i;
@@ -1233,7 +1268,8 @@ mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
down(&mxc_fbi->flip_sem);
- mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
+ mxc_fbi->cur_ipu_buf++;
+ mxc_fbi->cur_ipu_buf %= 3;
mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
@@ -1280,8 +1316,10 @@ mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
IPU_INPUT_BUFFER, 1),
ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
IPU_INPUT_BUFFER, 2));
- mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
- mxc_fbi->cur_ipu_buf = (++mxc_fbi->cur_ipu_buf) % 3;
+ mxc_fbi->cur_ipu_buf++;
+ mxc_fbi->cur_ipu_buf %= 3;
+ mxc_fbi->cur_ipu_buf++;
+ mxc_fbi->cur_ipu_buf %= 3;
mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
@@ -1672,49 +1710,8 @@ static int mxcfb_option_setup(struct platform_device *pdev)
continue;
}
if (!strncmp(opt, "if=", 3)) {
- if (!strncmp(opt+3, "RGB24", 5)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_RGB24;
- continue;
- } else if (!strncmp(opt+6, "BGR24", 5)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_BGR24;
- continue;
- }
- if (!strncmp(opt+3, "GBR24", 5)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_GBR24;
- continue;
- }
- if (!strncmp(opt+3, "RGB565", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_RGB565;
- continue;
- }
- if (!strncmp(opt+3, "RGB666", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_RGB666;
- continue;
- }
- if (!strncmp(opt+3, "YUV444", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_YUV444;
- continue;
- }
- if (!strncmp(opt+3, "LVDS666", 7)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
- continue;
- }
- if (!strncmp(opt+3, "YUYV16", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_YUYV;
- continue;
- }
- if (!strncmp(opt+3, "UYVY16", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_UYVY;
- continue;
- }
- if (!strncmp(opt+3, "YVYU16", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_YVYU;
- continue;
- }
- if (!strncmp(opt+3, "VYUY16", 6)) {
- pdata->interface_pix_fmt = IPU_PIX_FMT_VYUY;
- continue;
- }
+ pdata->interface_pix_fmt = if_fmt_parse(opt+3);
+ continue;
}
if (!strncmp(opt, "int_clk", 7)) {
pdata->int_clk = true;
@@ -1727,8 +1724,10 @@ static int mxcfb_option_setup(struct platform_device *pdev)
fb_mode_str = opt;
}
- if (fb_mode_str)
- pdata->mode_str = fb_mode_str;
+ if (fb_mode_str) {
+ memcpy(pdata->mode_str, fb_mode_str, strlen(fb_mode_str));
+ pdata->mode_str[strlen(fb_mode_str)] = '\0';
+ }
return 0;
}
@@ -1787,8 +1786,6 @@ static int mxcfb_register(struct fb_info *fbi)
ret = fb_set_var(fbi, &fbi->var);
fbi->flags &= ~FBINFO_MISC_USEREVENT;
console_unlock();
- if (ret < 0)
- goto err2;
if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
console_lock();
@@ -1898,6 +1895,54 @@ static void ipu_clear_usage(int ipu, int di)
ipu_usage[ipu][di] = false;
}
+static int of_get_fb_data(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
+ const char *disp_dev, *if_fmt, *mode_str, *int_clk;
+ const char *default_dev = "lcd";
+ const char *default_mode_str = "800x480M@55";
+ int ret;
+
+ if (!np)
+ return -EINVAL;
+
+ pdev->id = of_dev_id;
+ of_dev_id++;
+
+ plat_data->default_bpp = 16;
+
+ ret = of_property_read_string(np, "disp_dev", &disp_dev);
+ if (ret < 0)
+ memcpy(plat_data->disp_dev, default_dev, strlen(default_dev));
+ else
+ memcpy(plat_data->disp_dev, disp_dev, strlen(disp_dev));
+
+ ret = of_property_read_string(np, "interface_pix_fmt", &if_fmt);
+ if (ret < 0)
+ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB24;
+ else
+ plat_data->interface_pix_fmt = if_fmt_parse(if_fmt);
+
+ ret = of_property_read_string(np, "mode_str", &mode_str);
+ if (ret < 0)
+ memcpy(plat_data->mode_str, default_mode_str, strlen(default_mode_str));
+ else
+ memcpy(plat_data->mode_str, mode_str, strlen(mode_str));
+
+ ret = of_property_read_string(np, "internal_clk", &int_clk);
+ if (ret < 0)
+ plat_data->int_clk = false;
+ else {
+ if (!strcmp(int_clk, "true"))
+ plat_data->int_clk = true;
+ else
+ plat_data->int_clk = false;
+ }
+
+ return 0;
+}
+
/*!
* Probe routine for the framebuffer driver. It is called during the
* driver binding process. The following functions are performed in
@@ -1923,9 +1968,18 @@ static int mxcfb_probe(struct platform_device *pdev)
goto init_fbinfo_failed;
}
+ mxcfbi = (struct mxcfb_info *)fbi->par;
+
+ if (!plat_data) {
+ plat_data = pdev->dev.platform_data = &mxcfbi->of_data;
+ if (of_get_fb_data(pdev) < 0) {
+ dev_err(&pdev->dev, "no platform data\n");
+ goto platform_data_err;
+ }
+ }
+
mxcfb_option_setup(pdev);
- mxcfbi = (struct mxcfb_info *)fbi->par;
mxcfbi->ipu_int_clk = plat_data->int_clk;
ret = mxcfb_dispdrv_init(pdev, fbi);
if (ret < 0)
@@ -2002,6 +2056,7 @@ get_ipu_failed:
ipu_clear_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
ipu_in_busy:
init_dispdrv_failed:
+platform_data_err:
fb_dealloc_cmap(&fbi->cmap);
framebuffer_release(fbi);
init_fbinfo_failed:
@@ -2033,12 +2088,18 @@ static int mxcfb_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id mxcfb_ipuv3_dt_ids[] = {
+ { .compatible = "fsl,mxcfb-ipuv3", },
+ { /* sentinel */ }
+};
+
/*!
* This structure contains pointers to the power management callback functions.
*/
static struct platform_driver mxcfb_driver = {
.driver = {
.name = MXCFB_NAME,
+ .of_match_table = mxcfb_ipuv3_dt_ids,
},
.probe = mxcfb_probe,
.remove = mxcfb_remove,
diff --git a/drivers/video/mxc/mxcfb_sii902x.c b/drivers/video/mxc/mxcfb_sii902x.c
index 17ce8fca68b..f626f649f9c 100644
--- a/drivers/video/mxc/mxcfb_sii902x.c
+++ b/drivers/video/mxc/mxcfb_sii902x.c
@@ -50,7 +50,7 @@
#include <linux/uaccess.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
-#include "mxc_edid.h"
+#include <mach/mxc_edid.h>
#include "mxc_dispdrv.h"
#define DISPDRV_SII "hdmi"
@@ -671,7 +671,11 @@ static void sii902x_setup(struct sii902x_data *sii902x, struct fb_info *fbi)
/* reg 0x0a: set output format to RGB */
sii902x->tpivmode[2] = 0x00;
- if (fbi->var.xres/16 == fbi->var.yres/9)
+ if (fbi->var.vmode & FB_VMODE_ASPECT_16_9)
+ sii902x->aspect_ratio = VMD_ASPECT_RATIO_16x9;
+ else if (fbi->var.vmode & FB_VMODE_ASPECT_4_3)
+ sii902x->aspect_ratio = VMD_ASPECT_RATIO_4x3;
+ else if (fbi->var.xres/16 == fbi->var.yres/9)
sii902x->aspect_ratio = VMD_ASPECT_RATIO_16x9;
else
sii902x->aspect_ratio = VMD_ASPECT_RATIO_4x3;
diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c
index 35b100349fe..98b506d3730 100644
--- a/drivers/video/mxc/tve.c
+++ b/drivers/video/mxc/tve.c
@@ -38,7 +38,6 @@
#include <linux/uaccess.h>
#include <asm/atomic.h>
#include <mach/hardware.h>
-#include <mach/ipu-v3.h>
#include "mxc_dispdrv.h"
#define TVE_ENABLE (1UL)
@@ -1105,6 +1104,18 @@ static int tve_drv_init(struct mxc_dispdrv_entry *disp, bool vga)
tve->reg_fields = &tve_reg_fields_v2;
}
+ /* adjust video mode for mx37 */
+ if (cpu_is_mx37()) {
+ video_modes_tve[0].left_margin = 121;
+ video_modes_tve[0].right_margin = 16;
+ video_modes_tve[0].upper_margin = 17;
+ video_modes_tve[0].lower_margin = 5;
+ video_modes_tve[1].left_margin = 131;
+ video_modes_tve[1].right_margin = 12;
+ video_modes_tve[1].upper_margin = 21;
+ video_modes_tve[1].lower_margin = 3;
+ }
+
if (vga && cpu_is_mx53()) {
setting->if_fmt = IPU_PIX_FMT_GBR24;
modedb = video_modes_vga;
diff --git a/drivers/video/mxc_hdmi.c b/drivers/video/mxc_hdmi.c
new file mode 100644
index 00000000000..924264c32e2
--- /dev/null
+++ b/drivers/video/mxc_hdmi.c
@@ -0,0 +1,1975 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+/*
+ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
+ * for SLISHDMI13T and SLIPHDMIT IP cores
+ *
+ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <mach/clock.h>
+#include <linux/uaccess.h>
+#include <linux/cpufreq.h>
+#include <linux/firmware.h>
+#include <linux/kthread.h>
+#include <linux/regulator/driver.h>
+#include <linux/fsl_devices.h>
+#include <linux/ipu.h>
+
+#include <linux/console.h>
+#include <linux/types.h>
+
+#include <mach/mxc_edid.h>
+#include "mxc/mxc_dispdrv.h"
+
+#include <linux/mfd/mxc-hdmi-core.h>
+#include <mach/mxc_hdmi.h>
+
+#define DISPDRV_HDMI "hdmi"
+#define HDMI_EDID_LEN 512
+
+#define TRUE 1
+#define FALSE 0
+
+#define NUM_CEA_VIDEO_MODES 64
+#define DEFAULT_VIDEO_MODE 16 /* 1080P */
+
+#define RGB 0
+#define YCBCR444 1
+#define YCBCR422_16BITS 2
+#define YCBCR422_8BITS 3
+#define XVYCC444 4
+
+enum hdmi_datamap {
+ RGB444_8B = 0x01,
+ RGB444_10B = 0x03,
+ RGB444_12B = 0x05,
+ RGB444_16B = 0x07,
+ YCbCr444_8B = 0x09,
+ YCbCr444_10B = 0x0B,
+ YCbCr444_12B = 0x0D,
+ YCbCr444_16B = 0x0F,
+ YCbCr422_8B = 0x16,
+ YCbCr422_10B = 0x14,
+ YCbCr422_12B = 0x12,
+};
+
+enum hdmi_colorimetry {
+ eITU601,
+ eITU709,
+};
+
+struct hdmi_vmode {
+ unsigned int mHdmiDviSel;
+ unsigned int mHSyncPolarity;
+ unsigned int mVSyncPolarity;
+ unsigned int mInterlaced;
+ unsigned int mDataEnablePolarity;
+ unsigned int mPixelClock;
+ unsigned int mPixelRepetitionInput;
+ unsigned int mPixelRepetitionOutput;
+};
+
+struct hdmi_data_info {
+ unsigned int enc_in_format;
+ unsigned int enc_out_format;
+ unsigned int enc_color_depth;
+ unsigned int colorimetry;
+ unsigned int pix_repet_factor;
+ unsigned int hdcp_enable;
+ struct hdmi_vmode video_mode;
+};
+
+struct mxc_hdmi {
+ struct platform_device *pdev;
+ struct platform_device *core_pdev;
+ struct mxc_dispdrv_entry *disp_mxc_hdmi;
+ struct fb_info *fbi;
+ struct clk *hdmi_isfr_clk;
+ struct clk *hdmi_iahb_clk;
+ struct delayed_work det_work;
+ struct notifier_block nb;
+
+ struct hdmi_data_info hdmi_data;
+ int vic;
+ struct mxc_edid_cfg edid_cfg;
+ u8 edid[HDMI_EDID_LEN];
+ bool fb_reg;
+ bool need_mode_change;
+ bool cable_plugin;
+ u8 latest_intr_stat;
+ bool irq_enabled;
+ spinlock_t irq_lock;
+};
+
+struct i2c_client *hdmi_i2c;
+
+extern const struct fb_videomode mxc_cea_mode[64];
+
+/*!
+ * this submodule is responsible for the video data synchronization.
+ * for example, for RGB 4:4:4 input, the data map is defined as
+ * pin{47~40} <==> R[7:0]
+ * pin{31~24} <==> G[7:0]
+ * pin{15~8} <==> B[7:0]
+ */
+void hdmi_video_sample(struct mxc_hdmi *hdmi)
+{
+ int color_format = 0;
+ u8 val;
+
+ if (hdmi->hdmi_data.enc_in_format == RGB) {
+ if (hdmi->hdmi_data.enc_color_depth == 8)
+ color_format = 0x01;
+ else if (hdmi->hdmi_data.enc_color_depth == 10)
+ color_format = 0x03;
+ else if (hdmi->hdmi_data.enc_color_depth == 12)
+ color_format = 0x05;
+ else if (hdmi->hdmi_data.enc_color_depth == 16)
+ color_format = 0x07;
+ else
+ return;
+ } else if (hdmi->hdmi_data.enc_in_format == XVYCC444) {
+ if (hdmi->hdmi_data.enc_color_depth == 8)
+ color_format = 0x09;
+ else if (hdmi->hdmi_data.enc_color_depth == 10)
+ color_format = 0x0B;
+ else if (hdmi->hdmi_data.enc_color_depth == 12)
+ color_format = 0x0D;
+ else if (hdmi->hdmi_data.enc_color_depth == 16)
+ color_format = 0x0F;
+ else
+ return;
+ } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
+ if (hdmi->hdmi_data.enc_color_depth == 8)
+ color_format = 0x16;
+ else if (hdmi->hdmi_data.enc_color_depth == 10)
+ color_format = 0x14;
+ else if (hdmi->hdmi_data.enc_color_depth == 12)
+ color_format = 0x12;
+ else
+ return;
+ }
+
+ val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
+ ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
+ HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
+ hdmi_writeb(val, HDMI_TX_INVID0);
+
+ /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
+ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
+ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
+ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
+ hdmi_writeb(val, HDMI_TX_INSTUFFING);
+ hdmi_writeb(0x0, HDMI_TX_GYDATA0);
+ hdmi_writeb(0x0, HDMI_TX_GYDATA1);
+ hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
+ hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
+ hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
+ hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
+}
+
+static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
+{
+ return (hdmi->hdmi_data.enc_in_format !=
+ hdmi->hdmi_data.enc_out_format) ? TRUE : FALSE;
+}
+
+static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
+{
+ return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
+ (hdmi->hdmi_data.enc_in_format == RGB ||
+ hdmi->hdmi_data.enc_in_format == XVYCC444)) ? TRUE : FALSE;
+}
+
+static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
+{
+ return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
+ (hdmi->hdmi_data.enc_out_format == RGB
+ || hdmi->hdmi_data.enc_out_format == XVYCC444)) ?
+ TRUE : FALSE;
+}
+
+/*!
+ * update the color space conversion coefficients.
+ */
+void update_csc_coeffs(struct mxc_hdmi *hdmi)
+{
+ unsigned short csc_coeff[3][4];
+ unsigned int csc_scale = 1;
+ u8 val;
+ bool coeff_selected = false;
+
+ if (isColorSpaceConversion(hdmi)) { /* csc needed */
+ if (hdmi->hdmi_data.enc_out_format == RGB) {
+ if (hdmi->hdmi_data.colorimetry == eITU601) {
+ csc_coeff[0][0] = 0x2000;
+ csc_coeff[0][1] = 0x6926;
+ csc_coeff[0][2] = 0x74fd;
+ csc_coeff[0][3] = 0x010e;
+
+ csc_coeff[1][0] = 0x2000;
+ csc_coeff[1][1] = 0x2cdd;
+ csc_coeff[1][2] = 0x0000;
+ csc_coeff[1][3] = 0x7e9a;
+
+ csc_coeff[2][0] = 0x2000;
+ csc_coeff[2][1] = 0x0000;
+ csc_coeff[2][2] = 0x38b4;
+ csc_coeff[2][3] = 0x7e3b;
+
+ csc_scale = 1;
+ coeff_selected = true;
+ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
+ csc_coeff[0][0] = 0x2000;
+ csc_coeff[0][1] = 0x7106;
+ csc_coeff[0][2] = 0x7a02;
+ csc_coeff[0][3] = 0x00a7;
+
+ csc_coeff[1][0] = 0x2000;
+ csc_coeff[1][1] = 0x3264;
+ csc_coeff[1][2] = 0x0000;
+ csc_coeff[1][3] = 0x7e6d;
+
+ csc_coeff[2][0] = 0x2000;
+ csc_coeff[2][1] = 0x0000;
+ csc_coeff[2][2] = 0x3b61;
+ csc_coeff[2][3] = 0x7e25;
+
+ csc_scale = 1;
+ coeff_selected = true;
+ }
+ } else if (hdmi->hdmi_data.enc_in_format == RGB) {
+ if (hdmi->hdmi_data.colorimetry == eITU601) {
+ csc_coeff[0][0] = 0x2591;
+ csc_coeff[0][1] = 0x1322;
+ csc_coeff[0][2] = 0x074b;
+ csc_coeff[0][3] = 0x0000;
+
+ csc_coeff[1][0] = 0x6535;
+ csc_coeff[1][1] = 0x2000;
+ csc_coeff[1][2] = 0x7acc;
+ csc_coeff[1][3] = 0x0200;
+
+ csc_coeff[2][0] = 0x6acd;
+ csc_coeff[2][1] = 0x7534;
+ csc_coeff[2][2] = 0x2000;
+ csc_coeff[2][3] = 0x0200;
+
+ csc_scale = 0;
+ coeff_selected = true;
+ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
+ csc_coeff[0][0] = 0x2dc5;
+ csc_coeff[0][1] = 0x0d9b;
+ csc_coeff[0][2] = 0x049e;
+ csc_coeff[0][3] = 0x0000;
+
+ csc_coeff[1][0] = 0x62f0;
+ csc_coeff[1][1] = 0x2000;
+ csc_coeff[1][2] = 0x7d11;
+ csc_coeff[1][3] = 0x0200;
+
+ csc_coeff[2][0] = 0x6756;
+ csc_coeff[2][1] = 0x78ab;
+ csc_coeff[2][2] = 0x2000;
+ csc_coeff[2][3] = 0x0200;
+
+ csc_scale = 0;
+ coeff_selected = true;
+ }
+ }
+ }
+
+ if (!coeff_selected) {
+ csc_coeff[0][0] = 0x2000;
+ csc_coeff[0][1] = 0x0000;
+ csc_coeff[0][2] = 0x0000;
+ csc_coeff[0][3] = 0x0000;
+
+ csc_coeff[1][0] = 0x0000;
+ csc_coeff[1][1] = 0x2000;
+ csc_coeff[1][2] = 0x0000;
+ csc_coeff[1][3] = 0x0000;
+
+ csc_coeff[2][0] = 0x0000;
+ csc_coeff[2][1] = 0x0000;
+ csc_coeff[2][2] = 0x2000;
+ csc_coeff[2][3] = 0x0000;
+
+ csc_scale = 1;
+ }
+
+ /* Update CSC parameters in HDMI CSC registers */
+ hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
+ HDMI_CSC_COEF_A1_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
+ HDMI_CSC_COEF_A1_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
+ HDMI_CSC_COEF_A2_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
+ HDMI_CSC_COEF_A2_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
+ HDMI_CSC_COEF_A3_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
+ HDMI_CSC_COEF_A3_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
+ HDMI_CSC_COEF_A4_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
+ HDMI_CSC_COEF_A4_MSB);
+
+ hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
+ HDMI_CSC_COEF_B1_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
+ HDMI_CSC_COEF_B1_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
+ HDMI_CSC_COEF_B2_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
+ HDMI_CSC_COEF_B2_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
+ HDMI_CSC_COEF_B3_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
+ HDMI_CSC_COEF_B3_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
+ HDMI_CSC_COEF_B4_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
+ HDMI_CSC_COEF_B4_MSB);
+
+ hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
+ HDMI_CSC_COEF_C1_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
+ HDMI_CSC_COEF_C1_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
+ HDMI_CSC_COEF_C2_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
+ HDMI_CSC_COEF_C2_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
+ HDMI_CSC_COEF_C3_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
+ HDMI_CSC_COEF_C3_MSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
+ HDMI_CSC_COEF_C4_LSB);
+ hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
+ HDMI_CSC_COEF_C4_MSB);
+
+ val = hdmi_readb(HDMI_CSC_SCALE);
+ val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
+ val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
+ hdmi_writeb(val, HDMI_CSC_SCALE);
+}
+
+void hdmi_video_csc(struct mxc_hdmi *hdmi)
+{
+ int color_depth = 0;
+ int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
+ int decimation = 0;
+ u8 val;
+
+ /* YCC422 interpolation to 444 mode */
+ if (isColorSpaceInterpolation(hdmi))
+ interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
+ else if (isColorSpaceDecimation(hdmi))
+ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1;
+
+ if (hdmi->hdmi_data.enc_color_depth == 8)
+ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
+ else if (hdmi->hdmi_data.enc_color_depth == 10)
+ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
+ else if (hdmi->hdmi_data.enc_color_depth == 12)
+ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
+ else if (hdmi->hdmi_data.enc_color_depth == 16)
+ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
+ else
+ return;
+
+ /*configure the CSC registers */
+ hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
+ val = hdmi_readb(HDMI_CSC_SCALE);
+ val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
+ val |= color_depth;
+ hdmi_writeb(val, HDMI_CSC_SCALE);
+
+ update_csc_coeffs(hdmi);
+}
+
+/*!
+ * HDMI video packetizer is used to packetize the data.
+ * for example, if input is YCC422 mode or repeater is used,
+ * data should be repacked this module can be bypassed.
+ */
+void hdmi_video_packetize(struct mxc_hdmi *hdmi)
+{
+ unsigned int color_depth = 0;
+ unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
+ unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
+ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
+ u8 val;
+
+ if (hdmi_data->enc_out_format == RGB
+ || hdmi_data->enc_out_format == YCBCR444) {
+ if (hdmi_data->enc_color_depth == 0)
+ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+ else if (hdmi_data->enc_color_depth == 8) {
+ color_depth = 4;
+ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+ } else if (hdmi_data->enc_color_depth == 10)
+ color_depth = 5;
+ else if (hdmi_data->enc_color_depth == 12)
+ color_depth = 6;
+ else if (hdmi_data->enc_color_depth == 16)
+ color_depth = 7;
+ else
+ return;
+ } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
+ if (hdmi_data->enc_color_depth == 0 ||
+ hdmi_data->enc_color_depth == 8)
+ remap_size = HDMI_VP_REMAP_YCC422_16bit;
+ else if (hdmi_data->enc_color_depth == 10)
+ remap_size = HDMI_VP_REMAP_YCC422_20bit;
+ else if (hdmi_data->enc_color_depth == 12)
+ remap_size = HDMI_VP_REMAP_YCC422_24bit;
+ else
+ return;
+ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
+ } else
+ return;
+
+ /* set the packetizer registers */
+ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+ HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+ ((hdmi_data->pix_repet_factor <<
+ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+ hdmi_writeb(val, HDMI_VP_PR_CD);
+
+ val = hdmi_readb(HDMI_VP_STUFF);
+ val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
+ val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
+ hdmi_writeb(val, HDMI_VP_STUFF);
+
+ /* Data from pixel repeater block */
+ if (hdmi_data->pix_repet_factor > 1) {
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
+ HDMI_VP_CONF_BYPASS_SELECT_MASK);
+ val |= HDMI_VP_CONF_PR_EN_ENABLE |
+ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
+ hdmi_writeb(val, HDMI_VP_CONF);
+ } else { /* data from packetizer block */
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
+ HDMI_VP_CONF_BYPASS_SELECT_MASK);
+ val |= HDMI_VP_CONF_PR_EN_DISABLE |
+ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
+ hdmi_writeb(val, HDMI_VP_CONF);
+ }
+
+ val = hdmi_readb(HDMI_VP_STUFF);
+ val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
+ val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
+ hdmi_writeb(val, HDMI_VP_STUFF);
+
+ hdmi_writeb(remap_size, HDMI_VP_REMAP);
+
+ if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
+ HDMI_VP_CONF_PP_EN_ENMASK |
+ HDMI_VP_CONF_YCC422_EN_MASK);
+ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
+ HDMI_VP_CONF_PP_EN_ENABLE |
+ HDMI_VP_CONF_YCC422_EN_DISABLE;
+ hdmi_writeb(val, HDMI_VP_CONF);
+ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
+ HDMI_VP_CONF_PP_EN_ENMASK |
+ HDMI_VP_CONF_YCC422_EN_MASK);
+ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
+ HDMI_VP_CONF_PP_EN_DISABLE |
+ HDMI_VP_CONF_YCC422_EN_ENABLE;
+ hdmi_writeb(val, HDMI_VP_CONF);
+ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
+ HDMI_VP_CONF_PP_EN_ENMASK |
+ HDMI_VP_CONF_YCC422_EN_MASK);
+ val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
+ HDMI_VP_CONF_PP_EN_DISABLE |
+ HDMI_VP_CONF_YCC422_EN_DISABLE;
+ hdmi_writeb(val, HDMI_VP_CONF);
+ } else {
+ return;
+ }
+
+ val = hdmi_readb(HDMI_VP_STUFF);
+ val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
+ HDMI_VP_STUFF_YCC422_STUFFING_MASK);
+ val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
+ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
+ hdmi_writeb(val, HDMI_VP_STUFF);
+
+ val = hdmi_readb(HDMI_VP_CONF);
+ val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
+ val |= output_select;
+ hdmi_writeb(val, HDMI_VP_CONF);
+}
+
+void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
+{
+ u8 val;
+
+ if (force == TRUE) {
+ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
+ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
+ hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0); /* B */
+ val = hdmi_readb(HDMI_FC_DBGFORCE);
+ val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
+ hdmi_writeb(val, HDMI_FC_DBGFORCE);
+ } else {
+ val = hdmi_readb(HDMI_FC_DBGFORCE);
+ val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
+ hdmi_writeb(val, HDMI_FC_DBGFORCE);
+ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
+ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
+ hdmi_writeb(0x00, HDMI_FC_DBGTMDS0); /* B */
+ }
+}
+
+static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
+ unsigned char bit)
+{
+ u8 val = hdmi_readb(HDMI_PHY_TST0);
+ val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
+ val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
+ HDMI_PHY_TST0_TSTCLR_MASK;
+ hdmi_writeb(val, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
+ unsigned char bit)
+{
+ u8 val = hdmi_readb(HDMI_PHY_TST0);
+ val &= ~HDMI_PHY_TST0_TSTEN_MASK;
+ val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
+ HDMI_PHY_TST0_TSTEN_MASK;
+ hdmi_writeb(val, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
+ unsigned char bit)
+{
+ u8 val = hdmi_readb(HDMI_PHY_TST0);
+ val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
+ val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
+ HDMI_PHY_TST0_TSTCLK_MASK;
+ hdmi_writeb(val, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
+ unsigned char bit)
+{
+ hdmi_writeb(bit, HDMI_PHY_TST1);
+}
+
+static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
+ unsigned char bit)
+{
+ hdmi_writeb(bit, HDMI_PHY_TST2);
+}
+
+int hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
+{
+ unsigned char val = 0;
+ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
+ while (val == 0) {
+ udelay(1000);
+ if (msec-- == 0)
+ return FALSE;
+ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
+ }
+ return TRUE;
+}
+
+int hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
+ unsigned char addr)
+{
+ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
+ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+ hdmi_writeb((unsigned char)(data >> 8),
+ HDMI_PHY_I2CM_DATAO_1_ADDR);
+ hdmi_writeb((unsigned char)(data >> 0),
+ HDMI_PHY_I2CM_DATAO_0_ADDR);
+ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
+ HDMI_PHY_I2CM_OPERATION_ADDR);
+ hdmi_phy_wait_i2c_done(hdmi, 1000);
+ return TRUE;
+}
+
+unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi, unsigned char addr)
+{
+ unsigned short data;
+ unsigned char msb = 0, lsb = 0;
+ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
+ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
+ HDMI_PHY_I2CM_OPERATION_ADDR);
+ hdmi_phy_wait_i2c_done(hdmi, 1000);
+ msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
+ lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
+ data = (msb << 8) | lsb;
+ return data;
+}
+
+int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
+ unsigned char addr)
+{
+ unsigned short val = 0;
+ hdmi_phy_i2c_write(hdmi, data, addr);
+ val = hdmi_phy_i2c_read(hdmi, addr);
+ if (val != data)
+ return FALSE;
+ return TRUE;
+}
+
+int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
+ unsigned char cRes, int cscOn, int audioOn,
+ int cecOn, int hdcpOn)
+{
+ u8 val;
+
+ /* color resolution 0 is 8 bit colour depth */
+ if (cRes == 0)
+ cRes = 8;
+
+ if (pRep != 0)
+ return FALSE;
+ else if (cRes != 8 && cRes != 12)
+ return FALSE;
+
+ if (cscOn)
+ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
+ else
+ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
+
+ hdmi_writeb(val, HDMI_MC_FLOWCTRL);
+
+ /* clock gate == 0 => turn on modules */
+ val = hdcpOn ? HDMI_MC_CLKDIS_HDCPCLK_DISABLE_ENABLE :
+ HDMI_MC_CLKDIS_HDCPCLK_DISABLE_DISABLE;
+ val |= HDMI_MC_CLKDIS_PIXELCLK_DISABLE_ENABLE;
+ val |= HDMI_MC_CLKDIS_TMDSCLK_DISABLE_ENABLE;
+ val |= (pRep > 0) ? HDMI_MC_CLKDIS_PREPCLK_DISABLE_ENABLE :
+ HDMI_MC_CLKDIS_PREPCLK_DISABLE_DISABLE;
+ val |= cecOn ? HDMI_MC_CLKDIS_CECCLK_DISABLE_ENABLE :
+ HDMI_MC_CLKDIS_CECCLK_DISABLE_DISABLE;
+ val |= cscOn ? HDMI_MC_CLKDIS_CSCCLK_DISABLE_ENABLE :
+ HDMI_MC_CLKDIS_CSCCLK_DISABLE_DISABLE;
+ val |= audioOn ? HDMI_MC_CLKDIS_AUDCLK_DISABLE_ENABLE :
+ HDMI_MC_CLKDIS_AUDCLK_DISABLE_DISABLE;
+ hdmi_writeb(val, HDMI_MC_CLKDIS);
+
+ /* gen2 tx power off */
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ val |= HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_OFF;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ /* gen2 pddq */
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK;
+ val |= HDMI_PHY_CONF0_GEN2_PDDQ_ENABLE;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ /* PHY reset */
+ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
+ hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
+
+ hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT,
+ HDMI_MC_HEACPHY_RST);
+
+ hdmi_phy_test_clear(hdmi, 1);
+ hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+ HDMI_PHY_I2CM_SLAVE_ADDR);
+ hdmi_phy_test_clear(hdmi, 0);
+
+ if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
+ dev_dbg(&hdmi->pdev->dev, "Pixel clock (%d) must be positive\n",
+ hdmi->hdmi_data.video_mode.mPixelClock);
+ return FALSE;
+ }
+
+ if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
+ switch (cRes) {
+ case 8:
+ /* PLL/MPLL Cfg */
+ hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
+ default:
+ return FALSE;
+ }
+ } else {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
+ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
+ default:
+ return FALSE;
+ }
+ }
+
+ if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
+ switch (cRes) {
+ case 8:
+ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
+ break;
+ case 10:
+ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
+ break;
+ case 12:
+ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
+ break;
+ default:
+ return FALSE;
+ }
+ } else {
+ dev_err(&hdmi->pdev->dev,
+ "Pixel clock %d - unsupported by HDMI\n",
+ hdmi->hdmi_data.video_mode.mPixelClock);
+ return FALSE;
+ }
+
+ hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
+ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
+ /* RESISTANCE TERM 133Ohm Cfg */
+ hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
+ /* PREEMP Cgf 0.00 */
+ hdmi_phy_i2c_write(hdmi, 0x8009, 0x09); /* CKSYMTXCTRL */
+ /* TX/CK LVL 10 */
+ hdmi_phy_i2c_write(hdmi, 0x0210, 0x0E); /* VLEVCTRL */
+ /* REMOVE CLK TERM */
+ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
+
+ if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
+ hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
+ hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
+ }
+
+ /* gen2 tx power on */
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ val |= HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_ON;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK;
+ val |= HDMI_PHY_CONF0_GEN2_PDDQ_DISABLE;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ udelay(1000);
+
+ if ((hdmi_readb(HDMI_PHY_STAT0) & 0x01) == 0)
+ return FALSE;
+
+ return TRUE;
+}
+
+void hdmi_phy_init(struct mxc_hdmi *hdmi, unsigned char de)
+{
+ u8 val;
+
+ /* set the DE polarity */
+ val = (de << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET) &
+ HDMI_PHY_CONF0_SELDATAENPOL_MASK;
+ /* set ENHPDRXSENSE to 1 */
+ val |= HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE;
+ /* set the interface control to 0 */
+ val |= (0 << HDMI_PHY_CONF0_SELDIPIF_OFFSET) &
+ HDMI_PHY_CONF0_SELDIPIF_MASK;
+ /* enable TMDS output */
+ val |= (1 << HDMI_PHY_CONF0_ENTMDS_OFFSET) &
+ HDMI_PHY_CONF0_ENTMDS_MASK;
+ /* PHY power enable */
+ val |= (1 << HDMI_PHY_CONF0_PDZ_OFFSET) &
+ HDMI_PHY_CONF0_PDZ_MASK;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ /* TODO: Enable CSC */
+ hdmi_phy_configure(hdmi, 0, 8, FALSE, TRUE, TRUE, FALSE);
+}
+
+void hdmi_tx_hdcp_config(struct mxc_hdmi *hdmi)
+{
+ u8 de, val;
+
+ if (hdmi->hdmi_data.video_mode.mDataEnablePolarity)
+ de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
+ else
+ de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
+
+ /* disable rx detect */
+ val = hdmi_readb(HDMI_A_HDCPCFG0);
+ val &= HDMI_A_HDCPCFG0_RXDETECT_MASK;
+ val |= HDMI_A_HDCPCFG0_RXDETECT_DISABLE;
+ hdmi_writeb(val, HDMI_A_HDCPCFG0);
+
+ val = hdmi_readb(HDMI_A_VIDPOLCFG);
+ val &= HDMI_A_VIDPOLCFG_DATAENPOL_MASK;
+ val |= de;
+ hdmi_writeb(val, HDMI_A_VIDPOLCFG);
+
+ val = hdmi_readb(HDMI_A_HDCPCFG1);
+ val &= HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK;
+ val |= HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE;
+ hdmi_writeb(val, HDMI_A_HDCPCFG1);
+}
+
+void preamble_filter_set(struct mxc_hdmi *hdmi, unsigned char value,
+ unsigned char channel)
+{
+ if (channel == 0)
+ hdmi_writeb(value, HDMI_FC_CH0PREAM);
+ else if (channel == 1)
+ hdmi_writeb(value, HDMI_FC_CH1PREAM);
+ else if (channel == 2)
+ hdmi_writeb(value, HDMI_FC_CH2PREAM);
+ else
+
+ return;
+}
+
+static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
+{
+ u8 val;
+ u8 pix_fmt;
+ u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
+ struct fb_videomode mode;
+ const struct fb_videomode *edid_mode;
+ bool aspect_16_9;
+
+ dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
+
+ fb_var_to_videomode(&mode, &hdmi->fbi->var);
+ /* Use mode from list extracted from EDID to get aspect ratio */
+ if (!list_empty(&hdmi->fbi->modelist)) {
+ edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
+ if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
+ aspect_16_9 = true;
+ else
+ aspect_16_9 = false;
+ } else
+ aspect_16_9 = false;
+
+ /********************************************
+ * AVI Data Byte 1
+ ********************************************/
+ if (hdmi->edid_cfg.cea_ycbcr444)
+ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
+ else if (hdmi->edid_cfg.cea_ycbcr422)
+ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
+ else
+ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
+
+ /*
+ * Active format identification data is present in the AVI InfoFrame.
+ * No scan info, no bar data
+ */
+ val = pix_fmt |
+ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
+ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA |
+ HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
+
+ hdmi_writeb(val, HDMI_FC_AVICONF0);
+
+ /********************************************
+ * AVI Data Byte 2
+ ********************************************/
+
+ /* Set the Aspect Ratio */
+ if (aspect_16_9) {
+ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
+ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
+ } else {
+ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
+ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
+ }
+
+ /* Set up colorimetry */
+ if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
+ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
+ if (hdmi->hdmi_data.colorimetry == eITU601)
+ ext_colorimetry =
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+ else /* hdmi->hdmi_data.colorimetry == eITU709 */
+ ext_colorimetry =
+ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
+ } else if (hdmi->hdmi_data.enc_out_format != RGB) {
+ if (hdmi->hdmi_data.colorimetry == eITU601)
+ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
+ else /* hdmi->hdmi_data.colorimetry == eITU709 */
+ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
+ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+ } else { /* Carries no data */
+ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
+ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+ }
+
+ val = colorimetry | coded_ratio | act_ratio;
+ hdmi_writeb(val, HDMI_FC_AVICONF1);
+
+ /********************************************
+ * AVI Data Byte 3
+ ********************************************/
+
+ val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
+ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
+ HDMI_FC_AVICONF2_SCALING_NONE;
+ hdmi_writeb(val, HDMI_FC_AVICONF2);
+
+ /********************************************
+ * AVI Data Byte 4
+ ********************************************/
+ hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
+
+ /********************************************
+ * AVI Data Byte 5
+ ********************************************/
+
+ /* Set up input and output pixel repetition */
+ val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
+ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
+ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
+ ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
+ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
+ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
+ hdmi_writeb(val, HDMI_FC_PRCONF);
+
+ /* IT Content and quantization range = don't care */
+ val = HDMI_FC_AVICONF2_IT_CONTENT_TYPE_GRAPHICS |
+ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
+ hdmi_writeb(val, HDMI_FC_AVICONF3);
+
+ /********************************************
+ * AVI Data Bytes 6-13
+ ********************************************/
+ hdmi_writeb(0, HDMI_FC_AVIETB0);
+ hdmi_writeb(0, HDMI_FC_AVIETB1);
+ hdmi_writeb(0, HDMI_FC_AVISBB0);
+ hdmi_writeb(0, HDMI_FC_AVISBB1);
+ hdmi_writeb(0, HDMI_FC_AVIELB0);
+ hdmi_writeb(0, HDMI_FC_AVIELB1);
+ hdmi_writeb(0, HDMI_FC_AVISRB0);
+ hdmi_writeb(0, HDMI_FC_AVISRB1);
+}
+
+/*!
+ * this submodule is responsible for the video/audio data composition.
+ */
+void hdmi_av_composer(struct mxc_hdmi *hdmi)
+{
+ unsigned char i = 0;
+ u8 val;
+ struct fb_info *fbi = hdmi->fbi;
+ struct fb_videomode fb_mode;
+ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
+ int hblank, vblank;
+
+ fb_var_to_videomode(&fb_mode, &fbi->var);
+
+ vmode->mHSyncPolarity =
+ (fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) ? TRUE : FALSE;
+ vmode->mVSyncPolarity =
+ (fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) ? TRUE : FALSE;
+ vmode->mInterlaced =
+ (fb_mode.vmode & FB_VMODE_INTERLACED) ? TRUE : FALSE;
+ vmode->mPixelClock = (fb_mode.xres + fb_mode.left_margin +
+ fb_mode.right_margin + fb_mode.hsync_len) * (fb_mode.yres +
+ fb_mode.upper_margin + fb_mode.lower_margin +
+ fb_mode.vsync_len) * fb_mode.refresh;
+
+ dev_dbg(&hdmi->pdev->dev, "final pixclk = %d\n", vmode->mPixelClock);
+
+ /* Set up HDMI_FC_INVIDCONF */
+ val = ((hdmi->hdmi_data.hdcp_enable == TRUE) ?
+ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
+ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
+ val |= ((vmode->mVSyncPolarity == TRUE) ?
+ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
+ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
+ val |= ((vmode->mHSyncPolarity == TRUE) ?
+ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
+ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
+ val |= ((vmode->mDataEnablePolarity == TRUE) ?
+ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
+ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
+ val |= ((vmode->mHdmiDviSel == TRUE) ?
+ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
+ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
+ if (hdmi->vic == 39)
+ val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
+ else
+ val |= ((vmode->mInterlaced == TRUE) ?
+ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
+ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
+ val |= ((vmode->mInterlaced == TRUE) ?
+ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
+ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
+ hdmi_writeb(val, HDMI_FC_INVIDCONF);
+
+ /* Set up horizontal active pixel region width */
+ hdmi_writeb(fb_mode.xres,
+ HDMI_FC_INHACTV0);
+ hdmi_writeb(fb_mode.xres >> 8,
+ HDMI_FC_INHACTV1);
+
+ /* Set up horizontal blanking pixel region width */
+ hblank = fb_mode.left_margin + fb_mode.right_margin +
+ fb_mode.hsync_len;
+ hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
+ hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
+
+ /* Set up vertical blanking pixel region width */
+ hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
+ hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
+
+ /* Set up vertical blanking pixel region width */
+ vblank = fb_mode.upper_margin + fb_mode.lower_margin +
+ fb_mode.vsync_len;
+ hdmi_writeb(vblank, HDMI_FC_INVBLANK);
+
+ /* Set up HSYNC active edge delay width (in pixel clks) */
+ hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
+ hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
+
+ /* Set up HSYNC active pulse width (in pixel clks) */
+ hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
+ hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
+
+ /* Set up VSYNC active edge delay (in pixel clks) */
+ hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
+
+ /* Set up VSYNC active edge delay (in pixel clks) */
+ hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
+
+ /* control period minimum duration */
+ hdmi_writeb(12, HDMI_FC_CTRLDUR);
+ hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
+ hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
+
+ for (i = 0; i < 3; i++)
+ preamble_filter_set(hdmi, (i + 1) * 11, i);
+
+ /* configure AVI InfoFrame */
+ hdmi_config_AVI(hdmi);
+}
+
+static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi,
+ struct fb_info *fbi)
+{
+ int ret;
+ u8 edid_old[HDMI_EDID_LEN];
+
+ /* save old edid */
+ memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
+
+ /* edid reading */
+ ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
+ hdmi->edid, &hdmi->edid_cfg, fbi);
+
+ if (ret < 0)
+ return ret;
+
+ if (!memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN))
+ ret = -2;
+ return ret;
+}
+
+static void mxc_hdmi_poweron(struct mxc_hdmi *hdmi)
+{
+ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
+
+ dev_dbg(&hdmi->pdev->dev, "power on\n");
+
+ /* Enable pins to HDMI */
+ if (plat->enable_pins)
+ plat->enable_pins();
+}
+
+static void mxc_hdmi_poweroff(struct mxc_hdmi *hdmi)
+{
+ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
+
+ dev_dbg(&hdmi->pdev->dev, "power off\n");
+
+ /* Disable pins to HDMI */
+ if (plat->disable_pins)
+ plat->disable_pins();
+}
+
+static void mxc_hdmi_enable(struct mxc_hdmi *hdmi)
+{
+ u8 val;
+
+ dev_dbg(&hdmi->pdev->dev, "hdmi enable\n");
+
+ clk_enable(hdmi->hdmi_iahb_clk);
+
+ /* Enable HDMI PHY - Set PDDQ=0 and TXPWRON=1 */
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~(HDMI_PHY_CONF0_GEN2_PDDQ_MASK |
+ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
+ val |= HDMI_PHY_CONF0_GEN2_PDDQ_DISABLE |
+ HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_ON;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ if (hdmi->need_mode_change && hdmi->fb_reg) {
+ dev_dbg(&hdmi->pdev->dev, "HDMI changing FB mode\n");
+ hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
+ console_lock();
+ hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
+ fb_set_var(hdmi->fbi, &hdmi->fbi->var);
+ hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
+ console_unlock();
+ hdmi->need_mode_change = false;
+ }
+}
+
+static void mxc_hdmi_disable(struct mxc_hdmi *hdmi)
+{
+ u8 val;
+
+ dev_dbg(&hdmi->pdev->dev, "hdmi disable\n");
+
+ /* Disable HDMI PHY - Set PDDQ=1 and TXPWRON=0 */
+ val = hdmi_readb(HDMI_PHY_CONF0);
+ val &= ~(HDMI_PHY_CONF0_GEN2_PDDQ_MASK |
+ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
+ val |= HDMI_PHY_CONF0_GEN2_PDDQ_ENABLE |
+ HDMI_PHY_CONF0_GEN2_TXPWRON_POWER_OFF;
+ hdmi_writeb(val, HDMI_PHY_CONF0);
+
+ clk_disable(hdmi->hdmi_iahb_clk);
+}
+
+static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
+{
+ u32 i;
+ const struct fb_videomode *mode;
+
+ fb_destroy_modelist(&hdmi->fbi->modelist);
+
+ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
+ mode = &mxc_cea_mode[i];
+ if ((mode->xres == hdmi->fbi->var.xres) &&
+ (mode->yres == hdmi->fbi->var.yres) &&
+ !(mode->vmode & FB_VMODE_INTERLACED))
+ fb_add_videomode(mode, &hdmi->fbi->modelist);
+ }
+}
+
+static int mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
+{
+ int ret;
+ struct fb_videomode m;
+ const struct fb_videomode *mode;
+
+ dev_dbg(&hdmi->pdev->dev, "cable connected\n");
+
+ hdmi->cable_plugin = true;
+
+ /* edid read */
+ ret = mxc_hdmi_read_edid(hdmi, hdmi->fbi);
+ if (ret == -2)
+ dev_info(&hdmi->pdev->dev, "same edid\n");
+ else if (hdmi->fbi->monspecs.modedb_len > 0) {
+ int i;
+
+ fb_destroy_modelist(&hdmi->fbi->modelist);
+
+ for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
+ /*
+ * We might check here if mode is supported by HDMI.
+ * We do not currently support interlaced modes
+ */
+ if (!(hdmi->fbi->monspecs.modedb[i].vmode
+ & FB_VMODE_INTERLACED)) {
+ dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
+ dev_dbg(&hdmi->pdev->dev,
+ "xres = %d, yres = %d, freq = %d\n",
+ hdmi->fbi->monspecs.modedb[i].xres,
+ hdmi->fbi->monspecs.modedb[i].yres,
+ hdmi->fbi->monspecs.modedb[i].refresh);
+ fb_add_videomode(&hdmi->fbi->monspecs.modedb[i],
+ &hdmi->fbi->modelist);
+ }
+ }
+
+ fb_var_to_videomode(&m, &hdmi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &hdmi->fbi->modelist);
+
+ fb_videomode_to_var(&hdmi->fbi->var, mode);
+ hdmi->need_mode_change = true;
+ } else {
+ /* If not EDID data readed, setup default modelist */
+ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
+ mxc_hdmi_default_modelist(hdmi);
+
+ fb_var_to_videomode(&m, &hdmi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &hdmi->fbi->modelist);
+
+ fb_videomode_to_var(&hdmi->fbi->var, mode);
+ hdmi->need_mode_change = true;
+ }
+
+
+ return 0;
+}
+
+static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
+{
+ hdmi->cable_plugin = false;
+}
+
+static void det_worker(struct work_struct *work)
+{
+ struct delayed_work *delay_work = to_delayed_work(work);
+ struct mxc_hdmi *hdmi =
+ container_of(delay_work, struct mxc_hdmi, det_work);
+ u32 phy_int_stat, phy_int_pol, phy_int_mask;
+ u8 val;
+ bool hdmi_disable = false;
+ int irq = platform_get_irq(hdmi->pdev, 0);
+ unsigned long flags;
+
+ if (!hdmi->irq_enabled) {
+ clk_enable(hdmi->hdmi_iahb_clk);
+
+ /* Capture status - used in det_worker ISR */
+ phy_int_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
+ if ((phy_int_stat & HDMI_IH_PHY_STAT0_HPD) == 0) {
+ clk_disable(hdmi->hdmi_iahb_clk);
+ return; /* No interrupts to handle */
+ }
+
+ dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
+
+ /* Unmask interrupts until handled */
+ val = hdmi_readb(HDMI_PHY_MASK0);
+ val |= HDMI_PHY_HPD;
+ hdmi_writeb(val, HDMI_PHY_MASK0);
+
+ /* Clear Hotplug interrupts */
+ hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+
+ phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
+
+ clk_disable(hdmi->hdmi_iahb_clk);
+ } else {
+ /* Use saved interrupt status, since it was cleared in IST */
+ phy_int_stat = hdmi->latest_intr_stat;
+ phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
+ }
+
+ /* Re-enable HDMI irq now that our interrupts have been masked off */
+ hdmi_irq_enable(irq);
+
+ /* check cable status */
+ if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) {
+ /* cable connection changes */
+ if (phy_int_pol & HDMI_PHY_HPD) {
+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
+ mxc_hdmi_cable_connected(hdmi);
+ mxc_hdmi_enable(hdmi);
+
+ /* Make HPD intr active low to capture unplug event */
+ val = hdmi_readb(HDMI_PHY_POL0);
+ val &= ~HDMI_PHY_HPD;
+ hdmi_writeb(val, HDMI_PHY_POL0);
+ } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
+ mxc_hdmi_cable_disconnected(hdmi);
+ hdmi_disable = true;
+
+ /* Make HPD intr active high to capture plugin event */
+ val = hdmi_readb(HDMI_PHY_POL0);
+ val |= HDMI_PHY_HPD;
+ hdmi_writeb(val, HDMI_PHY_POL0);
+ } else
+ dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n");
+ }
+
+ /* Lock here to ensure full powerdown sequence
+ * completed before next interrupt processed */
+ spin_lock_irqsave(&hdmi->irq_lock, flags);
+
+ /* Re-enable HPD interrupts */
+ phy_int_mask = hdmi_readb(HDMI_PHY_MASK0);
+ phy_int_mask &= ~HDMI_PHY_HPD;
+ hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0);
+
+ if (hdmi_disable)
+ mxc_hdmi_disable(hdmi);
+
+ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
+}
+
+static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
+{
+ struct mxc_hdmi *hdmi = data;
+ unsigned int ret;
+ u8 val, intr_stat;
+ unsigned long flags;
+
+ spin_lock_irqsave(&hdmi->irq_lock, flags);
+
+ /*
+ * We have to disable the irq, rather than just masking
+ * off the HDMI interrupts using HDMI registers. This is
+ * because the HDMI iahb clock is required to be on to
+ * access the HDMI registers, and we cannot enable it
+ * in an IST. This IRQ will be re-enabled in the
+ * interrupt handler workqueue function.
+ */
+ ret = hdmi_irq_disable(irq);
+ if (ret == IRQ_DISABLE_FAIL) {
+ /* Capture status - used in det_worker ISR */
+ intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
+ if ((intr_stat & HDMI_IH_PHY_STAT0_HPD) == 0) {
+ hdmi_irq_enable(irq);
+ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
+ return IRQ_HANDLED;
+ }
+ dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
+ hdmi->latest_intr_stat = intr_stat;
+
+ /* Unmask interrupts until handled */
+ val = hdmi_readb(HDMI_PHY_MASK0);
+ val |= HDMI_PHY_HPD;
+ hdmi_writeb(val, HDMI_PHY_MASK0);
+
+ /* Clear Hotplug interrupts */
+ hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+
+ hdmi->irq_enabled = true;
+ } else
+ hdmi->irq_enabled = false;
+
+ schedule_delayed_work(&(hdmi->det_work), msecs_to_jiffies(20));
+
+ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static int mxc_hdmi_setup(struct mxc_hdmi *hdmi)
+{
+ struct fb_videomode m;
+ const struct fb_videomode *edid_mode;
+
+ fb_var_to_videomode(&m, &hdmi->fbi->var);
+ if (!list_empty(&hdmi->fbi->modelist)) {
+ edid_mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
+
+ hdmi->vic = mxc_edid_mode_to_vic(edid_mode);
+ } else
+ hdmi->vic = 0;
+
+ if (hdmi->vic == 0) {
+ dev_dbg(&hdmi->pdev->dev, "Non-CEA mode used in HDMI\n");
+ hdmi->hdmi_data.video_mode.mHdmiDviSel = FALSE;
+ } else
+ hdmi->hdmi_data.video_mode.mHdmiDviSel = TRUE;
+
+ if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
+ (hdmi->vic == 21) || (hdmi->vic == 22) ||
+ (hdmi->vic == 2) || (hdmi->vic == 3) ||
+ (hdmi->vic == 17) || (hdmi->vic == 18))
+ hdmi->hdmi_data.colorimetry = eITU601;
+ else
+ hdmi->hdmi_data.colorimetry = eITU709;
+
+ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
+ (hdmi->vic == 12) || (hdmi->vic == 13) ||
+ (hdmi->vic == 14) || (hdmi->vic == 15) ||
+ (hdmi->vic == 25) || (hdmi->vic == 26) ||
+ (hdmi->vic == 27) || (hdmi->vic == 28) ||
+ (hdmi->vic == 29) || (hdmi->vic == 30) ||
+ (hdmi->vic == 35) || (hdmi->vic == 36) ||
+ (hdmi->vic == 37) || (hdmi->vic == 38))
+ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
+ else
+ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
+
+ hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
+
+ /* TODO: Get input format from IPU (via FB driver iface) */
+ hdmi->hdmi_data.enc_in_format = RGB;
+
+ hdmi->hdmi_data.enc_out_format = RGB;
+ if (hdmi->edid_cfg.hdmi_cap) {
+ if (hdmi->edid_cfg.cea_ycbcr444)
+ hdmi->hdmi_data.enc_out_format = YCBCR444;
+ else if (hdmi->edid_cfg.cea_ycbcr422)
+ hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
+ }
+
+ hdmi->hdmi_data.enc_color_depth = 8;
+ hdmi->hdmi_data.pix_repet_factor = 0;
+ hdmi->hdmi_data.hdcp_enable = 0;
+ hdmi->hdmi_data.video_mode.mDataEnablePolarity = TRUE;
+
+ hdmi_video_force_output(hdmi, TRUE);
+ hdmi_av_composer(hdmi);
+ hdmi_video_packetize(hdmi);
+ hdmi_video_csc(hdmi);
+ hdmi_video_sample(hdmi);
+ hdmi_tx_hdcp_config(hdmi);
+ hdmi_phy_init(hdmi, TRUE);
+ hdmi_video_force_output(hdmi, FALSE);
+ /*FIXME: audio CTS/N should be set after ipu display timming finish */
+ /*hdmi_set_clk_regenerator();*/
+
+ return 0;
+}
+
+static int mxc_hdmi_fb_event(struct notifier_block *nb,
+ unsigned long val, void *v)
+{
+ struct fb_event *event = v;
+ struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
+
+ if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
+ return 0;
+
+ switch (val) {
+ case FB_EVENT_FB_REGISTERED:
+ hdmi->fb_reg = true;
+ break;
+ case FB_EVENT_FB_UNREGISTERED:
+ hdmi->fb_reg = false;
+ break;
+ case FB_EVENT_MODE_CHANGE:
+ mxc_hdmi_setup(hdmi);
+ break;
+ case FB_EVENT_BLANK:
+ if (*((int *)event->data) == FB_BLANK_UNBLANK)
+ mxc_hdmi_poweron(hdmi);
+ else
+ mxc_hdmi_poweroff(hdmi);
+ break;
+ }
+ return 0;
+}
+
+static int mxc_hdmi_disp_init(struct mxc_dispdrv_entry *disp)
+{
+ int ret = 0;
+ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
+ struct mxc_dispdrv_setting *setting = mxc_dispdrv_getsetting(disp);
+ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
+ int irq = platform_get_irq(hdmi->pdev, 0);
+ bool found = false;
+ u8 val;
+ const struct fb_videomode *mode;
+ struct fb_videomode m;
+ struct fb_var_screeninfo var;
+
+ if (!plat || irq < 0)
+ return -ENODEV;
+
+ setting->dev_id = mxc_hdmi_ipu_id;
+ setting->disp_id = mxc_hdmi_disp_id;
+ setting->if_fmt = IPU_PIX_FMT_RGB24;
+
+ hdmi->fbi = setting->fbi;
+
+ /* Claim HDMI pins */
+ if (plat->get_pins)
+ if (!plat->get_pins()) {
+ ret = -EACCES;
+ goto egetpins;
+ }
+
+ /* Initialize HDMI */
+ if (plat->init)
+ plat->init(mxc_hdmi_ipu_id, mxc_hdmi_disp_id);
+
+ hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr_clk");
+ if (IS_ERR(hdmi->hdmi_isfr_clk)) {
+ ret = PTR_ERR(hdmi->hdmi_isfr_clk);
+ dev_err(&hdmi->pdev->dev,
+ "Unable to get HDMI clk: %d\n", ret);
+ goto egetclk1;
+ }
+
+ ret = clk_enable(hdmi->hdmi_isfr_clk);
+ if (ret < 0) {
+ dev_err(&hdmi->pdev->dev,
+ "Cannot enable HDMI isfr clock: %d\n", ret);
+ goto erate1;
+ }
+
+ hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb_clk");
+ if (IS_ERR(hdmi->hdmi_iahb_clk)) {
+ ret = PTR_ERR(hdmi->hdmi_iahb_clk);
+ dev_err(&hdmi->pdev->dev,
+ "Unable to get HDMI clk: %d\n", ret);
+ goto egetclk2;
+ }
+
+ ret = clk_enable(hdmi->hdmi_iahb_clk);
+ if (ret < 0) {
+ dev_err(&hdmi->pdev->dev,
+ "Cannot enable HDMI iahb clock: %d\n", ret);
+ goto erate2;
+ }
+
+ dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
+
+ /* Product and revision IDs */
+ dev_info(&hdmi->pdev->dev,
+ "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
+ hdmi_readb(HDMI_DESIGN_ID),
+ hdmi_readb(HDMI_REVISION_ID),
+ hdmi_readb(HDMI_PRODUCT_ID0),
+ hdmi_readb(HDMI_PRODUCT_ID1));
+
+ INIT_LIST_HEAD(&hdmi->fbi->modelist);
+
+ /* try to read edid */
+ ret = mxc_hdmi_read_edid(hdmi, hdmi->fbi);
+ if (ret < 0) {
+ /* If not EDID data readed, setup default modelist */
+ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
+ mxc_hdmi_default_modelist(hdmi);
+
+ fb_var_to_videomode(&m, &hdmi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &hdmi->fbi->modelist);
+
+ fb_videomode_to_var(&hdmi->fbi->var, mode);
+ hdmi->need_mode_change = true;
+ } else if (hdmi->fbi->monspecs.modedb_len > 0) {
+ int i;
+
+ for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
+ /*
+ * We might check here if mode is supported by HDMI.
+ * Also, we do not currently support interlaced modes
+ */
+ fb_videomode_to_var(&var, &hdmi->fbi->monspecs.modedb[i]);
+ if (!(hdmi->fbi->monspecs.modedb[i].vmode
+ & FB_VMODE_INTERLACED)) {
+ dev_dbg(&hdmi->pdev->dev, "Adding mode %d:", i);
+ dev_dbg(&hdmi->pdev->dev,
+ "xres = %d, yres = %d, freq = %d\n",
+ hdmi->fbi->monspecs.modedb[i].xres,
+ hdmi->fbi->monspecs.modedb[i].yres,
+ hdmi->fbi->monspecs.modedb[i].refresh);
+ fb_add_videomode(
+ &hdmi->fbi->monspecs.modedb[i],
+ &hdmi->fbi->modelist);
+ }
+ }
+
+ fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
+ setting->dft_mode_str, NULL, 0, NULL,
+ setting->default_bpp);
+
+ fb_var_to_videomode(&m, &hdmi->fbi->var);
+ mode = fb_find_nearest_mode(&m,
+ &hdmi->fbi->modelist);
+ fb_videomode_to_var(&hdmi->fbi->var, mode);
+ found = 1;
+
+ hdmi->need_mode_change = true;
+ }
+
+ if (!found) {
+ ret = fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
+ setting->dft_mode_str, NULL, 0, NULL,
+ setting->default_bpp);
+ if (!ret) {
+ ret = -EINVAL;
+ goto efindmode;
+ }
+ }
+
+ spin_lock_init(&hdmi->irq_lock);
+
+ INIT_DELAYED_WORK(&(hdmi->det_work), det_worker);
+
+ /* Configure registers related to HDMI interrupt
+ * generation before registering IRQ. */
+ hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0);
+
+ /* enable cable hot plug irq */
+ val = ~HDMI_PHY_HPD;
+ hdmi_writeb(val, HDMI_PHY_MASK0);
+
+ /* Clear Hotplug interrupts */
+ hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+
+ hdmi_writeb(~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+
+ hdmi->nb.notifier_call = mxc_hdmi_fb_event;
+ ret = fb_register_client(&hdmi->nb);
+ if (ret < 0)
+ goto efbclient;
+
+ memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
+
+ mxc_hdmi_setup(hdmi);
+
+ /* Disable IAHB clock while waiting for hotplug interrupt.
+ * ISFR clock must remain enabled for hotplug to work. */
+ clk_disable(hdmi->hdmi_iahb_clk);
+
+ /* Initialize IRQ at HDMI core level */
+ hdmi_irq_init();
+
+ ret = request_irq(irq, mxc_hdmi_hotplug, IRQF_SHARED,
+ dev_name(&hdmi->pdev->dev), hdmi);
+ if (ret < 0) {
+ dev_err(&hdmi->pdev->dev,
+ "Unable to request irq: %d\n", ret);
+ goto ereqirq;
+ }
+
+ return ret;
+
+efbclient:
+ free_irq(irq, hdmi);
+efindmode:
+ereqirq:
+ clk_disable(hdmi->hdmi_iahb_clk);
+erate2:
+ clk_put(hdmi->hdmi_iahb_clk);
+egetclk2:
+ clk_disable(hdmi->hdmi_isfr_clk);
+erate1:
+ clk_put(hdmi->hdmi_isfr_clk);
+egetclk1:
+ plat->put_pins();
+egetpins:
+ return ret;
+}
+
+static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_entry *disp)
+{
+ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
+ struct fsl_mxc_hdmi_platform_data *plat = hdmi->pdev->dev.platform_data;
+
+ fb_unregister_client(&hdmi->nb);
+
+ mxc_hdmi_poweroff(hdmi);
+
+ clk_disable(hdmi->hdmi_isfr_clk);
+ clk_put(hdmi->hdmi_isfr_clk);
+ clk_disable(hdmi->hdmi_iahb_clk);
+ clk_put(hdmi->hdmi_iahb_clk);
+
+ /* Release HDMI pins */
+ if (plat->put_pins)
+ plat->put_pins();
+
+ platform_device_unregister(hdmi->pdev);
+
+ kfree(hdmi);
+}
+
+static struct mxc_dispdrv_driver mxc_hdmi_drv = {
+ .name = DISPDRV_HDMI,
+ .init = mxc_hdmi_disp_init,
+ .deinit = mxc_hdmi_disp_deinit,
+};
+
+static int __devinit mxc_hdmi_probe(struct platform_device *pdev)
+{
+ struct mxc_hdmi *hdmi;
+ int ret = 0;
+
+ /* Check that I2C driver is loaded and available */
+ if (!hdmi_i2c)
+ return -ENODEV;
+
+ hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi) {
+ dev_err(&pdev->dev, "Cannot allocate device data\n");
+ ret = -ENOMEM;
+ goto ealloc;
+ }
+
+ hdmi->pdev = pdev;
+
+ hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
+ if (!hdmi->core_pdev) {
+ pr_err("%s failed platform_device_alloc for hdmi core\n",
+ __func__);
+ ret = -ENOMEM;
+ goto ecore;
+ }
+
+ hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
+ if (IS_ERR(hdmi->disp_mxc_hdmi)) {
+ dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
+ (int)hdmi->disp_mxc_hdmi);
+ ret = (int)hdmi->disp_mxc_hdmi;
+ goto edispdrv;
+ }
+ mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ return 0;
+edispdrv:
+ platform_device_put(hdmi->core_pdev);
+ecore:
+ kfree(hdmi);
+ealloc:
+ return ret;
+}
+
+static int mxc_hdmi_remove(struct platform_device *pdev)
+{
+ struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
+ int irq = platform_get_irq(pdev, 0);
+
+ fb_unregister_client(&hdmi->nb);
+
+ /* No new work will be scheduled, wait for running ISR */
+ free_irq(irq, hdmi);
+ kfree(hdmi);
+
+ return 0;
+}
+
+static struct platform_driver mxc_hdmi_driver = {
+ .probe = mxc_hdmi_probe,
+ .remove = mxc_hdmi_remove,
+ .driver = {
+ .name = "mxc_hdmi",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init mxc_hdmi_init(void)
+{
+ return platform_driver_register(&mxc_hdmi_driver);
+}
+module_init(mxc_hdmi_init);
+
+static void __exit mxc_hdmi_exit(void)
+{
+ platform_driver_unregister(&mxc_hdmi_driver);
+}
+module_exit(mxc_hdmi_exit);
+
+
+static int __devinit mxc_hdmi_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
+ return -ENODEV;
+
+ hdmi_i2c = client;
+
+ return 0;
+}
+
+static int __devexit mxc_hdmi_i2c_remove(struct i2c_client *client)
+{
+ hdmi_i2c = NULL;
+ return 0;
+}
+
+static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
+ { "mxc_hdmi_i2c", 0 },
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
+
+static const struct of_device_id mxc_hdmi_ddc_dt_ids[] = {
+ { .compatible = "fsl,imx6q-hdmi-ddc", },
+ { /* sentinel */ }
+};
+
+static struct i2c_driver mxc_hdmi_i2c_driver = {
+ .driver = {
+ .name = "mxc_hdmi_i2c",
+ .of_match_table = mxc_hdmi_ddc_dt_ids,
+ },
+ .probe = mxc_hdmi_i2c_probe,
+ .remove = mxc_hdmi_i2c_remove,
+ .id_table = mxc_hdmi_i2c_id,
+};
+
+static int __init mxc_hdmi_i2c_init(void)
+{
+ return i2c_add_driver(&mxc_hdmi_i2c_driver);
+}
+
+static void __exit mxc_hdmi_i2c_exit(void)
+{
+ i2c_del_driver(&mxc_hdmi_i2c_driver);
+}
+
+module_init(mxc_hdmi_i2c_init);
+module_exit(mxc_hdmi_i2c_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index cb624eaff19..caf89353116 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -316,6 +316,27 @@ struct fsl_mxc_lcd_platform_data {
int disp_id;
};
+struct fsl_mxc_dvi_platform_data {
+ void (*init) (void);
+ int (*update) (void);
+ char *analog_regulator;
+ int ipu_id;
+ int disp_id;
+};
+
+struct fsl_mxc_hdmi_platform_data {
+ void (*init) (int, int);
+ int (*get_pins) (void);
+ void (*put_pins) (void);
+ void (*enable_pins) (void);
+ void (*disable_pins) (void);
+};
+
+struct fsl_mxc_hdmi_core_platform_data {
+ int ipu_id;
+ int disp_id;
+};
+
struct fsl_mxc_ldb_platform_data {
char *lvds_bg_reg;
u32 ext_ref;
diff --git a/include/linux/iram_alloc.h b/include/linux/iram_alloc.h
new file mode 100644
index 00000000000..d5d4c41a78a
--- /dev/null
+++ b/include/linux/iram_alloc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifdef CONFIG_IRAM_ALLOC
+int __init iram_init(unsigned long base, unsigned long size);
+void *iram_alloc(unsigned int size, unsigned long *dma_addr);
+void iram_free(unsigned long dma_addr, unsigned int size);
+#else
+static inline int __init iram_init(unsigned long base, unsigned long size)
+{
+ return -ENOMEM;
+}
+static inline void *iram_alloc(unsigned int size, unsigned long *dma_addr)
+{
+ return NULL;
+}
+static inline void iram_free(unsigned long base, unsigned long size) {}
+#endif
+
diff --git a/include/linux/mfd/mxc-hdmi-core.h b/include/linux/mfd/mxc-hdmi-core.h
new file mode 100644
index 00000000000..f449946a50f
--- /dev/null
+++ b/include/linux/mfd/mxc-hdmi-core.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __LINUX_MXC_HDMI_CORE_H_
+#define __LINUX_MXC_HDMI_CORE_H_
+
+#define IRQ_DISABLE_SUCCEED 0
+#define IRQ_DISABLE_FAIL 1
+
+u8 hdmi_readb(unsigned int reg);
+void hdmi_writeb(u8 value, unsigned int reg);
+void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask);
+unsigned int hdmi_read4(unsigned int reg);
+void hdmi_write4(unsigned int value, unsigned int reg);
+void hdmi_irq_init(void);
+void hdmi_irq_enable(int irq);
+unsigned int hdmi_irq_disable(int irq);
+void hdmi_set_sample_rate(unsigned int rate);
+void hdmi_set_clk_regenerator(void);
+
+extern int mxc_hdmi_ipu_id;
+extern int mxc_hdmi_disp_id;
+
+#endif