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2010-12-24ENGR00137362-2 L2Swtich: Add phy support for switch port1 and port2rel_imx_2.6.35_10.12.01_RC4Xie Xiaobo
Because the 1588 stack and STP stack need to know the phy status, added phy support for switch port1 and port2. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2010-12-24ENGR00137362-1 L2Switch: Add ENET-MAC interrupt resourceXie Xiaobo
In Switch mode, The ENET-MAC interrupts are enabled and can be used to monitor the line activity. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2010-12-24ENGR00137339 PTP: Synchronize fec1 timer to fec0 timer in i.MX28Xie Xiaobo
When enable fec0 and fec1 1588 timer in the same time, enalbe fec1 1588 timer to FRC_SLAVE mode in i.MX28. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> (cherry picked from commit e90197be678342bf9a09c4f64f5fe25a84cf75c7)
2010-12-24ENGR00136994 UBI : system halt when detaching UBI in NFS environmentHuang Shijie
The problem is caused by: ubi double free ubiblk_dev structrue, cause the list and memory mess up. This patch changes field `m` in the ubiblk_dev{} from the mtd_blktrans_dev{} to pointer. Also add a mutex for protecting the global ubiblk_devices. Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-22ENGR00136035 MX28 ALSA: Pcm read error during arecording and aplayingLionel Xu
Reslove the pcm read error when opening arecord and aplay at the same time. Signed-off-by: Lionel Xu <r63889@freescale.com> (cherry picked from commit c8d1b31e0fde30874d352c216a44ec1ad05424e1)
2010-12-20ENGR00137175 usb-otg: DO NOT read usb registers when usb is in low power modePeter Chen
Should not read usb registers when usb is in low power mode, or it will cause usb system hang or getting the wrong registers value Signed-off-by: Peter Chen <peter.chen@freescale.com>
2010-12-20ENGR00137080 USB: fix usb device can't work on MX53 boardZhang Yan
Set USB VBUS on when host only controller probed. Only DR OTG host doesn't set vbus on when platform driver probed. Signed-off-by: Zhang Yan <b34916@freescale.com>
2010-12-17ENGR00137099 - EPDC fb: Fix bug related to panning + Queue update schemeDanny Nold
- Changed default update scheme to SNAPSHOT - Added panning offset info for each update - Added merge check against panning offset - Fixed conditions for merging Signed-off-by: Danny Nold <dannynold@freescale.com>
2010-12-17ENGR00137101-6 mark the erase failed block to the bbt table.Huang Shijie
If it return failure in erasing a block, mark the block bad in the bbt table. Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-17ENGR00137101-5 GPMI : add TOGGLE NAND supportHuang Shijie
[1] Add the initializtion for TOGGLE nand. [2] chang the is_onfi_nand() to is_ddr_nand(). [3] add NAND_LOCK in the send_command() Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-17ENGR00137101-4 GPMI : change the is_onfi_nand() to is_ddr_nand()Huang Shijie
change the function name is_onfi_nand() to is_ddr_nand(). Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-17ENGR00137101-3 NAND : add TOGGLE NAND device info to the tableHuang Shijie
Add the TOGGLE nand device infomation to the table. And change the `is_onfi_nand` to `is_ddr_ok`. Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-17ENGR00137101-2 NAND : change the field `is_onfi_nand` to `is_ddr_ok`Huang Shijie
The ONFI NAND and TOGGLE NAND both support the DDR. So merge the same attribution to a new field `is_ddr_ok`. Also add a inline function to judge the DDR nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-17ENGR00137101-1 clock : keep GPMI and BCH working in the same frequencyHuang Shijie
add the BCH clock setting, and keep them work in the same frequncy. Signed-off-by: Huang Shijie <b32955@freescale.com>
2010-12-16ENGR00136909: MX50: Drop DDR freq to 133Mhz when AHB is at medium setpoint.Ranjani Vaidyanathan
Change the DDR freq to 133MHz from 266Mhz (or 200MHz) when the AHB is dropped to 66.5MHz. The DDR freq change will be initiated only when the EPDC clock is not active. So there will be brief periods of time when DDR is at 266Mhz even when AHB is at 66.5Mhz and DDR will be at 133Mhz even when AHB is at 133Mhz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-16ENGR00136941 MX50: Fix crash issue caused by ePxP when playback videoRobby Cai
The root cause is list_del() are called twice on same entry in pxp irq handler. Remove latter one fixes this issue. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-15ENGR00136939-2: MX50: Fix suspend/resume issue on MX50 RDPRanjani Vaidyanathan
Register SPI device first so that it will be the last device to be suspended and first device to be resumed. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-15ENGR00136939-1: SPI:Fix suspend/resume issue on MX50 RDPRanjani Vaidyanathan
Fixed the SPI driver suspend/resume code. The SPI driver was missing releasing the spin lock in certain conditions.In the resume code, the master bit needs to be set while re-enabling the spi. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-15ENGR00136990-2 MX50: Add sys interface to control ZQ calib run intervalRobby Cai
By default, dynamic ZQ calibration runs by interval of 10 seconds. This interval can be changed via Sys, for example 5 seconds, echo 5 > /sys/devices/platform/mxc_zq_calib/interval Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-15ENGR00136990-1 MX50: fix system resume failure issue due to ZQ calibrationRobby Cai
need to make sure last ZQ calib run completed and no more ZQ calib to be run during suspend, and resume ZQ calib until the system resumes. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-14ENGR00136942 FEC: Fix resume fec trigger transmit timeoutZeng Zhaoming
Set carrier flag to off when suspend, to avoid kernel warning about sending timeout. Reported-by: Peter Chen <peter.chen@freescale.com> Tested-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
2010-12-14ENGR00136921 FEC: Fix nfs not works after kernel suspend and resume on i.MX28Zeng Zhaoming
Fec phy state changing occurs in delay works, which in normal task context. And package sending mostly happens in softirq context, only happens in ksoftirq while network traffic is heavy and some _many retries_ situation. Linux network qdisc code keep raising NET_TX_SOFTIRQ softirq if package not send out when netdev queue set to start. And the subsequenece process will loop in softirq context for 10ms. Since Imx28 HZ set to 100Hz, the next timer interrupt will trigger softirq again. this loop prevent network link changing to up status. And cause a chicken-egg problem. To break this loop, we need to set netdev transmit queue stop when link is down, and start it when link becomes up. commit 757bfe446bab7661d12a8772ca10b7a490c8aa47 try to resolve this problem, but hand-merge mistake introduce a power resume bug. Reported-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
2010-12-13ENGR00136875-2 make video buffer cacheable to improve video performanceRobby Cai
Use pgprot_writethru() instead of pgprot_noncached() Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-13ENGR00136875-1 Add function pgprot_writethru()Robby Cai
Added pgprot_writethru(), to set the buffer's cache property as writethrough. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-10ENGR00136231: Read MAC ID from the IIM fuses for SMSC911x driverDinh Nguyen
For boards that use the SMSC 911x ethernet driver, the MAC ID for the ethernet controller was randomly being generated. It should get the MAC ID from the IIM fuses that are blown to show the correct MAC ID. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
2010-12-10ENGR00136190: MX50 RD1: Incorrect IOMUX settings break WVGA displayRanjani Vaidyanathan
Setting DSE to high and ODE bits in I2C3_SDA IOMUX pad causes WVGA to fail. Fix is to use the default values for pad control. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-11ENGR00136223 MX50 Fix epdc display issue via PAN_DISPLAY after resumeRobby Cai
Problem ======== In suspend/resume cycle, info->var.xoffset and info->var.yoffset will be reset to 0 (in function fbcon_switch). After reume, if the xoffset/yoffset of update region happens to be 0/0, this region will not be displayed. Resolution ========== Should not compare new offset with previous offset, but compare new panning/offset state with previous state in pan_display function to determine whether need to update fb_offset. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-10ENGR00136219 MX28: Fix keypad can't wake up systemFrank Li
Fix keypad can't wake up system Signed-off-by: Frank Li <Frank.Li@freescale.com>
2010-12-10ENGR00136218 FEC: Fix dhcp fail when enable preempt at mx28Frank Li
DHCP fail when enable NO_HZ and preempt at mx28evk Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
2010-12-10ENGR00136202 MX50: Finetune DLL delay paramater for LPDDR2Robby Cai
Changed DLL delay from 0x14 to 0x0b Swapped pu and (pu+1), pd and (pd+1) assignment in CFG1 and CFG2. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-10ENGR00136195 MX28-MSL: fix AHB clock divider issuePeter Chen
Also fix the suspend/resume issue when CPU running @261818000Hz Signed-off-by: Peter Chen <peter.chen@freescale.com>
2010-12-09ENGR00134274 - EPDC fb: Optimize update flow by merging compatible updatesDanny Nold
- Created a worker thread to centralize all update requests (new and collisions) - Added routine to merge compatible updates - Separated PXP processing from update ioctl and ISR flows into workqueue flow - Added IOCTL to turn control the update scheme. Supported schemes are snapshot mode (the old update scheme), queued mode, and queued mode with combining. - Added collision-handling refinement based on update submission order - Added support for 8bpp setting from kernel command line option Signed-off-by: Danny Nold <dannynold@freescale.com>
2010-12-09ENGR00136170 MX50: Add ZQ calibration revision for TO1.1Robby Cai
LPDDR2 ZQ calibration is different from mDDR/DDR2 in this version. The patch added a workaround to get appropriate pu/pd value for h/w. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-09ENGR00136108 PTP: Revise and supplement for MX53 1588 driverXie Xiaobo
1. Using the UDP dest port to identifying an event message. 2. Add related information checking for getting rx/tx timestamp. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2010-12-09ENGR00136101-2 MX50: Only kick the clock off timer in irq handler.Robby Cai
Here 'kick' means start the timer or postpone the timer. By only kicking the timer in irq handler only when no task pending in the queue, rather than each time we submit a new task, it should perform better. Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-09ENGR00136101-1 MX50: Export timeout value to turn off ePxP clock when inactiveRobby Cai
Usage (timeout in millisecond, default is 600): echo 2000 > /sys/devices/platform/mxc-pxp/clk_off_timeout Signed-off-by: Robby Cai <R63905@freescale.com>
2010-12-09ENGR00136150 IIM:Remap user defined size of IIM registersLiu Ying
This patch remaps user defined size of IIM registers from IIM base address. Signed-off-by: Liu Ying <b17645@freescale.com>
2010-12-08ENGR00136146-2 MX53 TO2 ARD: Changed R2 value for reulator SW2 and LDO2Nancy Chen
LTC3589: Changed R2 value for reulator SW2 and LDO2. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2010-12-08ENGR00136146-1 MX53 TO2 ARD: Change VDDGP and VCC valuesNancy Chen
1. Changed VDDGP voltage to 1.0V as CPU freq is 160MHz. 2. Changed suspend values of VDDGP and VCC back to 0.95V as HW issue has been resolved. Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2010-12-08ENGR00136097-2 mx50 rdp: add support to addon board's power key eventXinyu Chen
Register the PWRON3 event when probe the power key device. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2010-12-08ENGR00136097-1 pmic mc13892: Add PWRON3 power event supportXinyu Chen
Enable the PWRON3 event in mc13892. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
2010-12-07ENGR00135971 GPU: move clk_enable/disable out of timer handlerRichard Zhao
For timer based power autogating, we have to move clk_enable/disable out of timer handler, because they become may sleep. Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
2010-12-07ENGR00135975 usb: Add protection for resume routine for udc driverPeter Chen
At usb otg mode, the fsl_udc_resume will be called at otg_set_host and otg_set_peripheral. So we needs to add mutex_lock for fsl_udc_resume to protect being called at the same time. Besides, the fsl_udc_resume should not be called continuous twice, or the udc->suspended will be wrong Signed-off-by: Peter Chen <peter.chen@freescale.com>
2010-12-06ENGR00136022: MXC:Fixed bugs in bus_frequency driver.Ranjani Vaidyanathan
Fix MX53 boot issue caused by the changes made to bus_freq driver. Ensure that all MX5x platforms can enter/exit various low power modes. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-06ENGR00136004 iMX28: set NO_HZ and preempt as default configFrank Li
Enable NO_HZ and PREEMPT as default config for mx28 Signed-off-by: Frank Li <Frank.Li@freescale.com>
2010-12-06ENGR00134193-2 MX28: Fix FEC can't found phy after fix timer issueFrank Li
mdelay(10) actually delay 50ms before fix timer issue. After fix timer issue. It should set to 50ms Signed-off-by: Frank Li <Frank.Li@freescale.com>
2010-12-06ENGR00134193-1 TIMER: Fix i.MX28 set wrong match value of timerFrank Li
It should be match = current - delta. Original code is match = last_match -delta. Signed-off-by: Frank Li <Frank.Li@freescale.com>
2010-12-06ENGR00134285 LDB:Correct the way to match registered fb infoLiu Ying
In the probe function of LDB framebuffer driver, we will try to match the LVDS video modes defined in the driver. For LDB separate mode, we need to find two video modes matched, whereas, for other LDB modes, we need to find only one video mode matched. Signed-off-by: Liu Ying <b17645@freescale.com>
2010-12-04ENGR00135048-2: MX50: Added support for bus-frequency scaling.Ranjani Vaidyanathan
Add the capability to change the bus clocks at half the max frequency based on which modules are active. AHB_CLK, AXI_A and AXI_B clock are at half the max. DDR is left at 266MHz(LPDDR2)/200MHz (mDDR). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2010-12-04ENGR00135048-1: Fixed bugs in common sw bus frequency scaling code.Ranjani Vaidyanathan
Some GPC bits were getting set twice, fixed the issue. Protected the section where CPU frequency is changed. For MX50, increase the cpu frequency along with increasing the bus frequency. Fixed the test conditions under which bus frequency should be set to low, medium or high setpoint. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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