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authorEric Miao <eric.miao@linaro.org>2011-04-26 10:20:39 +0800
committerEric Miao <eric.miao@linaro.org>2011-04-26 10:23:45 +0800
commit9303d2964da98e259b17feb5ea7e099db5a53190 (patch)
tree6363be747ff11e80c4d5fc16e405bac45703a811
parent65d4c8ea42973637e5a1ae06204d369ec6d74404 (diff)
SAUCE: MX5: fix possible panic due to incorrectly calculated timeout
BugLink: http://bugs.launchpad.net/bugs/768373 Signed-off-by: Eric Miao <eric.miao@linaro.org>
-rw-r--r--arch/arm/mach-mx5/clock.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index adf9d9a49ef7..974b8e34fac9 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -5176,6 +5176,7 @@ static int cpu_clk_set_op(int op)
struct cpu_op *p;
u32 reg, pll_hfsm;
u32 stat;
+ int relock_timeout = 10;
if (op == cpu_curr_op)
return 0;
@@ -5242,14 +5243,12 @@ static int cpu_clk_set_op(int op)
__raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
/* Wait for the PLL to lock */
- getnstimeofday(&nstimeofday);
do {
- getnstimeofday(&curtime);
- if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
- panic("pll1 relock failed\n");
- stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) &
- MXC_PLL_DP_CTL_LRF;
- } while (!stat);
+ stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ if (stat & MXC_PLL_DP_CTL_LRF)
+ break;
+ udelay(100);
+ } while (--relock_timeout);
reg = __raw_readl(MXC_CCM_CCSR);
/* Move the PLL1 back to the pll1_main_clk */