From f461b8a322b7eea954b9f3dee139ce5bb3a6a8d0 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 17 Nov 2010 13:58:57 +0000 Subject: ARM: Set bit 22 in the PL310 (cache controller) AuxCtlr register Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This patch ensures that bit 22 is set in the l2x0_init() function if PL310 and not rely on the platform code to specify it. It also modifies the 'aux' variable only if the actual register is written so that the final printk displays the real hardware value. Signed-off-by: Catalin Marinas Signed-off-by: Nicolas Pitre --- arch/arm/mm/cache-l2x0.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ef59099a546..ae251209b8f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -283,9 +283,6 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); - aux &= aux_mask; - aux |= aux_val; - /* Determine the number of ways */ switch (cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: @@ -294,6 +291,13 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) else ways = 8; type = "L310"; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + aux_val |= 1 << 22; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; @@ -321,6 +325,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) * accessing the below registers will fault. */ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { + aux &= aux_mask; + aux |= aux_val; /* l2x0 controller is disabled */ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); -- cgit v1.2.3