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-rw-r--r--arch/ppc/kernel/head_44x.S12
-rw-r--r--arch/ppc/kernel/misc.S3
-rw-r--r--arch/ppc/platforms/4xx/ebony.c6
-rw-r--r--arch/ppc/platforms/4xx/ebony.h13
-rw-r--r--arch/ppc/platforms/4xx/ocotea.c4
-rw-r--r--arch/ppc/platforms/4xx/ocotea.h13
-rw-r--r--arch/ppc64/kernel/misc.S6
-rw-r--r--arch/x86_64/lib/csum-copy.S2
8 files changed, 47 insertions, 12 deletions
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 6c7ae605246..72ee8f33bde 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -179,14 +179,14 @@ skpinv: addi r4,r4,1 /* Increment */
4:
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/*
- * Add temporary UART mapping for early debug. This
- * mapping must be identical to that used by the early
- * bootloader code since the same asm/serial.h parameters
- * are used for polled operation.
+ * Add temporary UART mapping for early debug.
+ * We can map UART registers wherever we want as long as they don't
+ * interfere with other system mappings (e.g. with pinned entries).
+ * For an example of how we handle this - see ocotea.h. --ebs
*/
/* pageid fields */
lis r3,UART0_IO_BASE@h
- ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
+ ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K
/* xlat fields */
lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
@@ -196,7 +196,7 @@ skpinv: addi r4,r4,1 /* Increment */
li r5,0
ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
- li r0,1 /* TLB slot 1 */
+ li r0,0 /* TLB slot 0 */
tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 191a8def3bd..c2fb85b49a1 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1451,3 +1451,6 @@ _GLOBAL(sys_call_table)
.long sys_waitid
.long sys_ioprio_set
.long sys_ioprio_get
+ .long sys_inotify_init /* 275 */
+ .long sys_inotify_add_watch
+ .long sys_inotify_rm_watch
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index cd11734ef7c..509e69a095f 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -7,7 +7,7 @@
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
+ * Copyright (c) 2003-2005 Zultys Technologies
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -50,6 +50,7 @@
#include <asm/bootinfo.h>
#include <asm/ppc4xx_pic.h>
#include <asm/ppcboot.h>
+#include <asm/tlbflush.h>
#include <syslib/gen550.h>
#include <syslib/ibm440gp_common.h>
@@ -248,6 +249,9 @@ ebony_early_serial_map(void)
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &port);
+
+ /* Purge TLB entry added in head_44x.S for early serial access */
+ _tlbie(UART0_IO_BASE);
#endif
port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index 47c391c9174..d08faa46a0a 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -56,9 +56,18 @@
* Serial port defines
*/
-/* OpenBIOS defined UART mappings, used before early_serial_setup */
+#if defined(__BOOTER__)
+/* OpenBIOS defined UART mappings, used by bootloader shim */
#define UART0_IO_BASE 0xE0000200
#define UART1_IO_BASE 0xE0000300
+#else
+/* head_44x.S created UART mapping, used before early_serial_setup.
+ * We cannot use default OpenBIOS UART mappings because they
+ * don't work for configurations with more than 512M RAM. --ebs
+ */
+#define UART0_IO_BASE 0xF0000200
+#define UART1_IO_BASE 0xF0000300
+#endif
/* external Epson SG-615P */
#define BASE_BAUD 691200
@@ -66,7 +75,7 @@
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: UART##num##_IO_BASE, \
+ iomem_base: (void*)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 5f82a6bc704..8fc34a34476 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -48,6 +48,7 @@
#include <asm/bootinfo.h>
#include <asm/ppc4xx_pic.h>
#include <asm/ppcboot.h>
+#include <asm/tlbflush.h>
#include <syslib/gen550.h>
#include <syslib/ibm440gx_common.h>
@@ -266,6 +267,9 @@ ocotea_early_serial_map(void)
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &port);
+
+ /* Purge TLB entry added in head_44x.S for early serial access */
+ _tlbie(UART0_IO_BASE);
#endif
port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
index 202dc825119..33251153ac5 100644
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -55,15 +55,24 @@
*/
#define RS_TABLE_SIZE 2
-/* OpenBIOS defined UART mappings, used before early_serial_setup */
+#if defined(__BOOTER__)
+/* OpenBIOS defined UART mappings, used by bootloader shim */
#define UART0_IO_BASE 0xE0000200
#define UART1_IO_BASE 0xE0000300
+#else
+/* head_44x.S created UART mapping, used before early_serial_setup.
+ * We cannot use default OpenBIOS UART mappings because they
+ * don't work for configurations with more than 512M RAM. --ebs
+ */
+#define UART0_IO_BASE 0xF0000200
+#define UART1_IO_BASE 0xF0000300
+#endif
#define BASE_BAUD 11059200/16
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
- iomem_base: UART##num##_IO_BASE, \
+ iomem_base: (void*)UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#define SERIAL_PORT_DFNS \
diff --git a/arch/ppc64/kernel/misc.S b/arch/ppc64/kernel/misc.S
index 59f4f997381..a05b50b738e 100644
--- a/arch/ppc64/kernel/misc.S
+++ b/arch/ppc64/kernel/misc.S
@@ -1129,6 +1129,9 @@ _GLOBAL(sys_call_table32)
.llong .compat_sys_waitid
.llong .sys32_ioprio_set
.llong .sys32_ioprio_get
+ .llong .sys_inotify_init /* 275 */
+ .llong .sys_inotify_add_watch
+ .llong .sys_inotify_rm_watch
.balign 8
_GLOBAL(sys_call_table)
@@ -1407,3 +1410,6 @@ _GLOBAL(sys_call_table)
.llong .sys_waitid
.llong .sys_ioprio_set
.llong .sys_ioprio_get
+ .llong .sys_inotify_init /* 275 */
+ .llong .sys_inotify_add_watch
+ .llong .sys_inotify_rm_watch
diff --git a/arch/x86_64/lib/csum-copy.S b/arch/x86_64/lib/csum-copy.S
index 01808ec3783..72fd55ee896 100644
--- a/arch/x86_64/lib/csum-copy.S
+++ b/arch/x86_64/lib/csum-copy.S
@@ -188,8 +188,8 @@ csum_partial_copy_generic:
source
movw (%rdi),%bx
adcl %ebx,%eax
- dest
decl %ecx
+ dest
movw %bx,(%rsi)
leaq 2(%rdi),%rdi
leaq 2(%rsi),%rsi
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 07:43:34 +0000