diff options
| -rw-r--r-- | arch/arm/mach-omap2/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.c | 253 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.h | 132 |
3 files changed, 386 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e4c9bb3ad89..8ef8711eac9 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -137,6 +137,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o # L3 interconnect obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o +obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c new file mode 100644 index 00000000000..82632c24076 --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_noc.c @@ -0,0 +1,253 @@ +/* + * OMAP4XXX L3 Interconnect error handling driver + * + * Copyright (C) 2011 Texas Corporation + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Sricharan <r.sricharan@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/slab.h> + +#include "omap_l3_noc.h" + +/* + * Interrupt Handler for L3 error detection. + * 1) Identify the L3 clockdomain partition to which the error belongs to. + * 2) Identify the slave where the error information is logged + * 3) Print the logged information. + * 4) Add dump stack to provide kernel trace. + * + * Two Types of errors : + * 1) Custom errors in L3 : + * Target like DMM/FW/EMIF generates SRESP=ERR error + * 2) Standard L3 error: + * - Unsupported CMD. + * L3 tries to access target while it is idle + * - OCP disconnect. + * - Address hole error: + * If DSS/ISS/FDIF/USBHOSTFS access a target where they + * do not have connectivity, the error is logged in + * their default target which is DMM2. + * + * On High Secure devices, firewall errors are possible and those + * can be trapped as well. But the trapping is implemented as part + * secure software and hence need not be implemented here. + */ +static irqreturn_t l3_interrupt_handler(int irq, void *_l3) +{ + + struct omap4_l3 *l3 = _l3; + int inttype, i, j; + int err_src = 0; + u32 std_err_main_addr, std_err_main, err_reg; + u32 base, slave_addr, clear; + char *source_name; + + /* Get the Type of interrupt */ + if (irq == l3->app_irq) + inttype = L3_APPLICATION_ERROR; + else + inttype = L3_DEBUG_ERROR; + + for (i = 0; i < L3_MODULES; i++) { + /* + * Read the regerr register of the clock domain + * to determine the source + */ + base = (u32)l3->l3_base[i]; + err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); + + /* Get the corresponding error and analyse */ + if (err_reg) { + /* Identify the source from control status register */ + for (j = 0; !(err_reg & (1 << j)); j++) + ; + + err_src = j; + /* Read the stderrlog_main_source from clk domain */ + std_err_main_addr = base + (*(l3_targ[i] + err_src)); + std_err_main = readl(std_err_main_addr); + + switch ((std_err_main & CUSTOM_ERROR)) { + case STANDARD_ERROR: + source_name = + l3_targ_stderrlog_main_name[i][err_src]; + + slave_addr = std_err_main_addr + + L3_SLAVE_ADDRESS_OFFSET; + WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", + source_name, readl(slave_addr)); + /* clear the std error log*/ + clear = std_err_main | CLEAR_STDERR_LOG; + writel(clear, std_err_main_addr); + break; + + case CUSTOM_ERROR: + source_name = + l3_targ_stderrlog_main_name[i][err_src]; + + WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", + source_name); + /* clear the std error log*/ + clear = std_err_main | CLEAR_STDERR_LOG; + writel(clear, std_err_main_addr); + break; + + default: + /* Nothing to be handled here as of now */ + break; + } + /* Error found so break the for loop */ + break; + } + } + return IRQ_HANDLED; +} + +static int __init omap4_l3_probe(struct platform_device *pdev) +{ + static struct omap4_l3 *l3; + struct resource *res; + int ret; + int irq; + + l3 = kzalloc(sizeof(*l3), GFP_KERNEL); + if (!l3) + ret = -ENOMEM; + + platform_set_drvdata(pdev, l3); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 0\n"); + ret = -ENODEV; + goto err1; + } + + l3->l3_base[0] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[0])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err2; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 1\n"); + ret = -ENODEV; + goto err3; + } + + l3->l3_base[1] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[1])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err4; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 2\n"); + ret = -ENODEV; + goto err5; + } + + l3->l3_base[2] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[2])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err6; + } + + /* + * Setup interrupt Handlers + */ + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, + l3_interrupt_handler, + IRQF_DISABLED, "l3-dbg-irq", l3); + if (ret) { + pr_crit("L3: request_irq failed to register for 0x%x\n", + OMAP44XX_IRQ_L3_DBG); + goto err7; + } + l3->debug_irq = irq; + + irq = platform_get_irq(pdev, 1); + ret = request_irq(irq, + l3_interrupt_handler, + IRQF_DISABLED, "l3-app-irq", l3); + if (ret) { + pr_crit("L3: request_irq failed to register for 0x%x\n", + OMAP44XX_IRQ_L3_APP); + goto err8; + } + l3->app_irq = irq; + + goto err0; +err8: +err7: + iounmap(l3->l3_base[2]); +err6: +err5: + iounmap(l3->l3_base[1]); +err4: +err3: + iounmap(l3->l3_base[0]); +err2: +err1: + kfree(l3); +err0: + return ret; +} + +static int __exit omap4_l3_remove(struct platform_device *pdev) +{ + struct omap4_l3 *l3 = platform_get_drvdata(pdev); + + free_irq(l3->app_irq, l3); + free_irq(l3->debug_irq, l3); + iounmap(l3->l3_base[0]); + iounmap(l3->l3_base[1]); + iounmap(l3->l3_base[2]); + kfree(l3); + + return 0; +} + +static struct platform_driver omap4_l3_driver = { + .remove = __exit_p(omap4_l3_remove), + .driver = { + .name = "omap_l3_noc", + }, +}; + +static int __init omap4_l3_init(void) +{ + return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe); +} +postcore_initcall_sync(omap4_l3_init); + +static void __exit omap4_l3_exit(void) +{ + platform_driver_unregister(&omap4_l3_driver); +} +module_exit(omap4_l3_exit); diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h new file mode 100644 index 00000000000..359b83348ae --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_noc.h @@ -0,0 +1,132 @@ + /* + * OMAP4XXX L3 Interconnect error handling driver header + * + * Copyright (C) 2011 Texas Corporation + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * sricharan <r.sricharan@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H + +/* + * L3 register offsets + */ +#define L3_MODULES 3 +#define CLEAR_STDERR_LOG (1 << 31) +#define CUSTOM_ERROR 0x2 +#define STANDARD_ERROR 0x0 +#define INBAND_ERROR 0x0 +#define EMIF_KERRLOG_OFFSET 0x10 +#define L3_SLAVE_ADDRESS_OFFSET 0x14 +#define LOGICAL_ADDR_ERRORLOG 0x4 +#define L3_APPLICATION_ERROR 0x0 +#define L3_DEBUG_ERROR 0x1 + +u32 l3_flagmux[L3_MODULES] = { + 0x50C, + 0x100C, + 0X020C +}; + +/* + * L3 Target standard Error register offsets + */ +u32 l3_targ_stderrlog_main_clk1[] = { + 0x148, /* DMM1 */ + 0x248, /* DMM2 */ + 0x348, /* ABE */ + 0x448, /* L4CFG */ + 0x648 /* CLK2 PWR DISC */ +}; + +u32 l3_targ_stderrlog_main_clk2[] = { + 0x548, /* CORTEX M3 */ + 0x348, /* DSS */ + 0x148, /* GPMC */ + 0x448, /* ISS */ + 0x748, /* IVAHD */ + 0xD48, /* missing in TRM corresponds to AES1*/ + 0x948, /* L4 PER0*/ + 0x248, /* OCMRAM */ + 0x148, /* missing in TRM corresponds to GPMC sERROR*/ + 0x648, /* SGX */ + 0x848, /* SL2 */ + 0x1648, /* C2C */ + 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ + 0xF48, /* missing in TRM corrsponds to SHA1*/ + 0xE48, /* missing in TRM corresponds to AES2*/ + 0xC48, /* L4 PER3 */ + 0xA48, /* L4 PER1*/ + 0xB48 /* L4 PER2*/ +}; + +u32 l3_targ_stderrlog_main_clk3[] = { + 0x0148 /* EMUSS */ +}; + +char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { + { + "DMM1", + "DMM2", + "ABE", + "L4CFG", + "CLK2 PWR DISC", + }, + { + "CORTEX M3" , + "DSS ", + "GPMC ", + "ISS ", + "IVAHD ", + "AES1", + "L4 PER0", + "OCMRAM ", + "GPMC sERROR", + "SGX ", + "SL2 ", + "C2C ", + "PWR DISC CLK1", + "SHA1", + "AES2", + "L4 PER3", + "L4 PER1", + "L4 PER2", + }, + { + "EMUSS", + }, +}; + +u32 *l3_targ[L3_MODULES] = { + l3_targ_stderrlog_main_clk1, + l3_targ_stderrlog_main_clk2, + l3_targ_stderrlog_main_clk3, +}; + +struct omap4_l3 { + struct device *dev; + struct clk *ick; + + /* memory base */ + void __iomem *l3_base[4]; + + int debug_irq; + int app_irq; +}; + +#endif |