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authorRaghuveer Murthy <raghuveer.murthy@ti.com>2011-05-03 12:18:10 +0800
committerRicardo Salveti de Araujo <ricardo.salveti@canonical.com>2011-05-16 22:42:10 -0300
commit83b5e39b4d67d799be52e9f4f90c07986929fecd (patch)
treea6c35ca08de8d6d3838d19aceea01fdb2def8645 /drivers
parente9c997e03320db8b10d163800bccdee7a960ed13 (diff)
downloadlinux-linaro-android-83b5e39b4d67d799be52e9f4f90c07986929fecd.tar.gz
OMAP: DSS2: Adding macro for DISPC_DIVISOR register
Added macro for DISPC_DIVISOR. This is different from DISPC_DIVISOR1 and DISPC_DIVISOR2. OMAP4 supports all the above 3 registers. DISPC_DIVISOR1 and DISPC_DIVISOR2 registers are accessed through DISPC_DIVISORo(ch) macro Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/omap2/dss/dispc.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7804779c9da..abfe4b0bbdb 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -128,6 +128,16 @@ struct dispc_reg { u16 idx; };
#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
+/*
+ * The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
+ * However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK.
+ * This allows DISPC_CORE_CLK to be independent of logical clock dividers (lcd)
+ * of LCD1 (primary) and LCD2 (secondary) displays.
+ *
+ * To derive pixel clocks for Primary and Secondary LCD channels, configure the
+ * lcd and pcd in DISPC_DIVISOR1 and DISPC_DIVISOR2 respectively, using the
+ * DISPC_DIVISORo(ch).
+ */
#define DISPC_DIVISOR DISPC_REG(0x0804)
#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \