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authorDaniel Vetter <daniel.vetter@ffwll.ch>2011-02-22 18:25:49 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2011-02-24 00:33:49 +0000
commitc2e0eb167070a6e9dcb49c84c13c79a30d672431 (patch)
tree3adb50528eb95cb0c7df47b0231f1a3b2ee60b5e /drivers/char
parent011b9910bdaf2e52c48c012490ab444fceea1959 (diff)
drm/i915: fix corruptions on i8xx due to relaxed fencing
It looks like gen2 has a peculiar interleaved 2-row inter-tile layout. Probably inherited from i81x which had 2kb tiles (which naturally fit an even-number-of-tile-rows scheme to fit onto 4kb pages). There is no other mention of this in any docs (also not in the Intel internal documention according to Chris Wilson). Problem manifests itself in corruptions in the second half of the last tile row (if the bo has an odd number of tiles). Which can only happen with relaxed tiling (introduced in a00b10c360b35d6431a9). So reject set_tiling calls that don't satisfy this constrain to prevent broken userspace from causing havoc. While at it, also check the size for newer chipsets. LKML: https://lkml.org/lkml/2011/2/19/5 Reported-by: Indan Zupancic <indan@nul.nu> Tested-by: Indan Zupancic <indan@nul.nu> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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