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authorDave Airlie <airlied@gmail.com>2011-01-12 10:49:03 +1000
committerDave Airlie <airlied@gmail.com>2011-01-12 10:49:03 +1000
commit784fe39fa80d557847baeca2695915d17b09827f (patch)
treea258083fb42459b6f5415e397c0ce551713fc1ed /drivers/char
parent4162cf64973df51fc885825bc9ca4d055891c49f (diff)
parent6fe4f14044f181e146cdc15485428f95fa541ce8 (diff)
downloadlinux-linaro-android-784fe39fa80d557847baeca2695915d17b09827f.tar.gz
Merge branch 'drm-intel-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel
* 'drm-intel-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: (37 commits) drm/i915/execbuffer: Reorder binding of objects to favour restrictions drm/i915: If we hit OOM when allocating GTT pages, clear the aperture drm/i915/evict: Ensure we completely cleanup on failure drm/i915/execbuffer: Correctly clear the current object list upon EFAULT drm/i915/debugfs: Show all objects in the gtt drm/i915: Record AGP memory type upon error drm/i915: Periodically flush the active lists and requests drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTT drm/i915: Record the error batchbuffer on each ring drm/i915: Include TLB miss overhead for computing WM drm/i915: Propagate error from flushing the ring drm/i915: detect & report PCH display error interrupts drm/i915: cleanup rc6 code drm/i915: fix rc6 enabling around suspend/resume drm/i915: re-enable rc6 support for Ironlake+ drm/i915: Make the ring IMR handling private drm/i915/ringbuffer: Simplify the ring irq refcounting drm/i915/debugfs: Show the per-ring IMR drm/i915: Mask USER interrupts on gen6 (until required) drm/i915: Handle ringbuffer stalls when flushing ...
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-agp.h2
-rw-r--r--drivers/char/agp/intel-gtt.c9
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 010e3defd6c..c195bfeade1 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -94,6 +94,8 @@
#define G4x_GMCH_SIZE_VT_1_5M (0xa << 8)
#define G4x_GMCH_SIZE_VT_2M (0xc << 8)
+#define GFX_FLSH_CNTL 0x2170 /* 915+ */
+
#define I810_DRAM_CTL 0x3000
#define I810_DRAM_ROW_0 0x00000001
#define I810_DRAM_ROW_0_SDRAM 0x00000001
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 356f73e0d17..da8161806f3 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -814,6 +814,12 @@ static bool intel_enable_gtt(void)
}
}
+ /* On the resume path we may be adjusting the PGTBL value, so
+ * be paranoid and flush all chipset write buffers...
+ */
+ if (INTEL_GTT_GEN >= 3)
+ writel(0, intel_private.registers+GFX_FLSH_CNTL);
+
reg = intel_private.registers+I810_PGETBL_CTL;
writel(intel_private.PGETBL_save, reg);
if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
@@ -823,6 +829,9 @@ static bool intel_enable_gtt(void)
return false;
}
+ if (INTEL_GTT_GEN >= 3)
+ writel(0, intel_private.registers+GFX_FLSH_CNTL);
+
return true;
}