aboutsummaryrefslogtreecommitdiff
path: root/board/esd/pci405/writeibm.S
blob: 9f5c35b5877c572e5c537e67dd043d24ffd794df (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
/*------------------------------------------------------------------------------+ */
/* */
/*       This source code has been made available to you by IBM on an AS-IS */
/*       basis.  Anyone receiving this source is licensed under IBM */
/*       copyrights to use it in any way he or she deems fit, including */
/*       copying it, modifying it, compiling it, and redistributing it either */
/*       with or without modifications.  No license under IBM patents or */
/*       patent applications is to be implied by the copyright license. */
/* */
/*       Any user of this software should understand that IBM cannot provide */
/*       technical support for this software and will not be responsible for */
/*       any consequences resulting from the use of this software. */
/* */
/*       Any person who transfers this source code or any derivative work */
/*       must include the IBM copyright notice, this paragraph, and the */
/*       preceding two paragraphs in the transferred software. */
/* */
/*       COPYRIGHT   I B M   CORPORATION 1995 */
/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */

/*----------------------------------------------------------------------------- */
/* Function:     ext_bus_cntlr_init */
/* Description:  Initializes the External Bus Controller for the external */
/*		peripherals. IMPORTANT: For pass1 this code must run from */
/*		cache since you can not reliably change a peripheral banks */
/*		timing register (pbxap) while running code from that bank. */
/*		For ex., since we are running from ROM on bank 0, we can NOT */
/*		execute the code that modifies bank 0 timings from ROM, so */
/*		we run it from cache. */
/*	Bank 0 - Flash and SRAM */
/*	Bank 1 - NVRAM/RTC */
/*	Bank 2 - Keyboard/Mouse controller */
/*	Bank 3 - IR controller */
/*	Bank 4 - not used */
/*	Bank 5 - not used */
/*	Bank 6 - not used */
/*	Bank 7 - FPGA registers */
/*----------------------------------------------------------------------------- */
#include <ppc4xx.h>

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>


	.globl	write_without_sync
write_without_sync:
		/*
		 * Write one values to host via pci busmastering
		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
		 * *ptr = 0x01234567;
		 */
	addi    r31,0,0
	lis     r31,0xc000

start1:
	lis     r0,0x0123
	ori     r0,r0,0x4567
	stw     r0,0(r31)

		/*
		 * Read one value back
		 * ptr = (volatile unsigned long *)addr;
		 * val = *ptr;
		 */

	lwz     r0,0(r31)

		/*
		 * One pci config write
		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
		 */
		/* subsystem id */

	li      r4,0x002C
	oris    r4,r4,0x8000
	lis     r3,0xEEC0
	stwbrx  r4,0,r3

	li      r5,0x1234
	ori     r3,r3,0x4
	stwbrx  r5,0,r3

	b       start1

	blr	/* never reached !!!! */

	.globl	write_with_sync
write_with_sync:
		/*
		 * Write one values to host via pci busmastering
		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
		 * *ptr = 0x01234567;
		 */
	addi    r31,0,0
	lis     r31,0xc000

start2:
	lis     r0,0x0123
	ori     r0,r0,0x4567
	stw     r0,0(r31)

		/*
		 * Read one value back
		 * ptr = (volatile unsigned long *)addr;
		 * val = *ptr;
		 */

	lwz     r0,0(r31)

		/*
		 * One pci config write
		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
		 */
		/* subsystem id */

	li      r4,0x002C
	oris    r4,r4,0x8000
	lis     r3,0xEEC0
	stwbrx  r4,0,r3
	sync

	li      r5,0x1234
	ori     r3,r3,0x4
	stwbrx  r5,0,r3
	sync

	b       start2

	blr	/* never reached !!!! */

	.globl	write_with_less_sync
write_with_less_sync:
		/*
		 * Write one values to host via pci busmastering
		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
		 * *ptr = 0x01234567;
		 */
	addi    r31,0,0
	lis     r31,0xc000

start2b:
	lis     r0,0x0123
	ori     r0,r0,0x4567
	stw     r0,0(r31)

		/*
		 * Read one value back
		 * ptr = (volatile unsigned long *)addr;
		 * val = *ptr;
		 */

	lwz     r0,0(r31)

		/*
		 * One pci config write
		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
		 */
		/* subsystem id */

	li      r4,0x002C
	oris    r4,r4,0x8000
	lis     r3,0xEEC0
	stwbrx  r4,0,r3
	sync

	li      r5,0x1234
	ori     r3,r3,0x4
	stwbrx  r5,0,r3
/*        sync */

	b       start2b

	blr	/* never reached !!!! */

	.globl	write_with_more_sync
write_with_more_sync:
		/*
		 * Write one values to host via pci busmastering
		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
		 * *ptr = 0x01234567;
		 */
	addi    r31,0,0
	lis     r31,0xc000

start3:
	lis     r0,0x0123
	ori     r0,r0,0x4567
	stw     r0,0(r31)
	sync

		/*
		 * Read one value back
		 * ptr = (volatile unsigned long *)addr;
		 * val = *ptr;
		 */

	lwz     r0,0(r31)
	sync

		/*
		 * One pci config write
		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
		 */
		/* subsystem id (PCIC0_SBSYSVID)*/

	li      r4,0x002C
	oris    r4,r4,0x8000
	lis     r3,0xEEC0
	stwbrx  r4,0,r3
	sync

	li      r5,0x1234
	ori     r3,r3,0x4
	stwbrx  r5,0,r3
	sync

	b       start3

	blr	/* never reached !!!! */