From 9e0081d573442e7234355f0a043218d15df03933 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 08:43:07 +0000 Subject: mx31: Fix PDR0_CSI_PODF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- include/configs/mx31pdk.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index b272674f8..223b5b0bb 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -203,11 +203,11 @@ /* Configuration of lowlevel_init.S (clocks and SDRAM) */ #define CCM_CCMR_SETUP 0x074B0BF5 -#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0)) -#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ + PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ + PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ + PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ PLL_MFN(12)) #define ESDMISC_MDDR_SETUP 0x00000004 -- cgit v1.2.3