From 7e4a0d25ed18f6437bdf59ebfa49bb0edc2f24e6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Mar 2008 09:36:47 +0100 Subject: ppc4xx: Enable ECC on LWMON5 Since all ECC related problems seem to be resolved on LWMON5, this patch now enables ECC support. We have to write the ECC bytes by zeroing and flushing in smaller steps, since the whole 256MByte takes too long for the external watchdog. Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 90 ++++++++++++---------------------------------------- 1 file changed, 20 insertions(+), 70 deletions(-) (limited to 'board/lwmon5') diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index affaeff1a..7c3cf496b 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -6,7 +6,7 @@ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -35,6 +35,7 @@ #include #include #include +#include /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory @@ -99,87 +100,37 @@ static void wait_ddr_idle(void) */ } -static void blank_string(int size) -{ - int i; - - for (i=0; i 0) { + dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + current_addr += 64 << 20; + bytes_remaining -= 64 << 20; + WATCHDOG_RESET(); } + dflush(); sync(); - eieio(); wait_ddr_idle(); /* Clear error status */ @@ -191,7 +142,6 @@ static void program_ecc(u32 start_address, mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); sync(); - eieio(); wait_ddr_idle(); } #endif -- cgit v1.2.3