From a29d69e4640ce8b12e9f77cd37263dddf7455335 Mon Sep 17 00:00:00 2001 From: Laurence Withers Date: Mon, 30 Jul 2012 23:30:35 +0000 Subject: DaVinci DA850: UART2 clock ID comes from ASYNC3 On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: Laurence Withers Cc: Tom Rini Cc: Prabhakar Lad --- arch/arm/include/asm/arch-davinci/hardware.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 89bcbbeee..674c52922 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -467,7 +467,6 @@ enum davinci_clk_ids { DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2, - DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2, /* special clock ID - output of PLL multiplier */ DAVINCI_PLLM_CLKID = 0x0FF, @@ -479,6 +478,9 @@ enum davinci_clk_ids { DAVINCI_AUXCLK_CLKID = 0x101, }; +#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ + : get_async3_src()) + #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ : get_async3_src()) -- cgit v1.2.3