AgeCommit message (Collapse)Author
2012-10-26stdio: Remove the CLPS7111 serial driverMarek Vasut
This driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26arm: Remove support for NETARMMarek Vasut
This stuff has been rotting in the tree for a while now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26arm: Remove support for s3c4510Marek Vasut
This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26arm: Remove support for lpc2292Marek Vasut
This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
2012-10-26Merge remote-tracking branch 'u-boot-atmel/master'Albert ARIBAUD
2012-10-26Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD
2012-10-25am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbersPeter Korsgaard
So other parts can be added. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25am33xx: support board specific ddr settingsPeter Korsgaard
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25am33xx: move generic parts of pinmux handling out from board/ti/am335xPeter Korsgaard
So they are available for other boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25am33xx/board: use cpu_mmc_init() for default mmc initializationPeter Korsgaard
So platforms can override it with board_mmc_init() if needed. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25am33xx: move ti i2c baseboard header handling to board/ti/am335x/Peter Korsgaard
The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25am33xx/board.c: make wdtimer/uart_base staticPeter Korsgaard
Only used here (and uart_base only for SPL). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25am33xx: Add SPI SPL as an optionTom Rini
Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25omapimage: Add support for byteswapped SPI imagesTom Rini
Add MLO.byteswap as a target to spl/Makefile and un-guard the first MLO rule so we don't have to duplicate it. Signed-off-by: Tom Rini <trini@ti.com>
2012-10-25omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPEDPeter Korsgaard
D0/D1 Swapped or not is a board property, not anything specific to the am33xx SoC, so add a custom define for it. At the same time correct the bit handling for the swapped mode (DPE0 should be cleared and SI/DPE1 set). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
2012-10-25OMAP3: add video support to the mcx boardStefano Babic
Add video support to the board with the display focaltech etm070003dh6. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-25VIDEO: add macro to set LCD size for DSS driverStefano Babic
Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2012-10-25OMAP3: mcx: updated to new hardware revisionStefano Babic
Some GPIOs differ in the new revision board. Previous revision are considered obsolete and they will not anymore supported. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-25OMAP3: updated pinmux and environment for new revision of mcx boardStefano Babic
The mcx board was slightly modified and the pinmux must be updated. There is no need to support the old board, that becomes obsolete. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-25OMAP3: mt_ventoux: power on USB at startupStefano Babic
Updated revision of the board uses GPIOs to activate the USB ports. Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-25am335x: Enable RTC 32K OSC clockVaibhav Hiremath
In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-10-24ColdFire: Add Freescale MCF54418TWR ColdFire development board supportAlison Wang
Add Freescale MCF54418TWR ColdFire development board support. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-24ColdFire: Add MCF5441x CPU supportAlison Wang
Add MCF5441x CPU support. The MCF5441x devices are a family of highly-integrated 32-bit microprocessors based on the Version 4m ColdFire microarchitecture, comprising of the V4 integer core, memory management unit(MMU) and enchanced multiply-accumulate unit(EMAC). Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-24ColdFire: Fix unused variable in cpu_init.cAlison Wang
Fix the following build warnings in cpu_init.c: cpu_init.c: In function 'cpu_init_f': cpu_init.c:47:9: warning: unused variable 'pll' cpu_init.c:46:10: warning: unused variable 'fbcs' cpu_init.c:44:10: warning: unused variable 'scm1' Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-23km83xx: add kmvect1 boardGerlando Falauto
Add support for the new kmvect1 board powered by the mpc8309 processor. As this board is very similar to the existing suvd3, instead of adding a new config header file, just add a new config option to suvd3.h Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23km83xx: add common support for km8309 boardsGerlando Falauto
Add support for Keymile boards based on mpc8309 (it would be only kmvect1 for now) Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> [#elseif -> #if to allow kmcoge5ne and kmeter1 to build successfully] Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23mpc83xx: add support for mpc8309Gerlando Falauto
This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23cleanup: introduce CONFIG_MPC830xGerlando Falauto
Introduce a new configuration token CONFIG_MPC830x to be shared among mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor existing common code so to make future introduction of 8309 simpler. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832xGerlando Falauto
simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) for qe variables with #if defined(CONFIG_QE) Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23cosmetic: suvd3: align #definesGerlando Falauto
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-23cm-t35: clean unused defines from configIgor Grinberg
Neither cm-t35, nor cm-t3730 is using OneNAND or flash. Remove the related defines from config file. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-10-23configs: Fix usage of mmc rescanAndrew Bradford
Fix usage of 'mmc rescan' by many configs. Proper use is 'mmc dev ${mmcdev}; mmc rescan' to set the mmc device and then rescan the device. 'mmc rescan' itself does not take any arguments. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
2012-10-23am33xx: Enable DDR3 for DDR3 version of beagleboneJoel A Fernandes
DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK. Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Jason Kridner <jdk@ti.com>
2012-10-23USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDYPankaj Bharadiya
The endpoint rx count register value will be zero if it is read before receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set. Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before reading endpoint rx count register. Proceed with rx count read and FIFO read only if RXPKTRDY bit is set. Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-10-22Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini
2012-10-22Merge branch 'next'Gerald Van Baren
2012-10-22Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini
2012-10-22Merge branch 'master' of git://www.denx.de/git/u-boot-mmcTom Rini
2012-10-2285xx: Protect timeout_save variable with ifdefsAndy Fleming
The timeout_save variable was only used by the DDR111_134 erratum code. It was being set, but never used. Newer compilers will actually complain about this. Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/boot: Change the compile macro for SRIO & PCIE boot master moduleLiu Gang
Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22phylib: Enable SMSC LAN87xx PHY supportMingkai Hu
LAN8720 PHY is used on Freescale C2X0QDS board. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/espi: remove write command length checkShaohui Xie
Current espi controller driver assumes the command length of write command is not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash driver such as SST does use write command length as '1', so write command on SST SPI flash will not work. And the length check for write command is not necessary for SPANSION, though it's harmless for SPANSION, it will stop write operation on flashes like SST, so we remove the check. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/fm: fix TBI PHY address settingsshaohui xie
TBI PHY address (TBIPA) register is set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1 isn't used directly, which provides MDIO for other ports. So following code is wrong in case of FM2, which has a different mac base. struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; /* Assign a Physical address to the TBI */ out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE); Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22poweprc/85xx: add QMan frequency info and fdt fixup.Haiying Wang
Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22mpc85xx/portals: Add qman and bman ip_cfg field into portal infoHaiying Wang
Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the total portal number, buffer pool number etc, we can use this info to limit those resources in kernel driver. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/t4qds: Add T4QDS boardYork Sun
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platformYork Sun
New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1York Sun
Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc85xx: Remove R6 from spin tableYork Sun
R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22powerpc/mpc8xxx: Fix DDR SPD failed messageYork Sun
Since empty DIMM slot is allowed on other than the first slot, remove the error message if SPD is not found in this case. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>