diff options
Diffstat (limited to 'cpu/mcf52x2')
-rw-r--r-- | cpu/mcf52x2/cpu.c | 70 | ||||
-rw-r--r-- | cpu/mcf52x2/cpu_init.c | 79 | ||||
-rw-r--r-- | cpu/mcf52x2/fec.c | 24 | ||||
-rw-r--r-- | cpu/mcf52x2/interrupts.c | 7 | ||||
-rw-r--r-- | cpu/mcf52x2/serial.c | 109 | ||||
-rw-r--r-- | cpu/mcf52x2/start.S | 49 |
6 files changed, 246 insertions, 92 deletions
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 8795bcccf..aa6b2bd67 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -29,6 +29,11 @@ #include <watchdog.h> #include <command.h> +#ifdef CONFIG_M5271 +#include <asm/immap_5271.h> +#include <asm/m5271.h> +#endif + #ifdef CONFIG_M5272 #include <asm/immap_5272.h> #include <asm/m5272.h> @@ -43,6 +48,42 @@ #include <asm/m5249.h> #endif +#ifdef CONFIG_M5271 +int checkcpu (void) +{ + char buf[32]; + + printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK)); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + mbar_writeByte(MCF_RCM_RCR, + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + mbar_writeShort(MCF_WTM_WSR, 0x5555); + mbar_writeShort(MCF_WTM_WSR, 0xAAAA); +} + +int watchdog_disable (void) +{ + mbar_writeShort(MCF_WTM_WCR, 0); + return (0); +} + +int watchdog_init (void) +{ + mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#endif #ifdef CONFIG_M5272 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { @@ -71,12 +112,12 @@ int checkcpu(void) { case 0x4: suf = "3K75N"; break; default: suf = NULL; - printf ("MOTOROLA MCF5272 (Mask:%01x)\n", msk); + printf ("Freescale MCF5272 (Mask:%01x)\n", msk); break; } if (suf) - printf ("MOTOROLA MCF5272 %s\n", suf); + printf ("Freescale MCF5272 %s\n", suf); return 0; }; @@ -121,20 +162,19 @@ int watchdog_init (void) #ifdef CONFIG_M5282 int checkcpu (void) { - unsigned char resetsource; + unsigned char resetsource = MCFRESET_RSR; - printf ("CPU: MOTOROLA Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - puts ("Reset: "); - resetsource = MCFRESET_RSR; - if (resetsource & MCFRESET_RSR_LOL) puts("Lose-of-lock "); - if (resetsource & MCFRESET_RSR_LOC) puts("Lose-of-clock "); - if (resetsource & MCFRESET_RSR_EXT) puts("external "); - if (resetsource & MCFRESET_RSR_POR) puts("Power-on "); - if (resetsource & MCFRESET_RSR_WDR) puts("Watchdog "); - if (resetsource & MCFRESET_RSR_SOFT) puts("Software "); - if (resetsource & MCFRESET_RSR_LVD) puts("Low-voltage "); - puts("\n"); + printf ("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" + ); return 0; } @@ -150,7 +190,7 @@ int checkcpu (void) { char buf[32]; - printf ("CPU: MOTOROLA Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 0fa2ce2e1..1748ea9d9 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -16,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -28,6 +28,11 @@ #include <common.h> #include <watchdog.h> +#ifdef CONFIG_M5271 +#include <asm/m5271.h> +#include <asm/immap_5271.h> +#endif + #ifdef CONFIG_M5272 #include <asm/m5272.h> #include <asm/immap_5272.h> @@ -42,6 +47,38 @@ #include <asm/m5249.h> #endif +#if defined(CONFIG_M5271) +void cpu_init_f (void) +{ +#ifndef CONFIG_WATCHDOG + /* Disable the watchdog if we aren't using it */ + mbar_writeShort(MCF_WTM_WCR, 0); +#endif + + /* Set clockspeed to 100MHz */ + mbar_writeShort(MCF_FMPLL_SYNCR, + MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK); + + /* Enable UART pins */ + mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | + MCF_GPIO_PAR_UART_U0RXD | + MCF_GPIO_PAR_UART_U1RXD_UART1 | + MCF_GPIO_PAR_UART_U1TXD_UART1); + + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} +#endif + #if defined(CONFIG_M5272) /* * Breath some life into the CPU... @@ -64,7 +101,7 @@ void cpu_init_f (void) regp->sysctrl_reg.sc_scr = CFG_SCR; regp->sysctrl_reg.sc_spr = CFG_SPR; - /* Setup Ports: */ + /* Setup Ports: */ regp->gpio_reg.gpio_pacnt = CFG_PACNT; regp->gpio_reg.gpio_paddr = CFG_PADDR; regp->gpio_reg.gpio_padat = CFG_PADAT; @@ -114,15 +151,15 @@ void cpu_init_f (void) #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ - /* enable instruction cache now */ - icache_enable(); + /* enable instruction cache now */ + icache_enable(); } /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r (void) { return (0); } @@ -318,7 +355,7 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r (void) { return (0); } @@ -342,23 +379,23 @@ void cpu_init_f (void) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; #ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ #endif - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ #endif /* #ifndef CFG_PLL_BYPASS */ /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); @@ -373,7 +410,7 @@ void cpu_init_f (void) * (Internal Register Display) command * ~Jeremy * - */ + */ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); @@ -392,9 +429,9 @@ void cpu_init_f (void) mbar_writeByte(MCFSIM_QSPIICR, 0x00); mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); - mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ + mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ @@ -422,7 +459,7 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r (void) { return (0); } diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index b8b82d07d..702563d7d 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -25,6 +25,11 @@ #include <malloc.h> #include <asm/fec.h> +#ifdef CONFIG_M5271 +#include <asm/m5271.h> +#include <asm/immap_5271.h> +#endif + #ifdef CONFIG_M5272 #include <asm/m5272.h> #include <asm/immap_5272.h> @@ -41,7 +46,7 @@ #ifdef CONFIG_M5272 #define FEC_ADDR (CFG_MBAR + 0x840) #endif -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) #define FEC_ADDR (CFG_MBAR + 0x1000) #endif @@ -242,6 +247,17 @@ int eth_init (bd_t * bd) #endif #undef ea +#ifdef CONFIG_M5271 + /* Clear multicast address hash table + */ + fecp->fec_ghash_table_high = 0; + fecp->fec_ghash_table_low = 0; + + /* Clear individual address hash table + */ + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else /* Clear multicast address hash table */ #ifdef CONFIG_M5282 @@ -251,6 +267,7 @@ int eth_init (bd_t * bd) fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; #endif + /* Set maximum receive buffer size. */ fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; @@ -305,10 +322,11 @@ int eth_init (bd_t * bd) /* Enable MII mode */ -#if 0 /* Full duplex mode */ + +#if 0 /* Full duplex mode */ fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ +#else /* Half duplex mode */ fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; fecp->fec_x_cntrl = 0; diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 868df3919..116747ad3 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -27,6 +27,11 @@ #include <watchdog.h> #include <asm/processor.h> +#ifdef CONFIG_M5271 +#include <asm/m5271.h> +#include <asm/immap_5271.h> +#endif + #ifdef CONFIG_M5272 #include <asm/m5272.h> #include <asm/immap_5272.h> @@ -171,7 +176,7 @@ int interrupt_init (void) } #endif -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) int interrupt_init (void) { return 0; diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c index fe412a0a3..8be09e34f 100644 --- a/cpu/mcf52x2/serial.c +++ b/cpu/mcf52x2/serial.c @@ -23,9 +23,14 @@ #include <common.h> #include <command.h> +#include <watchdog.h> #include <asm/mcfuart.h> +#ifdef CONFIG_M5271 +#include <asm/m5271.h> +#endif + #ifdef CONFIG_M5272 #include <asm/m5272.h> #endif @@ -40,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5271) #define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) #else #define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) @@ -48,72 +53,77 @@ DECLARE_GLOBAL_DATA_PTR; void rs_serial_setbaudrate(int port,int baudrate) { -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) volatile unsigned char *uartp; - double clock, fraction; +# ifndef CONFIG_M5271 + double fraction; +# endif + double clock; if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - clock = DoubleClock(baudrate); /* Set baud above */ + clock = DoubleClock(baudrate); /* Set baud above */ - fraction = ((clock - (int)clock) * 16.0) + 0.5; + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ +# ifndef CONFIG_M5271 + fraction = ((clock - (int)clock) * 16.0) + 0.5; + uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ +# endif #endif + #if defined(CONFIG_M5282) volatile unsigned char *uartp; long clock; - switch (port) - { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + switch (port) { + case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); } - clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ + clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ #endif }; -void rs_serial_init(int port,int baudrate) +void rs_serial_init (int port, int baudrate) { - volatile unsigned char *uartp; + volatile unsigned char *uartp; /* - * Reset UART, get it into known state... + * Reset UART, get it into known state... */ - switch (port) - { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - #if defined(CONFIG_M5282) - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - #endif - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + switch (port) { + case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; +#if defined(CONFIG_M5282) + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; +#endif + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); } - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ /* * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. @@ -121,9 +131,15 @@ void rs_serial_init(int port,int baudrate) uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - rs_serial_setbaudrate(port,baudrate); + /* Mask UART interrupts */ + uartp[MCFUART_UIMR] = 0; + /* Set clock Select Register: Tx/Rx clock is timer */ uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; + + rs_serial_setbaudrate (port, baudrate); + + /* Enable Tx/Rx */ uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; return; @@ -183,13 +199,14 @@ void serial_putc(const char c) { } void serial_puts (const char *s) { - while (*s) { + while (*s) serial_putc(*s++); - } } int serial_getc(void) { - while(!rs_is_char()); + while(!rs_is_char()) + WATCHDOG_RESET(); + return rs_get_char(); } diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 9a13491fb..8a83ca5ef 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -54,12 +54,16 @@ * These vectors are to catch any un-intended traps. */ _vectors: - .long 0x00000000 -#ifndef CONFIG_M5282 -.long _START -#else + +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +#if defined(CONFIG_R5200) +.long 0x400 +#elif defined(CONFIG_M5282) .long _start - TEXT_BASE +#else +.long _START #endif + .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -131,7 +135,7 @@ _start: movec %d0, %RAMBAR0 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 @@ -175,12 +179,26 @@ _after_flashbar_copy: movec %d0, %VBR #endif +#ifdef CONFIG_R5200 + move.l #(_flash_setup-CFG_FLASH_BASE), %a0 + move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CFG_INIT_RAM_ADDR +_after_flash_copy: +#endif + +#if 0 /* invalidate and disable cache */ move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 movec %d0, %ACR1 +#endif /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp @@ -191,9 +209,28 @@ _after_flashbar_copy: bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ - /* board_init_f() does not return + /* board_init_f() does not return */ /*------------------------------------------------------------------------------*/ + +#ifdef CONFIG_R5200 +_flash_setup: + /* CSAR0 */ + move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0 + move.w %d0, 0x40000080 + + /* CSCR0 */ + move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */ + move.w %d0, 0x4000008A + + /* CSMR0 */ + move.l #0x001f0001, %d0 /* 2 MB, valid */ + move.l %d0, 0x40000084 + + jmp _after_flash_copy.L +_flash_setup_end: +#endif + /* * void relocate_code (addr_sp, gd, addr_moni) * |