aboutsummaryrefslogtreecommitdiff
path: root/cpu/arm920t/speed.c
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/arm920t/speed.c')
-rw-r--r--cpu/arm920t/speed.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/speed.c
index 494272727..1f435436b 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/speed.c
@@ -51,12 +51,13 @@
static ulong get_PLLCLK(int pllreg)
{
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
ulong r, m, p, s;
if (pllreg == MPLL)
- r = rMPLLCON;
+ r = clk_power->MPLLCON;
else if (pllreg == UPLL)
- r = rUPLLCON;
+ r = clk_power->UPLLCON;
else
hang();
@@ -76,17 +77,17 @@ ulong get_FCLK(void)
/* return HCLK frequency */
ulong get_HCLK(void)
{
- ulong clkdiv = rCLKDIVN;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
+ return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
- ulong clkdiv = rCLKDIVN;
+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
+ return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
}
/* return UCLK frequency */