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-rw-r--r--board/highbank/highbank.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 6776cb127..944ab9ce7 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -26,6 +26,8 @@
#define HB_SREG_A9_PWR_REQ 0xfff3cf00
#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
+#define HB_SYSRAM_OPP_TABLE_BASE 0xfff8f000
+#define HB_OPP_VERSION 0
#define HB_PWR_SUSPEND 0
#define HB_PWR_SOFT_RESET 1
@@ -95,9 +97,16 @@ void dram_init_banksize(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+struct a9_opp {
+ unsigned int freq_hz;
+ unsigned int volt_mv;
+};
+
+
void ft_board_setup(void *fdt, bd_t *bd)
{
const char disabled[] = "disabled";
+ u32 *opp_table = HB_SYSRAM_OPP_TABLE_BASE;
u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
if (!(reg & PWRDOM_STAT_SATA))
@@ -105,6 +114,20 @@ void ft_board_setup(void *fdt, bd_t *bd)
if (!(reg & PWRDOM_STAT_EMMC))
do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", disabled, sizeof(disabled), 1);
+
+ if ((opp_table[0] >> 16) == HB_OPP_VERSION) {
+ u32 dtb_table[2*10];
+ u32 ret;
+ u32 i;
+ u32 num_opps = opp_table[0] & 0xff;
+ for (i = 0; i < num_opps; i++) {
+ dtb_table[2 * i] = cpu_to_be32(opp_table[3 + 3 * i]);
+ dtb_table[2 * i + 1] =
+ cpu_to_be32(opp_table[2 + 3 * i]);
+ }
+ fdt_find_and_setprop(fdt, "/cpus/cpu@0", "operating-points",
+ dtb_table, 8 * num_opps, 1);
+ }
}
#endif