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-rw-r--r--board/sacsng/Makefile2
-rw-r--r--board/sacsng/clkinit.c586
-rw-r--r--board/sacsng/clkinit.h16
-rw-r--r--board/sacsng/ioconfig.h15
-rw-r--r--board/sacsng/sacsng.c100
-rw-r--r--board/sacsng/u-boot.lds6
6 files changed, 364 insertions, 361 deletions
diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile
index e593f2724..baefa4a74 100644
--- a/board/sacsng/Makefile
+++ b/board/sacsng/Makefile
@@ -28,7 +28,7 @@ LIB = lib$(BOARD).a
OBJS := sacsng.o flash.o clkinit.o
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
index 634c1e05f..ea4c65d6b 100644
--- a/board/sacsng/clkinit.c
+++ b/board/sacsng/clkinit.c
@@ -41,8 +41,8 @@ void Daq_BRG_Reset(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
*brg_ptr |= CPM_BRG_RST;
@@ -57,8 +57,8 @@ void Daq_BRG_Disable(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
*brg_ptr &= ~CPM_BRG_EN;
@@ -71,8 +71,8 @@ void Daq_BRG_Enable(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
*brg_ptr |= CPM_BRG_EN;
@@ -85,18 +85,18 @@ uint Daq_BRG_Get_Div16(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
if (*brg_ptr & CPM_BRG_DIV16) {
- /* DIV16 active */
- return (TRUE);
+ /* DIV16 active */
+ return (TRUE);
}
else {
- /* DIV16 inactive */
- return (FALSE);
+ /* DIV16 inactive */
+ return (FALSE);
}
}
@@ -107,18 +107,18 @@ void Daq_BRG_Set_Div16(uint brg, uint div16)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
if (div16) {
- /* DIV16 active */
- *brg_ptr |= CPM_BRG_DIV16;
+ /* DIV16 active */
+ *brg_ptr |= CPM_BRG_DIV16;
}
else {
- /* DIV16 inactive */
- *brg_ptr &= ~CPM_BRG_DIV16;
+ /* DIV16 inactive */
+ *brg_ptr &= ~CPM_BRG_DIV16;
}
}
@@ -130,8 +130,8 @@ uint Daq_BRG_Get_Count(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
@@ -143,7 +143,7 @@ uint Daq_BRG_Get_Count(uint brg)
brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
brg_cnt++;
if (*brg_ptr & CPM_BRG_DIV16) {
- brg_cnt *= 16;
+ brg_cnt *= 16;
}
return (brg_cnt);
@@ -156,8 +156,8 @@ void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
@@ -166,14 +166,14 @@ void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
* therefore we need to subtract 1 from the count.
*/
if (brg_cnt > 4096) {
- /* Prescale = Divide by 16 */
- *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+ /* Prescale = Divide by 16 */
+ *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
(((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
*brg_ptr |= CPM_BRG_DIV16;
}
else {
- /* Prescale = Divide by 1 */
- *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+ /* Prescale = Divide by 1 */
+ *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
*brg_ptr &= ~CPM_BRG_DIV16;
}
@@ -186,8 +186,8 @@ uint Daq_BRG_Get_ExtClk(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
@@ -201,40 +201,40 @@ char* Daq_BRG_Get_ExtClk_Description(uint brg)
extc = Daq_BRG_Get_ExtClk(brg);
switch (brg + 1) {
- case 1:
- case 2:
- case 5:
- case 6: {
- switch (extc) {
- case 0: {
- return ("BRG_INT");
- }
- case 1: {
- return ("CLK3");
- }
- case 2: {
- return ("CLK5");
- }
- }
- return ("??1245??");
- }
- case 3:
- case 4:
- case 7:
- case 8: {
- switch (extc) {
- case 0: {
- return ("BRG_INT");
- }
- case 1: {
- return ("CLK9");
- }
- case 2: {
- return ("CLK15");
- }
- }
- return ("??3478??");
- }
+ case 1:
+ case 2:
+ case 5:
+ case 6: {
+ switch (extc) {
+ case 0: {
+ return ("BRG_INT");
+ }
+ case 1: {
+ return ("CLK3");
+ }
+ case 2: {
+ return ("CLK5");
+ }
+ }
+ return ("??1245??");
+ }
+ case 3:
+ case 4:
+ case 7:
+ case 8: {
+ switch (extc) {
+ case 0: {
+ return ("BRG_INT");
+ }
+ case 1: {
+ return ("CLK9");
+ }
+ case 2: {
+ return ("CLK15");
+ }
+ }
+ return ("??3478??");
+ }
}
return ("??9876??");
}
@@ -246,13 +246,13 @@ void Daq_BRG_Set_ExtClk(uint brg, uint extc)
brg_ptr = (uint *)&immr->im_brgc1;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg -= 4;
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg -= 4;
}
brg_ptr += brg;
*brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
- ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
+ ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
}
uint Daq_BRG_Rate(uint brg)
@@ -266,15 +266,15 @@ uint Daq_BRG_Rate(uint brg)
brg_ptr = (uint *)&immr->im_brgc1;
brg_ptr += brg;
if (brg >= 5) {
- brg_ptr = (uint *)&immr->im_brgc5;
- brg_ptr += (brg - 4);
+ brg_ptr = (uint *)&immr->im_brgc5;
+ brg_ptr += (brg - 4);
}
brg_cnt = Daq_BRG_Get_Count(brg);
switch (Daq_BRG_Get_ExtClk(brg)) {
- case CPM_BRG_EXTC_CLK3:
- case CPM_BRG_EXTC_CLK5: {
+ case CPM_BRG_EXTC_CLK3:
+ case CPM_BRG_EXTC_CLK5: {
brg_freq = brg_cnt;
break;
}
@@ -298,7 +298,7 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
DECLARE_GLOBAL_DATA_PTR;
volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
uint mclk_divisor; /* MCLK divisor */
- int flag; /* Interrupt state */
+ int flag; /* Interrupt state */
/* Save off the clocking data */
Daq64xSampling = sample_64x;
@@ -307,10 +307,10 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
* Limit the sample rate to some sensible values.
*/
if (sample_rate > MAX_64x_SAMPLE_RATE) {
- sample_rate = MAX_64x_SAMPLE_RATE;
+ sample_rate = MAX_64x_SAMPLE_RATE;
}
if (sample_rate < MIN_SAMPLE_RATE) {
- sample_rate = MIN_SAMPLE_RATE;
+ sample_rate = MIN_SAMPLE_RATE;
}
/*
@@ -322,16 +322,16 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
/* Setup SCLK */
# ifdef RUN_SCLK_ON_BRG_INT
- Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+ Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
# else
- Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
+ Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
# endif
/* Setup LRCLK */
# ifdef RUN_LRCLK_ON_BRG_INT
- Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+ Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
# else
- Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
+ Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
# endif
/*
@@ -357,7 +357,7 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
# endif
# ifdef RUN_LRCLK_ON_BRG_INT
- Daq_BRG_Set_Count(LRCLK_BRG,
+ Daq_BRG_Set_Count(LRCLK_BRG,
mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
# else
Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
@@ -367,7 +367,7 @@ void Daq_Init_Clocks(int sample_rate, int sample_64x)
* Restore the Interrupt state
*/
if (flag) {
- enable_interrupts();
+ enable_interrupts();
}
/* Enable the clock drivers */
@@ -386,276 +386,276 @@ void Daq_Stop_Clocks(void)
#endif
# ifdef TIGHTEN_UP_BRG_TIMING
- /*
- * Obtain MCLK BRG reset/disabled value
- */
+ /*
+ * Obtain MCLK BRG reset/disabled value
+ */
# if (MCLK_BRG == 0)
- mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 1)
- mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 2)
- mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 3)
- mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 4)
- mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 5)
- mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 6)
- mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (MCLK_BRG == 7)
- mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
- /*
- * Obtain SCLK BRG reset/disabled value
- */
+ /*
+ * Obtain SCLK BRG reset/disabled value
+ */
# if (SCLK_BRG == 0)
- sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 1)
- sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 2)
- sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 3)
- sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 4)
- sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 5)
- sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 6)
- sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (SCLK_BRG == 7)
- sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
- /*
- * Obtain LRCLK BRG reset/disabled value
- */
+ /*
+ * Obtain LRCLK BRG reset/disabled value
+ */
# if (LRCLK_BRG == 0)
- lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 1)
- lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 2)
- lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 3)
- lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 4)
- lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 5)
- lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 6)
- lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 7)
- lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
# endif
-
+
/*
* Disable interrupt and save the current state
*/
flag = disable_interrupts();
- /*
- * Set reset on MCLK BRG
- */
+ /*
+ * Set reset on MCLK BRG
+ */
# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg;
+ *IM_BRGC1 = mclk_brg;
# endif
# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg;
+ *IM_BRGC2 = mclk_brg;
# endif
# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg;
+ *IM_BRGC3 = mclk_brg;
# endif
# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg;
+ *IM_BRGC4 = mclk_brg;
# endif
# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg;
+ *IM_BRGC5 = mclk_brg;
# endif
# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg;
+ *IM_BRGC6 = mclk_brg;
# endif
# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg;
+ *IM_BRGC7 = mclk_brg;
# endif
# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg;
+ *IM_BRGC8 = mclk_brg;
# endif
- /*
- * Set reset on SCLK BRG
- */
+ /*
+ * Set reset on SCLK BRG
+ */
# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg;
+ *IM_BRGC1 = sclk_brg;
# endif
# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg;
+ *IM_BRGC2 = sclk_brg;
# endif
# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg;
+ *IM_BRGC3 = sclk_brg;
# endif
# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg;
+ *IM_BRGC4 = sclk_brg;
# endif
# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg;
+ *IM_BRGC5 = sclk_brg;
# endif
# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg;
+ *IM_BRGC6 = sclk_brg;
# endif
# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg;
+ *IM_BRGC7 = sclk_brg;
# endif
# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg;
+ *IM_BRGC8 = sclk_brg;
# endif
- /*
- * Set reset on LRCLK BRG
- */
+ /*
+ * Set reset on LRCLK BRG
+ */
# if (LRCLK_BRG == 0)
- *IM_BRGC1 = lrclk_brg;
+ *IM_BRGC1 = lrclk_brg;
# endif
# if (LRCLK_BRG == 1)
- *IM_BRGC2 = lrclk_brg;
+ *IM_BRGC2 = lrclk_brg;
# endif
# if (LRCLK_BRG == 2)
- *IM_BRGC3 = lrclk_brg;
+ *IM_BRGC3 = lrclk_brg;
# endif
# if (LRCLK_BRG == 3)
- *IM_BRGC4 = lrclk_brg;
+ *IM_BRGC4 = lrclk_brg;
# endif
# if (LRCLK_BRG == 4)
- *IM_BRGC5 = lrclk_brg;
+ *IM_BRGC5 = lrclk_brg;
# endif
# if (LRCLK_BRG == 5)
- *IM_BRGC6 = lrclk_brg;
+ *IM_BRGC6 = lrclk_brg;
# endif
# if (LRCLK_BRG == 6)
- *IM_BRGC7 = lrclk_brg;
+ *IM_BRGC7 = lrclk_brg;
# endif
# if (LRCLK_BRG == 7)
- *IM_BRGC8 = lrclk_brg;
+ *IM_BRGC8 = lrclk_brg;
# endif
-
- /*
- * Clear reset on MCLK BRG
- */
+
+ /*
+ * Clear reset on MCLK BRG
+ */
# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
# endif
# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
# endif
- /*
- * Clear reset on SCLK BRG
- */
+ /*
+ * Clear reset on SCLK BRG
+ */
# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
# endif
# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
# endif
- /*
- * Clear reset on LRCLK BRG
- */
+ /*
+ * Clear reset on LRCLK BRG
+ */
# if (LRCLK_BRG == 0)
- *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 1)
- *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 2)
- *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 3)
- *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 4)
- *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 5)
- *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 6)
- *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
# endif
# if (LRCLK_BRG == 7)
- *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
+ *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
# endif
-
+
/*
* Restore the Interrupt state
*/
if (flag) {
- enable_interrupts();
+ enable_interrupts();
}
# else
- /*
- * Reset the clocks
- */
- Daq_BRG_Reset(MCLK_BRG);
- Daq_BRG_Reset(SCLK_BRG);
- Daq_BRG_Reset(LRCLK_BRG);
+ /*
+ * Reset the clocks
+ */
+ Daq_BRG_Reset(MCLK_BRG);
+ Daq_BRG_Reset(SCLK_BRG);
+ Daq_BRG_Reset(LRCLK_BRG);
# endif
}
@@ -676,88 +676,88 @@ void Daq_Start_Clocks(int sample_rate)
#endif
# ifdef TIGHTEN_UP_BRG_TIMING
- /*
- * Obtain the enabled MCLK BRG value
- */
+ /*
+ * Obtain the enabled MCLK BRG value
+ */
# if (MCLK_BRG == 0)
- mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 1)
- mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 2)
- mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 3)
- mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 4)
- mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 5)
- mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 6)
- mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (MCLK_BRG == 7)
- mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
- /*
- * Obtain the enabled SCLK BRG value
- */
+ /*
+ * Obtain the enabled SCLK BRG value
+ */
# if (SCLK_BRG == 0)
- sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 1)
- sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 2)
- sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 3)
- sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 4)
- sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 5)
- sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 6)
- sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (SCLK_BRG == 7)
- sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
- /*
- * Obtain the enabled LRCLK BRG value
- */
+ /*
+ * Obtain the enabled LRCLK BRG value
+ */
# if (LRCLK_BRG == 0)
- lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 1)
- lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 2)
- lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 3)
- lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 4)
- lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 5)
- lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 6)
- lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
# if (LRCLK_BRG == 7)
- lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+ lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
# endif
/* Save off the real LRCLK value */
@@ -767,15 +767,15 @@ void Daq_Start_Clocks(int sample_rate)
sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1;
/* Compute the delay as a function of SCLK count */
- delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
+ delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
if (DaqSampleRate == 43402) {
delay_cnt++;
}
- /* Clear out the count */
+ /* Clear out the count */
temp_lrclk_brg = sclk_brg & ~0x00001FFE;
- /* Insert the count */
+ /* Insert the count */
temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE;
/*
@@ -783,116 +783,116 @@ void Daq_Start_Clocks(int sample_rate)
*/
flag = disable_interrupts();
- /*
- * Enable MCLK BRG
- */
+ /*
+ * Enable MCLK BRG
+ */
# if (MCLK_BRG == 0)
- *IM_BRGC1 = mclk_brg;
+ *IM_BRGC1 = mclk_brg;
# endif
# if (MCLK_BRG == 1)
- *IM_BRGC2 = mclk_brg;
+ *IM_BRGC2 = mclk_brg;
# endif
# if (MCLK_BRG == 2)
- *IM_BRGC3 = mclk_brg;
+ *IM_BRGC3 = mclk_brg;
# endif
# if (MCLK_BRG == 3)
- *IM_BRGC4 = mclk_brg;
+ *IM_BRGC4 = mclk_brg;
# endif
# if (MCLK_BRG == 4)
- *IM_BRGC5 = mclk_brg;
+ *IM_BRGC5 = mclk_brg;
# endif
# if (MCLK_BRG == 5)
- *IM_BRGC6 = mclk_brg;
+ *IM_BRGC6 = mclk_brg;
# endif
# if (MCLK_BRG == 6)
- *IM_BRGC7 = mclk_brg;
+ *IM_BRGC7 = mclk_brg;
# endif
# if (MCLK_BRG == 7)
- *IM_BRGC8 = mclk_brg;
+ *IM_BRGC8 = mclk_brg;
# endif
- /*
- * Enable SCLK BRG
- */
+ /*
+ * Enable SCLK BRG
+ */
# if (SCLK_BRG == 0)
- *IM_BRGC1 = sclk_brg;
+ *IM_BRGC1 = sclk_brg;
# endif
# if (SCLK_BRG == 1)
- *IM_BRGC2 = sclk_brg;
+ *IM_BRGC2 = sclk_brg;
# endif
# if (SCLK_BRG == 2)
- *IM_BRGC3 = sclk_brg;
+ *IM_BRGC3 = sclk_brg;
# endif
# if (SCLK_BRG == 3)
- *IM_BRGC4 = sclk_brg;
+ *IM_BRGC4 = sclk_brg;
# endif
# if (SCLK_BRG == 4)
- *IM_BRGC5 = sclk_brg;
+ *IM_BRGC5 = sclk_brg;
# endif
# if (SCLK_BRG == 5)
- *IM_BRGC6 = sclk_brg;
+ *IM_BRGC6 = sclk_brg;
# endif
# if (SCLK_BRG == 6)
- *IM_BRGC7 = sclk_brg;
+ *IM_BRGC7 = sclk_brg;
# endif
# if (SCLK_BRG == 7)
- *IM_BRGC8 = sclk_brg;
+ *IM_BRGC8 = sclk_brg;
# endif
- /*
- * Enable LRCLK BRG (1st time - temporary)
- */
+ /*
+ * Enable LRCLK BRG (1st time - temporary)
+ */
# if (LRCLK_BRG == 0)
- *IM_BRGC1 = temp_lrclk_brg;
+ *IM_BRGC1 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 1)
- *IM_BRGC2 = temp_lrclk_brg;
+ *IM_BRGC2 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 2)
- *IM_BRGC3 = temp_lrclk_brg;
+ *IM_BRGC3 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 3)
- *IM_BRGC4 = temp_lrclk_brg;
+ *IM_BRGC4 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 4)
- *IM_BRGC5 = temp_lrclk_brg;
+ *IM_BRGC5 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 5)
- *IM_BRGC6 = temp_lrclk_brg;
+ *IM_BRGC6 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 6)
- *IM_BRGC7 = temp_lrclk_brg;
+ *IM_BRGC7 = temp_lrclk_brg;
# endif
# if (LRCLK_BRG == 7)
- *IM_BRGC8 = temp_lrclk_brg;
+ *IM_BRGC8 = temp_lrclk_brg;
# endif
-
- /*
- * Enable LRCLK BRG (2nd time - permanent)
- */
+
+ /*
+ * Enable LRCLK BRG (2nd time - permanent)
+ */
# if (LRCLK_BRG == 0)
- *IM_BRGC1 = real_lrclk_brg;
+ *IM_BRGC1 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 1)
- *IM_BRGC2 = real_lrclk_brg;
+ *IM_BRGC2 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 2)
- *IM_BRGC3 = real_lrclk_brg;
+ *IM_BRGC3 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 3)
- *IM_BRGC4 = real_lrclk_brg;
+ *IM_BRGC4 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 4)
- *IM_BRGC5 = real_lrclk_brg;
+ *IM_BRGC5 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 5)
- *IM_BRGC6 = real_lrclk_brg;
+ *IM_BRGC6 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 6)
- *IM_BRGC7 = real_lrclk_brg;
+ *IM_BRGC7 = real_lrclk_brg;
# endif
# if (LRCLK_BRG == 7)
- *IM_BRGC8 = real_lrclk_brg;
+ *IM_BRGC8 = real_lrclk_brg;
# endif
/*
@@ -900,14 +900,14 @@ void Daq_Start_Clocks(int sample_rate)
*/
if (flag) {
enable_interrupts();
- }
+ }
# else
- /*
- * Enable the clocks
- */
- Daq_BRG_Enable(LRCLK_BRG);
- Daq_BRG_Enable(SCLK_BRG);
- Daq_BRG_Enable(MCLK_BRG);
+ /*
+ * Enable the clocks
+ */
+ Daq_BRG_Enable(LRCLK_BRG);
+ Daq_BRG_Enable(SCLK_BRG);
+ Daq_BRG_Enable(MCLK_BRG);
# endif
}
@@ -920,7 +920,7 @@ void Daq_Display_Clocks(void)
printf("\nBRG:\n");
if (immr->im_brgc4 != 0) {
- printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
+ printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n",
immr->im_brgc4,
(uint)&(immr->im_brgc4),
Daq_BRG_Get_Count(3),
@@ -928,7 +928,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(3));
}
if (immr->im_brgc8 != 0) {
- printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
+ printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n",
immr->im_brgc8,
(uint)&(immr->im_brgc8),
Daq_BRG_Get_Count(7),
@@ -936,7 +936,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(7));
}
if (immr->im_brgc6 != 0) {
- printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
+ printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n",
immr->im_brgc6,
(uint)&(immr->im_brgc6),
Daq_BRG_Get_Count(5),
@@ -944,7 +944,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(5));
}
if (immr->im_brgc1 != 0) {
- printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
+ printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n",
immr->im_brgc1,
(uint)&(immr->im_brgc1),
Daq_BRG_Get_Count(0),
@@ -952,7 +952,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(0));
}
if (immr->im_brgc2 != 0) {
- printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
+ printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n",
immr->im_brgc2,
(uint)&(immr->im_brgc2),
Daq_BRG_Get_Count(1),
@@ -960,7 +960,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(1));
}
if (immr->im_brgc3 != 0) {
- printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
+ printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n",
immr->im_brgc3,
(uint)&(immr->im_brgc3),
Daq_BRG_Get_Count(2),
@@ -968,7 +968,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(2));
}
if (immr->im_brgc5 != 0) {
- printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+ printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
immr->im_brgc5,
(uint)&(immr->im_brgc5),
Daq_BRG_Get_Count(4),
@@ -976,7 +976,7 @@ void Daq_Display_Clocks(void)
Daq_BRG_Get_ExtClk_Description(4));
}
if (immr->im_brgc7 != 0) {
- printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+ printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
immr->im_brgc7,
(uint)&(immr->im_brgc7),
Daq_BRG_Get_Count(6),
@@ -985,14 +985,14 @@ void Daq_Display_Clocks(void)
}
# ifdef RUN_SCLK_ON_BRG_INT
- mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
+ mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
# else
- mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
+ mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
# endif
# ifdef RUN_LRCLK_ON_BRG_INT
- sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
+ sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
# else
- sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
+ sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
# endif
printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
@@ -1001,23 +1001,23 @@ void Daq_Display_Clocks(void)
mclk_divisor,
mclk_divisor * sclk_divisor);
# ifdef RUN_SCLK_ON_BRG_INT
- printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
+ printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
Daq_BRG_Rate(SCLK_BRG),
sclk_divisor);
# else
- printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
+ printf("\tSCLK %8d Hz, or %3dx LRCLK\n",
Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
sclk_divisor);
# endif
# ifdef RUN_LRCLK_ON_BRG_INT
- printf("\tLRCLK %8d Hz\n",
+ printf("\tLRCLK %8d Hz\n",
Daq_BRG_Rate(LRCLK_BRG));
# else
# ifdef RUN_SCLK_ON_BRG_INT
- printf("\tLRCLK %8d Hz\n",
+ printf("\tLRCLK %8d Hz\n",
Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
# else
- printf("\tLRCLK %8d Hz\n",
+ printf("\tLRCLK %8d Hz\n",
Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
# endif
# endif
diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h
index 2731f2e7c..011638f2f 100644
--- a/board/sacsng/clkinit.h
+++ b/board/sacsng/clkinit.h
@@ -50,16 +50,16 @@
#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
- /* LRCLK = SCLK / SCLK_DIVISOR */
+ /* LRCLK = SCLK / SCLK_DIVISOR */
#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating SCLK from MCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating SCLK from MCLK */
/* via CLK9. */
#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating LRCLK from SCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating LRCLK from SCLK */
#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */
/* to wait for the clock to stabilize */
@@ -67,9 +67,9 @@
#define CPM_CLK (gd->bd->bi_cpmfreq)
#define DFBRG 4
#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
- /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
- /* BRG = CPM * 2 / 4 */
- /* BRG = CPM / 2 */
+ /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+ /* BRG = CPM * 2 / 4 */
+ /* BRG = CPM / 2 */
#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
#define CPM_BRG_EXTC_SHIFT 14
diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h
index 6857f99ae..be1ce7c83 100644
--- a/board/sacsng/ioconfig.h
+++ b/board/sacsng/ioconfig.h
@@ -45,7 +45,7 @@
#define GPIO 0 /* PPARx 0: General Purpose I/O */
#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */
- /* i.e. the port has a SPECial use. */
+ /* i.e. the port has a SPECial use. */
#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */
#define OPEN 1 /* PODRx 1: OPEN-drain driver */
@@ -67,12 +67,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */
/* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */
/* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */
- /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
+ /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */
/* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
/* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */
/* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */
- /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
- /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
+ /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */
+ /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */
/* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */
/* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */
/* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */
@@ -143,7 +143,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
/* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */
/* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */
- /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
+ /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */
/* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
/* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */
/* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
@@ -156,11 +156,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */
/* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */
/* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */
- /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
+ /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */
/* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */
/* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */
/* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */
- /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
+ /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */
},
/* Port D */
@@ -215,4 +215,3 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */
}
};
-
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
index 19dbb97e6..086e42a6a 100644
--- a/board/sacsng/sacsng.c
+++ b/board/sacsng/sacsng.c
@@ -75,7 +75,7 @@
#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
- /* Wait at least 4100 LRCLK's */
+ /* Wait at least 4100 LRCLK's */
#define ADC_REG1_FRAME_START 0x80 /* Frame start */
#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
@@ -201,17 +201,17 @@ long int initdram(int board_type)
else if(j == 4) cols = data & 0x0F;
else if(j == 12) {
/*
- * Refresh rate: this assumes the prescaler is set to
+ * Refresh rate: this assumes the prescaler is set to
* approximately 1uSec per tick.
*/
switch(data & 0x7F) {
- default:
- case 0: psrt = 14 ; /* 15.625uS */ break;
- case 1: psrt = 2; /* 3.9uS */ break;
- case 2: psrt = 6; /* 7.8uS */ break;
- case 3: psrt = 29; /* 31.3uS */ break;
- case 4: psrt = 60; /* 62.5uS */ break;
- case 5: psrt = 120; /* 125uS */ break;
+ default:
+ case 0: psrt = 14 ; /* 15.625uS */ break;
+ case 1: psrt = 2; /* 3.9uS */ break;
+ case 2: psrt = 6; /* 7.8uS */ break;
+ case 3: psrt = 29; /* 31.3uS */ break;
+ case 4: psrt = 60; /* 62.5uS */ break;
+ case 5: psrt = 120; /* 125uS */ break;
}
}
else if(j == 17) banks = data;
@@ -228,13 +228,13 @@ long int initdram(int board_type)
#endif
else {
printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
- data);
+ data);
}
}
else if(j == 63) {
if(data != cksum) {
printf ("WARNING: Configuration data checksum failure:"
- " is 0x%02x, calculated 0x%02x\n",
+ " is 0x%02x, calculated 0x%02x\n",
data, cksum);
}
}
@@ -309,7 +309,7 @@ long int initdram(int board_type)
PSDMR_ACTTORW_8W |\
PSDMR_WRC_4C |\
PSDMR_EAMUX |\
- PSDMR_BUFCMD) |\
+ PSDMR_BUFCMD) |\
caslatency |\
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
(sdam << 24) |\
@@ -323,7 +323,7 @@ long int initdram(int board_type)
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
PSDMR_WRC_1C | /* 1 clock + 7nSec */
EAMUX |\
- BUFCMD) |\
+ BUFCMD) |\
caslatency |\
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
(sdam << 24) |\
@@ -400,7 +400,7 @@ long int initdram(int board_type)
* two chip selects (double sided).
*/
if(chipselects > 1) {
- ramaddr += sdram_size;
+ ramaddr += sdram_size;
memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
@@ -459,13 +459,13 @@ int misc_init_r(void)
sample_rate = INITIAL_SAMPLE_RATE;
if ((ep = getenv("DaqSampleRate")) != NULL) {
- sample_rate = simple_strtol(ep, NULL, 10);
+ sample_rate = simple_strtol(ep, NULL, 10);
}
sample_64x = INITIAL_SAMPLE_64X;
sample_128x = INITIAL_SAMPLE_128X;
if ((ep = getenv("Daq64xSampling")) != NULL) {
- sample_64x = simple_strtol(ep, NULL, 10);
+ sample_64x = simple_strtol(ep, NULL, 10);
if (sample_64x) {
sample_128x = 0;
}
@@ -474,18 +474,18 @@ int misc_init_r(void)
}
}
else {
- if ((ep = getenv("Daq128xSampling")) != NULL) {
+ if ((ep = getenv("Daq128xSampling")) != NULL) {
sample_128x = simple_strtol(ep, NULL, 10);
if (sample_128x) {
- sample_64x = 0;
+ sample_64x = 0;
}
else {
- sample_64x = 1;
+ sample_64x = 1;
}
}
}
- /*
+ /*
* Stop the clocks and wait for at least 1 LRCLK period
* to make sure the clocking has really stopped.
*/
@@ -509,12 +509,12 @@ int misc_init_r(void)
setenv("DaqSampleRate", str_buf);
if (sample_64x) {
- setenv("Daq64xSampling", "1");
- setenv("Daq128xSampling", NULL);
+ setenv("Daq64xSampling", "1");
+ setenv("Daq128xSampling", NULL);
}
else {
- setenv("Daq64xSampling", NULL);
- setenv("Daq128xSampling", "1");
+ setenv("Daq64xSampling", NULL);
+ setenv("Daq128xSampling", "1");
}
/* Display the ADC/DAC clocking information */
@@ -526,7 +526,7 @@ int misc_init_r(void)
right_just = INITIAL_RIGHT_JUST;
if ((ep = getenv("DaqDACRightJustified")) != NULL) {
- right_just = simple_strtol(ep, NULL, 10);
+ right_just = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", right_just);
@@ -538,7 +538,7 @@ int misc_init_r(void)
mclk_divide = INITIAL_MCLK_DIVIDE;
if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
- mclk_divide = simple_strtol(ep, NULL, 10);
+ mclk_divide = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", mclk_divide);
@@ -666,7 +666,7 @@ int misc_init_r(void)
*/
i2c_reg_write(I2C_DAC_ADDR, 0x01,
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
- DAC_REG1_LEFT_JUST_24_BIT) |
+ DAC_REG1_LEFT_JUST_24_BIT) |
DAC_REG1_DEM_NO |
(sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
@@ -724,7 +724,7 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
* Recursively do upper digits.
*/
if(digits > 1) {
- flash_code(number / modulo, modulo, digits - 1);
+ flash_code(number / modulo, modulo, digits - 1);
}
number = number % modulo;
@@ -733,20 +733,20 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
* Zero is indicated by one long flash (dash).
*/
if(number == 0) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(1000000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(1000000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
} else {
- /*
- * Non-zero is indicated by short flashes, one per count.
- */
- for(j = 0; j < number; j++) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(100000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- }
+ /*
+ * Non-zero is indicated by short flashes, one per count.
+ */
+ for(j = 0; j < number; j++) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(100000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ }
}
/*
* Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
@@ -759,16 +759,16 @@ static int last_boot_progress;
void show_boot_progress (int status)
{
if(status != -1) {
- last_boot_progress = status;
+ last_boot_progress = status;
} else {
- /*
- * Houston, we have a problem. Blink the last OK status which
- * indicates where things failed.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- flash_code(last_boot_progress, 5, 3);
- udelay(1000000);
- status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+ /*
+ * Houston, we have a problem. Blink the last OK status which
+ * indicates where things failed.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ flash_code(last_boot_progress, 5, 3);
+ udelay(1000000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
}
}
#endif /* CONFIG_SHOW_BOOT_PROGRESS */
diff --git a/board/sacsng/u-boot.lds b/board/sacsng/u-boot.lds
index b4e502b0d..44224cbdd 100644
--- a/board/sacsng/u-boot.lds
+++ b/board/sacsng/u-boot.lds
@@ -93,6 +93,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
@@ -115,4 +120,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}
-