diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/p3060_serdes.c | 20 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 10 |
2 files changed, 0 insertions, 30 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c index 6387276ba..e720dcf6b 100644 --- a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c @@ -83,8 +83,6 @@ void soc_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2); u32 rcwsr11 = in_be32(&gur->rcwsr[11]); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 ec1_ext, ec2_ext; /* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */ @@ -116,23 +114,5 @@ void soc_serdes_init(void) devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1; } - ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT; - if (ec1_ext) { - if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) || - (ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII)) - devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4; - } - - ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT; - if (ec2_ext) { - if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) || - (ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII)) - devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; - } - - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) == - FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII) - devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4; - out_be32(&gur->devdisr2, devdisr2); } diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index a29fe35cd..1bbf9867a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1708,16 +1708,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P3060) -#define FSL_CORENET_RCWSR13_EC1_EXT 0x1c000000 -#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII 0x04000000 -#define FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII 0x08000000 -#define FSL_CORENET_RCWSR13_EC2_EXT 0x01c00000 -#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII 0x00400000 -#define FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII 0x00800000 -#define FSL_CORENET_RCWSR13_EC3 0x00380000 -#define FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII 0x00100000 -#endif #if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \ || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 |