diff options
59 files changed, 22 insertions, 1169 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 80057ce1e..0abeb26dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -80,7 +80,6 @@ Torsten Demke <torsten.demke@fci.com> Wolfgang Denk <wd@denx.de> - IceCube_5100 MGT5100 IceCube_5200 MPC5200 ARIA MPC5121e @@ -61,7 +61,6 @@ LIST_5xxx=" \ EVAL5200 \ fo300 \ galaxy5200 \ - icecube_5100 \ icecube_5200 \ inka4x0 \ ipek01 \ @@ -76,7 +75,6 @@ LIST_5xxx=" \ pf5200 \ PM520 \ TB5200 \ - Total5100 \ Total5200 \ Total5200_Rev2 \ TQM5200 \ @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2009 +# (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -548,8 +548,7 @@ icecube_5200_LOWBOOT_config \ icecube_5200_LOWBOOT08_config \ icecube_5200_DDR_config \ icecube_5200_DDR_LOWBOOT_config \ -icecube_5200_DDR_LOWBOOT08_config \ -icecube_5100_config: unconfig +icecube_5200_DDR_LOWBOOT08_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/icecube @[ -z "$(findstring LOWBOOT_,$@)" ] || \ @@ -568,14 +567,6 @@ icecube_5100_config: unconfig { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \ $(XECHO) "... DDR memory revision" ; \ } - @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ - } - @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ - } @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube jupiter_config: unconfig @@ -594,7 +585,6 @@ lite5200b_LOWBOOT_config: unconfig @mkdir -p $(obj)board/icecube @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h @ $(XECHO) "... DDR memory revision" - @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h @[ -z "$(findstring _PM_,$@)" ] || \ { echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \ @@ -604,7 +594,6 @@ lite5200b_LOWBOOT_config: unconfig { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \ $(XECHO) "... with LOWBOOT configuration" ; \ } - @ $(XECHO) "... with MPC5200B processor" @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube mcc200_config \ @@ -728,21 +717,12 @@ TOP5200_config: unconfig @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk -Total5100_config \ Total5200_config \ Total5200_lowboot_config \ Total5200_Rev2_config \ Total5200_Rev2_lowboot_config: unconfig @mkdir -p $(obj)include @mkdir -p $(obj)board/total5200 - @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ - } - @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ - } @[ -n "$(findstring Rev,$@)" ] || \ { echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \ $(XECHO) "... revision 1 board" ; \ diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index 6fb0096be..3117b5fbf 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -204,57 +203,6 @@ phys_size_t initdram (int board_type) return dramsize; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_TQM5200) @@ -276,10 +224,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h index 3f1e1691b..48b43213d 100644 --- a/board/bc3450/mt48lc16m16a2-75.h +++ b/board/bc3450/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index dce07bf78..6ddc858ea 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -81,7 +81,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -183,57 +182,6 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { puts ("Board: CANMB\n"); diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h index ffdf0396a..15477259c 100644 --- a/board/canmb/mt48lc16m32s2-75.h +++ b/board/canmb/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/cpci5200/mt46v16m16-75.h +++ b/board/esd/cpci5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/mecp5200/mt46v16m16-75.h +++ b/board/esd/mecp5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/pf5200/mt46v16m16-75.h +++ b/board/esd/pf5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 75244610c..47b219555 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -134,7 +134,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -258,65 +257,12 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_LITE5200B) puts ("Board: Freescale Lite5200B\n"); -#elif defined(CONFIG_MPC5200) +#else puts ("Board: Motorola MPC5200 (IceCube)\n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: Motorola MGT5100 (IceCube)\n"); #endif return 0; } @@ -329,10 +275,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h index 4c0f9a740..eb857404f 100644 --- a/board/icecube/mt46v16m16-75.h +++ b/board/icecube/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h index de2b48bc6..519bf6d0f 100644 --- a/board/icecube/mt46v32m16.h +++ b/board/icecube/mt46v32m16.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/icecube/mt48lc16m16a2-75.h +++ b/board/icecube/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 6e752c655..967aabdcf 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -227,10 +227,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } @@ -248,10 +244,8 @@ void flash_afterinit(ulong size) *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } -#if defined(CONFIG_MPC5200) *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif } int update_flash_size (int flash_size) diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h index f650faaa1..423febe20 100644 --- a/board/mcc200/mt46v16m16-75.h +++ b/board/mcc200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/mcc200/mt48lc16m16a2-75.h +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h index ffdf0396a..15477259c 100644 --- a/board/mcc200/mt48lc16m32s2-75.h +++ b/board/mcc200/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/munices/mt48lc16m16a2-75.h +++ b/board/munices/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h index f650faaa1..423febe20 100644 --- a/board/pm520/mt46v16m16-75.h +++ b/board/pm520/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/pm520/mt48lc16m16a2-75.h +++ b/board/pm520/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 9da104173..d6914343f 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -84,7 +84,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -186,64 +185,9 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { -#if defined(CONFIG_MPC5200) puts ("Board: MicroSys PM520 \n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: MicroSys PM510 \n"); -#endif return 0; } @@ -255,10 +199,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h index 5b0923e3e..ae237c6ca 100644 --- a/board/total5200/mt48lc16m16a2-75.h +++ b/board/total5200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h index 4b5ac80b3..cb4b43d63 100644 --- a/board/total5200/mt48lc32m16a2-75.h +++ b/board/total5200/mt48lc32m16a2-75.h @@ -28,13 +28,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x514F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#else -#error CONFIG_MPC5200 is not defined -#endif diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c index dc4c6f18c..d883eb656 100644 --- a/board/total5200/sdram.c +++ b/board/total5200/sdram.c @@ -76,7 +76,6 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) { ulong dramsize = 0; @@ -174,54 +173,3 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) return dramsize + dramsize2; } - -#elif defined(CONFIG_MGT5100) - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel; - __asm__ volatile ("sync"); - - /* find RAM size */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h index bc21e1d30..396a19014 100644 --- a/board/total5200/sdram.h +++ b/board/total5200/sdram.h @@ -28,12 +28,7 @@ typedef struct { ulong control; ulong config1; ulong config2; -#if defined(CONFIG_MPC5200) ulong tapdelay; -#endif -#if defined(CONFIG_MGT5100) - ulong addrsel; -#endif } sdram_conf_t; long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index c524d63f9..61b5b807a 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -47,26 +47,17 @@ phys_size_t initdram (int board_type) sdram_conf.control = SDRAM_CONTROL; sdram_conf.config1 = SDRAM_CONFIG1; sdram_conf.config2 = SDRAM_CONFIG2; -#if defined(CONFIG_MPC5200) sdram_conf.tapdelay = 0; -#endif -#if defined(CONFIG_MGT5100) - sdram_conf.addrsel = SDRAM_ADDRSEL; -#endif return mpc5xxx_sdram_init (&sdram_conf); } int checkboard (void) { -#if defined(CONFIG_MPC5200) #if CONFIG_TOTAL5200_REV==2 puts ("Board: Total5200 Rev.2 "); #else puts ("Board: Total5200 "); #endif -#elif defined(CONFIG_MGT5100) - puts ("Board: Total5100 "); -#endif /* * Retrieve FPGA Revision. @@ -85,20 +76,6 @@ int checkboard (void) return 0; } -#if defined(CONFIG_MGT5100) -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable CS0 - * because CS_BOOT cannot be written. - */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ - - return 0; -} -#endif - #ifdef CONFIG_PCI static struct pci_controller hose; @@ -266,9 +243,7 @@ static const S1D_REGS init_regs [] = void video_get_info_str (int line_number, char *info) { if (line_number == 1) { -#ifdef CONFIG_MGT5100 - strcpy (info, " Total5100"); -#elif CONFIG_TOTAL5200_REV==1 +#if CONFIG_TOTAL5200_REV==1 strcpy (info, " Total5200"); #elif CONFIG_TOTAL5200_REV==2 strcpy (info, " Total5200 Rev.2"); diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h index 3f1e1691b..48b43213d 100644 --- a/board/tqc/tqm5200/mt48lc16m16a2-75.h +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile index 06fdbcfb7..0ee061155 100644 --- a/cpu/mpc5xxx/Makefile +++ b/cpu/mpc5xxx/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o +SOBJS = io.o firmware_sc_task_bestcomm.impl.o COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index edfb8282b..b20234d32 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -50,16 +50,10 @@ int checkcpu (void) { ulong clock = gd->cpu_clk; char buf[32]; -#ifndef CONFIG_MGT5100 uint svr, pvr; -#endif puts ("CPU: "); -#ifdef CONFIG_MGT5100 - puts (CPU_ID_STR); - printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); -#else svr = get_svr(); pvr = get_pvr(); @@ -77,7 +71,6 @@ int checkcpu (void) printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), PVR_MAJ(pvr), PVR_MIN(pvr)); -#endif printf (" at %s MHz\n", strmhz (buf, clock)); return 0; } diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index 560c9b311..9daf3755a 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -53,10 +53,6 @@ void cpu_init_f (void) (struct mpc5xxx_gpt *) MPC5XXX_GPT; #endif /* CONFIG_WATCHDOG */ unsigned long addecr = (1 << 25); /* Boot_CS */ - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) - addecr |= (1 << 22); /* SDRAM enable */ -#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -136,7 +132,6 @@ void cpu_init_f (void) out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG); #endif -#if defined(CONFIG_MPC5200) addecr |= 1; #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START)); @@ -164,14 +159,9 @@ void cpu_init_f (void) #if defined(CONFIG_SYS_CS_DEADCYCLE) out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE); #endif -#endif /* CONFIG_MPC5200 */ /* Enable chip selects */ -#if defined(CONFIG_MGT5100) - out_be32(&mm->addecr, addecr); -#elif defined(CONFIG_MPC5200) out_be32(&mm->ipbi_ws_ctrl, addecr); -#endif out_be32(&lpb->cs_ctrl, (1 << 24)); /* Setup pin multiplexing */ @@ -179,7 +169,6 @@ void cpu_init_f (void) out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); #endif -#if defined(CONFIG_MPC5200) /* enable timebase */ setbits_be32(&xlb->config, (1 << 13)); @@ -187,33 +176,29 @@ void cpu_init_f (void) setbits_be32(&xlb->config, (1 << 15)); out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d); -# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) +#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) /* Motorola reports IPB should better run at 133 MHz. */ -# if defined(CONFIG_MGT5100) - setbits_be32(&mm->addecr, 1); -# elif defined(CONFIG_MPC5200) setbits_be32(&mm->ipbi_ws_ctrl, 1); -# endif /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = in_be32(&cdm->cfg); addecr &= ~0x103; -# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) +# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ addecr |= 0x01; -# else +# else /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ addecr |= 0x02; -# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ +# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ out_be32(&cdm->cfg, addecr); -# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ +#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ /* Configure the XLB Arbiter */ out_be32(&xlb->master_pri_enable, 0xff); out_be32(&xlb->master_priority, 0x11111111); -# if defined(CONFIG_SYS_XLB_PIPELINING) +#if defined(CONFIG_SYS_XLB_PIPELINING) /* Enable piplining */ clrbits_be32(&xlb->config, (1 << 31)); -# endif +#endif #if defined(CONFIG_WATCHDOG) /* Charge the watchdog timer - prescaler = 64k, count = 64k*/ @@ -222,8 +207,6 @@ void cpu_init_f (void) reset_5xxx_watchdog(); #endif /* CONFIG_WATCHDOG */ - -#endif /* CONFIG_MPC5200 */ } /* @@ -235,11 +218,7 @@ int cpu_init_r (void) (struct mpc5xxx_intr *) MPC5XXX_ICTL; /* mask all interrupts */ -#if defined(CONFIG_MGT5100) - out_be32(&intr->per_mask, 0xfffffc00); -#elif defined(CONFIG_MPC5200) out_be32(&intr->per_mask, 0xffffff00); -#endif setbits_be32(&intr->main_mask, 0x0001ffff); clrbits_be32(&intr->ctrl, 0x00000f00); /* route critical ints to normal ints */ diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S deleted file mode 100644 index b668ee5cf..000000000 --- a/cpu/mpc5xxx/firmware_sc_task.impl.S +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MGT5100 CPU. - */ - -#include <config.h> - -#if defined(CONFIG_MGT5100) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0004800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0004800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.align 8 -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 256, 0x0 - - -.align 8 -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 256, 0x0 - -#endif /* CONFIG_MGT5100 */ diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S index d140c7e98..00c23121a 100644 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -6,8 +6,6 @@ #include <config.h> -#if defined(CONFIG_MPC5200) - /* sas/sccg, gas target */ .section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ .section smartdmaTaskTable,"aw",@progbits /* Task tables */ @@ -359,5 +357,3 @@ scEthernetRecv_CSave: /* Task 0 context save space */ .globl scEthernetXmit_CSave scEthernetXmit_CSave: /* Task 1 context save space */ .space 128, 0x0 - -#endif /* CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index 225738a07..8268f8afe 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -23,7 +23,7 @@ #include <common.h> -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) +#if defined(CONFIG_PCI) #include <asm/processor.h> #include <asm/io.h> @@ -184,4 +184,4 @@ void pci_mpc5xxx_init (struct pci_controller *hose) hose->last_busno = pci_hose_scan(hose); } -#endif /* CONFIG_PCI && CONFIG_MPC5200 */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index a8a384aa5..66759887c 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -50,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE MPC5XXX_PSC2 #elif CONFIG_PSC_CONSOLE == 3 #define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3 #elif CONFIG_PSC_CONSOLE == 4 #define PSC_BASE MPC5XXX_PSC4 #elif CONFIG_PSC_CONSOLE == 5 @@ -73,8 +71,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE2 MPC5XXX_PSC2 #elif CONFIG_PSC_CONSOLE2 == 3 #define PSC_BASE2 MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3 #elif CONFIG_PSC_CONSOLE2 == 4 #define PSC_BASE2 MPC5XXX_PSC4 #elif CONFIG_PSC_CONSOLE2 == 5 @@ -104,23 +100,14 @@ int serial_init (void) psc->command = PSC_SEL_MODE_REG_1; /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; -#endif /* switch to UART mode */ psc->sicr = 0; /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif psc->mode = PSC_MODE_ONE_STOP; /* set up UART divisor */ @@ -246,11 +233,7 @@ void serial_setbrg(void) #endif unsigned long baseclk, div; -#if defined(CONFIG_MGT5100) - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) baseclk = (gd->ipb_clk + 16) / 32; -#endif /* set up UART divisor */ div = (baseclk + (gd->baudrate/2)) / gd->baudrate; diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index d499da503..ba4994421 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -111,9 +111,6 @@ boot_warm: # if defined(CONFIG_SYS_RAMBOOT) # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT # endif /* CONFIG_SYS_RAMBOOT */ -# if defined(CONFIG_MGT5100) -# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100 -# endif /* CONFIG_MGT5100 */ lis r4, CONFIG_SYS_DEFAULT_MBAR@h lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l @@ -145,14 +142,9 @@ lowboot_reentry: #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) lis r3, CONFIG_SYS_MBAR@h ori r3, r3, CONFIG_SYS_MBAR@l -#if defined(CONFIG_MPC5200) /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 -#endif -#if defined(CONFIG_MGT5100) - rlwinm r3, r3, 17, 15, 31 -#endif lis r4, CONFIG_SYS_DEFAULT_MBAR@h stw r3, 0(r4) #endif /* CONFIG_SYS_DEFAULT_MBAR */ diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c index 66a4af8d8..7976e4df7 100644 --- a/cpu/mpc5xxx/usb_ohci.c +++ b/cpu/mpc5xxx/usb_ohci.c @@ -76,13 +76,8 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#ifdef CONFIG_MPC5200 #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) -#else -#define ohci_cpu_to_le16(x) swap_16(x) -#define ohci_cpu_to_le32(x) swap_32(x) -#endif /* global ohci_t */ static ohci_t gohci; @@ -803,9 +798,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci) } else td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); } -#ifdef CONFIG_MPC5200 td_list->hwNextTD = 0; -#endif } td_list->next_dl_td = td_rev; diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h index 6eedbdd1d..629b529a6 100644 --- a/cpu/mpc5xxx/usb_ohci.h +++ b/cpu/mpc5xxx/usb_ohci.h @@ -127,13 +127,8 @@ typedef struct td td_t; #define NUM_INTS 32 /* part of the OHCI standard */ struct ohci_hcca { __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) __u16 pad1; /* set to 0 on each frame_no change */ __u16 frame_no; /* current frame number */ -#else - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ -#endif __u32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc[116]; } __attribute__((aligned(256))); diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 1b20a76c4..8d0b6d604 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -36,8 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PSC_BASE MPC5XXX_PSC2 #elif CONFIG_PS2SERIAL == 3 #define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PS2SERIAL must be in 1, 2 or 3 #elif CONFIG_PS2SERIAL == 4 #define PSC_BASE MPC5XXX_PSC4 #elif CONFIG_PS2SERIAL == 5 @@ -87,23 +85,14 @@ int ps2ser_init(void) psc->command = PSC_SEL_MODE_REG_1; /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; -#endif /* switch to UART mode */ psc->sicr = 0; /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif psc->mode = PSC_MODE_ONE_STOP; /* set up UART divisor */ diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 1876b7684..c2b1bbdc7 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -336,13 +336,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) */ fec->eth->xmit_fsm = 0x03000000; -#if defined(CONFIG_MPC5200) /* - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't + * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't * work w/ the current receive task. */ sdma->PtdCntrl |= 0x00000001; -#endif /* * Set priority of different initiators @@ -579,9 +577,7 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) /********************************************************************/ static void mpc5xxx_fec_halt(struct eth_device *dev) { -#if defined(CONFIG_MPC5200) struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; -#endif mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; int counter = 0xffff; @@ -611,13 +607,11 @@ static void mpc5xxx_fec_halt(struct eth_device *dev) SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); -#if defined(CONFIG_MPC5200) /* - * Turn on COMM bus prefetch in the MGT5200 BestComm after we're + * Turn on COMM bus prefetch in the MPC5200 BestComm after we're * done. It doesn't work w/ the current receive task. */ sdma->PtdCntrl &= ~0x00000001; -#endif /* * Disable the Ethernet Controller diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 8c5a74229..44befe9ed 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -471,13 +471,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) -# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -# define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -# define CONFIG_SYS_HID0_INIT 0 -# define CONFIG_SYS_HID0_FINAL 0 -#endif +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5ef0b7798..5d3a744ff 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -30,6 +30,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_ICECUBE 1 /* ... on IceCube board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -47,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -77,10 +77,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else -#define CONFIG_MII 1 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,7 +165,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -178,7 +173,6 @@ #else #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif -#endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -338,13 +332,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_LITE5200B) #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/PM520.h b/include/configs/PM520.h index f9687d274..22de2075f 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -75,7 +74,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X -#endif /* Partitions */ #define CONFIG_DOS_PARTITION @@ -111,9 +109,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB -#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI -#endif /* @@ -147,12 +143,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -301,13 +295,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #if defined(CONFIG_BOOT_ROM) #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 3438abaea..6da18ebca 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -430,13 +430,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 2154c7870..107bff19f 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -633,13 +633,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 1daa5746e..7510ab10e 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -41,6 +41,7 @@ */ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ #define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -73,7 +74,6 @@ #define CONFIG_SPLASH_SCREEN -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -98,12 +98,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else /* MGT5100 */ - -#define CONFIG_MII 1 - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,9 +121,7 @@ */ #include <config_cmd_default.h> -#if defined(CONFIG_MPC5200) - #define CONFIG_CMD_PCI -#endif +#define CONFIG_CMD_PCI #define CONFIG_CMD_BMP #define CONFIG_CMD_EEPROM @@ -176,12 +168,10 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration @@ -326,17 +316,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif #if CONFIG_TOTAL5200_REV==1 # define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE diff --git a/include/configs/aev.h b/include/configs/aev.h index 2b4826d90..98958a623 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -362,13 +362,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 52df16af1..f7290d6eb 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -59,7 +59,6 @@ #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -90,8 +89,6 @@ #define CONFIG_NS8382X 1 #endif -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -169,8 +166,6 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) - #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 #define CONFIG_SYS_NVRAM_SIZE 32*1024 @@ -179,7 +174,6 @@ * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -303,13 +297,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index a81527ebe..f9cdcbc3c 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -261,13 +261,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 14f782670..c5b1565e3 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output) /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index d0cb1e1d6..6903b3614 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -324,13 +324,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index b29ef9b65..d25e093ac 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -170,13 +170,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 4a93b5888..73405eabb 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -63,9 +63,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ - #define CONFIG_MII #if 0 /* test-only !!! */ #define CONFIG_NET_MULTI 1 @@ -74,10 +71,6 @@ #define CONFIG_NS8382X 1 #endif -#else /* MPC5100 */ - -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -152,12 +145,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -288,13 +279,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 18e7cc2a9..bdc0f7944 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -138,7 +138,6 @@ #define CONFIG_BOOTCOMMAND "run flash_self" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ @@ -154,7 +153,6 @@ */ #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif -#endif /* * I2C configuration @@ -276,13 +274,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 8ca55d78e..80a0bc609 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -61,7 +61,6 @@ #endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory @@ -87,7 +86,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif -#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -121,9 +119,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE -#ifdef CONFIG_MPC5200 #define CONFIG_CMD_PCI -#endif #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ @@ -166,12 +162,10 @@ #define CONFIG_BOOTCOMMAND "run flash_vxworks0" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration */ @@ -289,13 +283,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 5a2ef3aa8..060026bb6 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -358,13 +358,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 27dda253f..d377e199d 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -438,13 +438,8 @@ /* * Various low-level settings */ -#if defined(CONFIG_MPC5200) #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI #define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 92bcdb33f..d462ed0f1 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -170,12 +170,10 @@ #define CONFIG_BOOTCOMMAND "run net_nfs" -#if defined(CONFIG_MPC5200) /* * IPB Bus clocking configuration. */ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#endif /* * I2C configuration diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 4dcf90c03..2d343c7b0 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -1,7 +1,7 @@ /* * include/asm-ppc/mpc5xxx.h * - * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx + * Prototypes, etc. for the Motorola MPC5xxx * embedded cpu chips * * 2003 (c) MontaVista, Software, Inc. @@ -33,24 +33,15 @@ #include <asm/types.h> /* Processor name */ -#if defined(CONFIG_MPC5200) #define CPU_ID_STR "MPC5200" -#elif defined(CONFIG_MGT5100) -#define CPU_ID_STR "MGT5100" -#endif /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 #define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ -#if defined(CONFIG_MGT5100) -#define START_REG(start) ((start) >> 15) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 15) -#elif defined(CONFIG_MPC5200) #define START_REG(start) ((start) >> 16) #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) -#endif /* Internal memory map */ @@ -70,21 +61,12 @@ #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038) -#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c) -#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040) -#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044) -#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) -#endif #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) @@ -99,18 +81,12 @@ #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) -#endif #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) @@ -118,22 +94,14 @@ #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000) -#define MPC5XXX_SRAM_SIZE (8*1024) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) #define MPC5XXX_SRAM_SIZE (16*1024) -#endif /* SDRAM Controller */ #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) -#endif #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ @@ -155,19 +123,15 @@ #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#if defined(CONFIG_MPC5200) #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) -#endif -#if defined(CONFIG_MPC5200) /* XLB Arbiter registers */ #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) -#endif /* GPIO registers */ #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) @@ -242,14 +206,6 @@ #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#if defined(CONFIG_MGT5100) -#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) -#elif defined(CONFIG_MPC5200) #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) @@ -262,7 +218,6 @@ #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) -#endif /* Interrupt Controller registers */ #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) @@ -495,31 +450,16 @@ struct mpc5xxx_mmap_ctl { volatile u32 cs4_stop; volatile u32 cs5_start; /* 0x002c */ volatile u32 cs5_stop; -#if defined(CONFIG_MGT5100) - volatile u32 sdram_start; /* 0x0034 */ - volatile u32 sdram_stop; /* 0x0038 */ - volatile u32 pci1_start; /* 0x003c */ - volatile u32 pci1_stop; /* 0x0040 */ - volatile u32 pci2_start; /* 0x0044 */ - volatile u32 pci2_stop; /* 0x0048 */ -#elif defined(CONFIG_MPC5200) volatile u32 sdram0; /* 0x0034 */ volatile u32 sdram1; /* 0x0038 */ volatile u32 dummy1[4]; /* 0x003c */ -#endif volatile u32 boot_start; /* 0x004c */ volatile u32 boot_stop; -#if defined(CONFIG_MGT5100) - volatile u32 addecr; /* 0x0054 */ -#elif defined(CONFIG_MPC5200) volatile u32 ipbi_ws_ctrl; /* 0x0054 */ -#endif -#if defined(CONFIG_MPC5200) volatile u32 cs6_start; /* 0x0058 */ volatile u32 cs6_stop; volatile u32 cs7_start; /* 0x0060 */ volatile u32 cs7_stop; -#endif }; /* Clock distribution module */ @@ -546,12 +486,7 @@ struct mpc5xxx_sdram { volatile u32 ctrl; volatile u32 config1; volatile u32 config2; -#if defined(CONFIG_MGT5100) - volatile u32 xlbsel; - volatile u32 dummy[31]; -#else volatile u32 dummy[32]; -#endif volatile u32 sdelay; }; @@ -564,12 +499,10 @@ struct mpc5xxx_lpb { volatile u32 cs5_cfg; volatile u32 cs_ctrl; volatile u32 cs_status; -#if defined(CONFIG_MPC5200) volatile u32 cs6_cfg; volatile u32 cs7_cfg; volatile u32 cs_burst; volatile u32 cs_deadcycle; -#endif }; |