diff options
30 files changed, 1725 insertions, 1296 deletions
@@ -1,3 +1,9 @@ +commit 8d9a8610b8256331132227e9e6585c6bd5742787 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Thu Nov 30 01:54:07 2006 +0100 + + Code cleanup. Update CHANGELOG. + commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba Author: Grant Likely <grant.likely@secretlab.ca> Date: Wed Nov 29 16:23:42 2006 +0100 @@ -52,6 +58,49 @@ Date: Wed Nov 29 12:03:57 2006 +0100 Signed-off-by: Jeff Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de> +commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a +Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> +Date: Tue Nov 28 16:17:27 2006 -0600 + + Make fsl-i2c not conflict with SOFT I2C + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 14198bf768fdc958e3c1afd2404e5262208e98d7 +Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> +Date: Tue Nov 28 16:17:18 2006 -0600 + + Fix I2C master address initialization. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit cf3d045e51ca8dcc6cf759827140861d6ac25c04 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Nov 28 23:31:19 2006 -0600 + + Assign maintainers for mpc8349emds and mpc8360emds + + Dave for mpc8360emds, and me for mpc8349emds. + +commit 1aa934c81b77f2080d3ca4b226eab67b17a33961 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Nov 28 23:28:33 2006 -0600 + + Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c + + give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src + since they are passed by reference to ucc_get_cmxucr_reg and assigned. + +commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Nov 28 12:09:35 2006 -0600 + + mpc83xx: Miscellaneous code style fixes + + Implement various code style fixes and similar changes. + + Signed-off-by: Timur Tabi <timur@freescale.com> + commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706 Author: Stefan Roese <sr@denx.de> Date: Tue Nov 28 17:55:49 2006 +0100 @@ -268,6 +317,379 @@ Date: Mon Nov 6 17:06:36 2006 +0100 This fixes get_ram_size() problems on MPC5200 Rev. B boards. +commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa +Author: Timur Tabi <timur@freescale.com> +Date: Fri Nov 3 19:15:00 2006 -0600 + + mpc83xx: Update 83xx to use fsl_i2c.c + + Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete + cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. + Added multiple I2C bus support to fsl_i2c.c. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit d239d74b1c937984bc519083a8e7de373a390f06 +Author: Timur Tabi <timur@freescale.com> +Date: Fri Nov 3 12:00:28 2006 -0600 + + mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR + + Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx + tree matches the other 8xxx trees. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit f7fb2e703ec9688541416962724adff70a7322cb +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Nov 2 19:47:11 2006 -0600 + + mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c + +commit 90f30a710a3c619b5405860a686c4ddfc495d4b6 +Author: Dave Liu <daveliu@freescale.com> +Date: Thu Nov 2 18:05:50 2006 -0600 + + mpc83xx: Fix the incorrect dcbz operation + + The 834x rev1.x silicon has one CPU5 errata. + + The issue is when the data cache locked with + HID0[DLOCK], the dcbz instruction looks like no-op inst. + + The right behavior of the data cache is when the data cache + Locked with HID0[DLOCK], the dcbz instruction allocates + new tags in cache. + + The 834x rev3.0 and later and 8360 have not this bug inside. + + So, when 834x rev3.0/8360 are working with ECC, the dcbz + instruction will corrupt the stack in cache, the processor will + checkstop reset. + + However, the 834x rev1.x can work with ECC with these code, + because the sillicon has this cache bug. The dcbz will not + corrupt the stack in cache. + Really, it is the fault code running on fault sillicon. + + This patch fix the incorrect dcbz operation. Instead of + CPU FP writing to initialise the ECC. + + CHANGELOG: + * Fix the incorrect dcbz operation instead of CPU FP + writing to initialise the ECC memory. Otherwise, it + will corrupt the stack in cache, The processor will checkstop + reset. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Nov 1 00:10:40 2006 -0600 + + mpc83xx: add OF_FLAT_TREE bits to 83xx boards + + add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and + STDOUT_PATH configuration bits to mpc8349emds, + mpc8349itx, and mpc8360emds board code. + + redo environment to use bootm with the fdtaddr + for booting ARCH=powerpc kernels by default, + and provide default fdtaddr values. + +commit 48041365b3420589ad464ebc7752e0053538b729 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Nov 1 00:07:25 2006 -0600 + + mpc83xx: change ft code to modify local-mac-address property + + Update 83xx OF code to update local-mac-address properties + for ethernet instead of the obsolete 'address' property. + +commit 9ca880a250870a7d55754291b5591d2b5fe89b54 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Oct 31 21:23:16 2006 -0600 + + mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS + + This patch also adds an improved I2C set_speed(), which handles all clock + frequencies. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit ac4b5622ce050b5ee1e154b98df630d778661632 +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Oct 31 19:54:59 2006 -0600 + + mpc83xx: add the README.mpc8360emds + + add doc/README.mpc8360emds to accompany the new board support + +commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 3 12:11:15 2006 -0600 + + mpc83xx: add QE ethernet support + + this patch adds support for the QUICC Engine based UCC gigabit ethernet device. + +commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 3 19:33:44 2006 -0600 + + mpc83xx: Add MPC8360EMDS basic board support + + Add support for the Freescale MPC8360EMDS board. + Includes DDR, DUART, Local Bus, PCI. + +commit 23892e49352de74f7fac36ff90bb1be143d195e3 +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Oct 31 19:30:40 2006 -0600 + + mpc83xx: add the QUICC Engine (QE) immap file + + common QE immap file. Also required for 8360. + +commit b701652a4992bdcc62fb1a6038a85beef9e55da4 +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Oct 31 19:25:38 2006 -0600 + + mpc83xx: Add 8360 specifics to 83xx immap + + Mainly add QE device dependencies, with appropriate 8360 protection. + Lindent also run. + +commit 988833324a7fda482c8ac3ca23eb539f8232e404 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Oct 31 19:14:41 2006 -0600 + + mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX + + PREREQUISITE PATCHES: + + * This patch can only be applied after the following patches have been applied: + + 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" + 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" + + CHANGELOG: + + * For the 8349E-mITX, fix some size values in pci_init_board(), enable + the clock for the 2nd USB board (Linux kernel will hang otherwise), + and fix the CONFIG_BOOTARGS macro. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Oct 31 18:44:42 2006 -0600 + + mpc83xx: Add support for the MPC8349E-mITX + + PREREQUISITE PATCHES: + + * This patch can only be applied after the following patches have been applied: + + 1) DNX#2006090742000024 "Add support for multiple I2C buses" + 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" + 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" + 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" + 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" + + CHANGELOG: + + * Add support for the Freescale MPC8349E-mITX reference design platform. + The second TSEC (Vitesse 7385 switch) is not supported at this time. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 183da6d9b446cc12123455844ad1187e2375626f +Author: Ben Warren <bwarren@qstreams.com> +Date: Tue Sep 12 10:15:53 2006 -0400 + + Additional MPC8349 support for multibus i2c + + Hello, + + Here is a patch for a file that was accidentally left out of a previous + attempt. + + It accompanies the patch with ticket DNX#2006090742000024 + + CHANGELOG: + Change PCI initialization to use new multi-bus I2C API. + + regards, + Ben + +commit b24f119d672b709d153ff2ac091d4aa63ec6877d +Author: Ben Warren <bwarren@qstreams.com> +Date: Thu Sep 7 16:51:04 2006 -0400 + + Multi-bus I2C implementation of MPC834x + + Hello, + + Attached is a patch implementing multiple I2C buses on the MPC834x CPU + family and the MPC8349EMDS board in particular. + This patch requires Patch 1 (Add support for multiple I2C buses). + Testing was performed on a 533MHz board. + + /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ + + Signed-off-by: Ben Warren <bwarren@qstreams.com> + + CHANGELOG: + Implemented driver-level code to support two I2C buses on the + MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds + are 50kHz, 100kHz and 400kHz on each bus. + + regards, + Ben + +commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae +Author: Ben Warren <bwarren@qstreams.com> +Date: Thu Sep 7 16:50:54 2006 -0400 + + Add support for multiple I2C buses + + Hello, + + Attached is a patch providing support for multiple I2C buses at the + command level. The second part of the patch includes an implementation + for the MPC834x CPU and MPC8349EMDS board. + + /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ + + Signed-off-by: Ben Warren <bwarren@qstreams.com> + + Overview: + + 1. Include new 'i2c' command (based on USB implementation) using + CONFIG_I2C_CMD_TREE. + + 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that + the commands to change bus number and speed are only available under the + new 'i2c' command mentioned in the first bullet. + + 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus + systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form + of an array of bus-device pairs. Otherwise, it is an array of uchar. + + CHANGELOG: + Added new 'i2c' master command for all I2C interaction. This is + conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for + setting I2C bus speed as well as changing the active bus if the board + has more than one (conditionally compiled with + CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. + Updated README. + + regards, + Ben + +commit bed85caf872714ebf53013967a695c9d63acfc68 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Oct 31 18:13:36 2006 -0600 + + mpc83xx: Add support for Errata DDR6 on MPC 834x systems + + CHANGELOG: + + * Errata DDR6, which affects all current MPC 834x processors, lists changes + required to maintain compatibility with various types of DDR memory. This + patch implements those changes. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit afd6e470f639883002c7c59d562690a5cb0f4865 +Author: Timur Tabi <timur@freescale.com> +Date: Wed Oct 25 18:45:23 2006 -0500 + + mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it + +commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a +Author: Timur Tabi <timur@freescale.com> +Date: Tue Aug 22 17:07:00 2006 -0500 + + mpc83xx: Add support for variable flash memory sizes on 83xx systems + + CHANGELOG: + + * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access + window registers, instead of using a hard-coded value of 8MB. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965 +Author: Tanya Jiang <tanya.jiang@freescale.com> +Date: Thu Aug 3 18:38:13 2006 +0800 + + mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros + + Unified TQM834x variable names with 83xx and consolidated macro + in preparation for the 8360 and other upcoming 83xx devices. + + Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com> + +commit f6eda7f80ccc13d658020268c507d7173cf2e8aa +Author: Dave Liu <daveliu@freescale.com> +Date: Wed Oct 25 14:41:21 2006 -0500 + + mpc83xx: Changed to unified mpx83xx names and added common 83xx changes + + Incorporated the common unified variable names and the changes in preparation + for releasing mpc8360 patches. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 3894c46c27c64891f93ac04edde86a9fa9758d92 +Author: Tanya Jiang <tanya.jiang@freescale.com> +Date: Thu Aug 3 18:36:02 2006 +0800 + + mpc83xx: Fix missing build for mpc8349emds pci.c + + Make pci build for mpc8349emds + + Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com> + +commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219 +Author: Tanya Jiang <tanya.jiang@freescale.com> +Date: Thu Aug 3 18:39:49 2006 +0800 + + mpc83xx: Removed unused file resetvec.S for mpc83xx cpu + + Removed unused file resetvec.S for mpc83xx cpu + + Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com> + +commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf +Author: Nick Spence <Nick.Spence@freescale.com> +Date: Sat Sep 30 00:32:59 2006 -0700 + + NAND Flash verify across block boundaries + + This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is + defined + and the write crosses a block boundary. The pointer to the verification + buffer (bufstart) is not being updated to reflect the starting of the + new + block so the verification of the second block fails. + + CHANGELOG: + + * Fix NAND FLASH page verification across block boundaries + +commit f484dc791a3932537213c43c654cc1295c64b84c +Author: Nick Spence <nick.spence@freescale.com> +Date: Thu Sep 7 07:39:46 2006 -0700 + + Added RGMII support to the TSECs and Marvell 881111 Phy + + Added a phy initialization to adjust the RGMII RX and TX timing + Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode + + Signed-off-by: Nick Spence <nick.spence@freescale.com> + commit c59200443072353044aa4bf737a5a60f9a9af231 Author: Wolfgang Denk <wd@pollux.denx.de> Date: Thu Nov 2 15:15:01 2006 +0100 @@ -93,7 +93,7 @@ MKCONFIG := $(SRCTREE)/mkconfig export MKCONFIG ifneq ($(OBJTREE),$(SRCTREE)) -REMOTE_BUILD := 1 +REMOTE_BUILD := 1 export REMOTE_BUILD endif @@ -378,8 +378,8 @@ Lite5200_LOWBOOT08_config \ icecube_5200_config \ icecube_5200_LOWBOOT_config \ icecube_5200_LOWBOOT08_config \ -icecube_5200_DDR_config \ -icecube_5200_DDR_LOWBOOT_config \ +icecube_5200_DDR_config \ +icecube_5200_DDR_LOWBOOT_config \ icecube_5200_DDR_LOWBOOT08_config \ icecube_5100_config: unconfig @mkdir -p $(obj)include @@ -458,7 +458,7 @@ prs200_highboot_DDR_config: unconfig @[ -n "$(findstring _SDRAM,$@)" ] || \ { if [ -n "$(findstring mcc200,$@)" ]; \ then \ - echo "... with DDR" ; \ + echo "... with DDR" ; \ else \ if [ -n "$(findstring _DDR,$@)" ];\ then \ @@ -865,9 +865,9 @@ RPXClassic_config: unconfig RPXlite_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite -RPXlite_DW_64_config \ -RPXlite_DW_LCD_config \ -RPXlite_DW_64_LCD_config \ +RPXlite_DW_64_config \ +RPXlite_DW_LCD_config \ +RPXlite_DW_64_LCD_config \ RPXlite_DW_NVRAM_config \ RPXlite_DW_NVRAM_64_config \ RPXlite_DW_NVRAM_LCD_config \ @@ -880,12 +880,12 @@ RPXlite_DW_config: unconfig echo "... with 64MHz system clock ..."; \ } @[ -z "$(findstring _LCD,$@)" ] || \ - { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \ echo "... with LCD display ..."; \ } @[ -z "$(findstring _NVRAM,$@)" ] || \ - { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \ + { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \ echo "... with ENV in NVRAM ..."; \ } @$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw @@ -1821,7 +1821,7 @@ ap966_config \ ap922_config \ ap922_XA10_config \ ap7_config \ -ap720t_config \ +ap720t_config \ ap920t_config \ ap926ejs_config \ ap946es_config: unconfig @@ -1978,7 +1978,7 @@ cm4008_config : unconfig cm41xx_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 -gth2_config : unconfig +gth2_config : unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h @@ -2124,19 +2124,19 @@ tb0229_config: unconfig ######################################################################### ## MIPS32 AU1X00 ######################################################################### -dbau1000_config : unconfig +dbau1000_config : unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 -dbau1100_config : unconfig +dbau1100_config : unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 -dbau1500_config : unconfig +dbau1500_config : unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h @@ -2154,7 +2154,7 @@ dbau1550_el_config : unconfig @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 -pb1000_config : unconfig +pb1000_config : unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index f18313d51..dcfd83ed2 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -50,13 +50,13 @@ long int initdram (int board_type) MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0) | MCFSDRAMC_DACR_CASL(1) - | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_16); MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; *(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; @@ -70,10 +70,10 @@ long int initdram (int board_type) #ifdef CFG_SDRAM_BASE1 MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL(1) - | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_16; - MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M + MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; @@ -82,7 +82,7 @@ long int initdram (int board_type) MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i=0; i < 2000; i++) asm(" nop"); - MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; *(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; size += CFG_SDRAM_SIZE1 * 1024 * 1024; #endif diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c index 493881791..4b46b7c9a 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.c +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -66,7 +66,7 @@ int init_vcxk(void) return 1; } -void vcxk_loadimage(ulong source) +void vcxk_loadimage(ulong source) { int cnt; vcxk_acknowledge_wait(); diff --git a/board/BuS/EB+MCF-EV123/VCxK.h b/board/BuS/EB+MCF-EV123/VCxK.h index 74467ba98..f591e5c52 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.h +++ b/board/BuS/EB+MCF-EV123/VCxK.h @@ -25,24 +25,24 @@ #define __VCXK_H_ extern int init_vcxk(void); -void vcxk_loadimage(ulong source); +void vcxk_loadimage(ulong source); #define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR +#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR #define VIDEO_ACKNOWLEDGE_PIN 0x0001 -#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT -#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR +#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT +#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR #define VIDEO_ENABLE_PIN 0x0002 -#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT -#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR +#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT +#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR #define VIDEO_REQUEST_PIN 0x0004 #define VIDEO_Invert_CFG MCFGPIO_PEPAR #define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2 -#define VIDEO_INVERT_PORT MCFGPIO_PORTE -#define VIDEO_INVERT_DDR MCFGPIO_DDRE +#define VIDEO_INVERT_PORT MCFGPIO_PORTE +#define VIDEO_INVERT_DDR MCFGPIO_DDRE #define VIDEO_INVERT_PIN MCFGPIO_PORT2 #endif diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c index 6ecf0d1f5..b32638410 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.c +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -60,7 +60,7 @@ void cfm_flash_init (flash_info_t * info) MCFCFM_MCR = 0; MCFCFM_CLKD = CFM_CLK; debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ - CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ CFG_CLK); MCFCFM_SACC = 0; MCFCFM_DACC = 0; diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index ba76bef12..5e2647dda 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -256,7 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) enable_interrupts (); if (cflag) - icache_enable (); + icache_enable (); return rc; } diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds index d790018d2..ac532451c 100644 --- a/board/BuS/EB+MCF-EV123/u-boot.lds +++ b/board/BuS/EB+MCF-EV123/u-boot.lds @@ -34,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index b09fc3390..214752d9c 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -43,11 +43,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 6f5af91fd..17f99eb84 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -43,11 +43,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile index cb6ea2629..fa28d3b49 100644 --- a/board/MAI/AmigaOneG3SE/Makefile +++ b/board/MAI/AmigaOneG3SE/Makefile @@ -30,7 +30,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \ - via686.o i8259.o ../bios_emulator/x86interface.o \ + via686.o i8259.o ../bios_emulator/x86interface.o \ ../bios_emulator/bios.o ../bios_emulator/glue.o \ interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \ ../menu/cmd_menu.o cmd_boota.o nvram.o diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c index 480dae5b9..45b819501 100644 --- a/board/MAI/AmigaOneG3SE/articiaS_pci.c +++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c @@ -368,11 +368,11 @@ void articiaS_pci_init (void) if (articiaS_init_vga() == -1) { /* If the VGA didn't init and we have stdout set to VGA, reset to serial */ -/* s = getenv("stdout"); */ -/* if (s && strcmp(s, "vga") == 0) */ -/* { */ -/* setenv("stdout", "serial"); */ -/* } */ +/* s = getenv("stdout"); */ +/* if (s && strcmp(s, "vga") == 0) */ +/* { */ +/* setenv("stdout", "serial"); */ +/* } */ } } pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c index d4be889ea..ad2bcdeff 100644 --- a/board/MAI/AmigaOneG3SE/enet.c +++ b/board/MAI/AmigaOneG3SE/enet.c @@ -41,57 +41,57 @@ /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ -#define TotalReset (0<<11) -#define SelectWindow (1<<11) -#define StartCoax (2<<11) -#define RxDisable (3<<11) -#define RxEnable (4<<11) -#define RxReset (5<<11) -#define UpStall (6<<11) -#define UpUnstall (6<<11)+1 -#define DownStall (6<<11)+2 -#define DownUnstall (6<<11)+3 -#define RxDiscard (8<<11) -#define TxEnable (9<<11) -#define TxDisable (10<<11) -#define TxReset (11<<11) -#define FakeIntr (12<<11) -#define AckIntr (13<<11) -#define SetIntrEnb (14<<11) -#define SetStatusEnb (15<<11) -#define SetRxFilter (16<<11) -#define SetRxThreshold (17<<11) -#define SetTxThreshold (18<<11) -#define SetTxStart (19<<11) -#define StartDMAUp (20<<11) -#define StartDMADown (20<<11)+1 +#define TotalReset (0<<11) +#define SelectWindow (1<<11) +#define StartCoax (2<<11) +#define RxDisable (3<<11) +#define RxEnable (4<<11) +#define RxReset (5<<11) +#define UpStall (6<<11) +#define UpUnstall (6<<11)+1 +#define DownStall (6<<11)+2 +#define DownUnstall (6<<11)+3 +#define RxDiscard (8<<11) +#define TxEnable (9<<11) +#define TxDisable (10<<11) +#define TxReset (11<<11) +#define FakeIntr (12<<11) +#define AckIntr (13<<11) +#define SetIntrEnb (14<<11) +#define SetStatusEnb (15<<11) +#define SetRxFilter (16<<11) +#define SetRxThreshold (17<<11) +#define SetTxThreshold (18<<11) +#define SetTxStart (19<<11) +#define StartDMAUp (20<<11) +#define StartDMADown (20<<11)+1 #define StatsEnable (21<<11) #define StatsDisable (22<<11) -#define StopCoax (23<<11) -#define SetFilterBit (25<<11) +#define StopCoax (23<<11) +#define SetFilterBit (25<<11) /* The SetRxFilter command accepts the following classes */ -#define RxStation 1 +#define RxStation 1 #define RxMulticast 2 #define RxBroadcast 4 -#define RxProm 8 +#define RxProm 8 /* 3Com status word defnitions */ -#define IntLatch 0x0001 -#define HostError 0x0002 -#define TxComplete 0x0004 -#define TxAvailable 0x0008 -#define RxComplete 0x0010 -#define RxEarly 0x0020 -#define IntReq 0x0040 -#define StatsFull 0x0080 -#define DMADone (1<<8) -#define DownComplete (1<<9) -#define UpComplete (1<<10) -#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ -#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ +#define IntLatch 0x0001 +#define HostError 0x0002 +#define TxComplete 0x0004 +#define TxAvailable 0x0008 +#define RxComplete 0x0010 +#define RxEarly 0x0020 +#define IntReq 0x0040 +#define StatsFull 0x0080 +#define DMADone (1<<8) +#define DownComplete (1<<9) +#define UpComplete (1<<10) +#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ +#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ /* Polling Registers */ @@ -100,17 +100,17 @@ /* Register window 0 offets */ -#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ -#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ +#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ +#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ #define IntrStatus 0x0E /* Valid in all windows. */ /* Register window 0 EEPROM bits */ -#define EEPROM_Read 0x80 -#define EEPROM_WRITE 0x40 -#define EEPROM_ERASE 0xC0 -#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ -#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ +#define EEPROM_Read 0x80 +#define EEPROM_WRITE 0x40 +#define EEPROM_ERASE 0xC0 +#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ +#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ /* EEPROM locations. */ @@ -129,13 +129,13 @@ /* Register window 1 offsets, the window used in normal operation */ -#define TX_FIFO 0x10 -#define RX_FIFO 0x10 -#define RxErrors 0x14 -#define RxStatus 0x18 +#define TX_FIFO 0x10 +#define RX_FIFOa 0x10 +#define RxErrors 0x14 +#define RxStatus 0x18 #define Timer 0x1A -#define TxStatus 0x1B -#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ +#define TxStatus 0x1B +#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ /* Register Window 2 */ @@ -147,47 +147,47 @@ #define Wn3_MAC_Ctrl 6 #define Wn3_Options 8 -#define BFEXT(value, offset, bitcount) \ +#define BFEXT(value, offset, bitcount) \ ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) #define BFINS(lhs, rhs, offset, bitcount) \ - (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ + (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) #define RAM_SIZE(v) BFEXT(v, 0, 3) -#define RAM_WIDTH(v) BFEXT(v, 3, 1) -#define RAM_SPEED(v) BFEXT(v, 4, 2) +#define RAM_WIDTH(v) BFEXT(v, 3, 1) +#define RAM_SPEED(v) BFEXT(v, 4, 2) #define ROM_SIZE(v) BFEXT(v, 6, 2) -#define RAM_SPLIT(v) BFEXT(v, 16, 2) +#define RAM_SPLIT(v) BFEXT(v, 16, 2) #define XCVR(v) BFEXT(v, 20, 4) -#define AUTOSELECT(v) BFEXT(v, 24, 1) +#define AUTOSELECT(v) BFEXT(v, 24, 1) /* Register Window 4: Xcvr/media bits */ -#define Wn4_FIFODiag 4 -#define Wn4_NetDiag 6 +#define Wn4_FIFODiag 4 +#define Wn4_NetDiag 6 #define Wn4_PhysicalMgmt 8 -#define Wn4_Media 10 +#define Wn4_Media 10 -#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ -#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ -#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ -#define Media_LnkBeat 0x0800 +#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ +#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ +#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ +#define Media_LnkBeat 0x0800 /* Register Window 7: Bus Master control */ -#define Wn7_MasterAddr 0 -#define Wn7_MasterLen 6 -#define Wn7_MasterStatus 12 +#define Wn7_MasterAddr 0 +#define Wn7_MasterLen 6 +#define Wn7_MasterStatus 12 /* Boomerang bus master control registers. */ -#define PktStatus 0x20 +#define PktStatus 0x20 #define DownListPtr 0x24 -#define FragAddr 0x28 -#define FragLen 0x2c +#define FragAddr 0x28 +#define FragLen 0x2c #define TxFreeThreshold 0x2f -#define UpPktStatus 0x30 +#define UpPktStatus 0x30 #define UpListPtr 0x38 /* The Rx and Tx descriptor lists. */ diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c index 12acc5717..d741e6b5c 100644 --- a/board/emk/top5200/top5200.c +++ b/board/emk/top5200/top5200.c @@ -190,7 +190,7 @@ void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; } diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index f14331beb..a925b84fd 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -191,8 +191,7 @@ static struct pci_controller hose; extern void pci_mpc5xxx_init(struct pci_controller *); -void pci_init_board(void - ) { +void pci_init_board(void) { pci_mpc5xxx_init(&hose); } #endif diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 1f30d454f..77e164bd1 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -191,8 +191,7 @@ static struct pci_controller hose; extern void pci_mpc5xxx_init(struct pci_controller *); -void pci_init_board(void - ) { +void pci_init_board(void) { pci_mpc5xxx_init(&hose); } #endif diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index ddad1bbb9..700c9d932 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -316,7 +316,7 @@ void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index bb60e730b..d6a12b82a 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -74,7 +74,7 @@ pib_init(void) */ /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7286726f1..b011b5e3d 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -684,178 +684,182 @@ extern int nand_write_oob(struct nand_chip *nand, size_t ofs, size_t len, size_t *retlen, const u_char *buf); -int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - int rcode = 0; - - switch (argc) { - case 0: - case 1: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 2: - if (strcmp(argv[1],"info") == 0) { - int i; + int rcode = 0; - putc ('\n'); + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strcmp (argv[1], "info") == 0) { + int i; - for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) { - if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) - continue; /* list only known devices */ - printf ("Device %d: ", i); - nand_print(&nand_dev_desc[i]); - } - return 0; + putc ('\n'); - } else if (strcmp(argv[1],"device") == 0) { - if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d: ", curr_device); - nand_print(&nand_dev_desc[curr_device]); - return 0; + for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) { + if (nand_dev_desc[i].ChipID == + NAND_ChipID_UNKNOWN) + continue; /* list only known devices */ + printf ("Device %d: ", i); + nand_print (&nand_dev_desc[i]); + } + return 0; - } else if (strcmp(argv[1],"bad") == 0) { - if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d bad blocks:\n", curr_device); - nand_print_bad(&nand_dev_desc[curr_device]); - return 0; + } else if (strcmp (argv[1], "device") == 0) { + if ((curr_device < 0) + || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d: ", curr_device); + nand_print (&nand_dev_desc[curr_device]); + return 0; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 3: - if (strcmp(argv[1],"device") == 0) { - int dev = (int)simple_strtoul(argv[2], NULL, 10); + } else if (strcmp (argv[1], "bad") == 0) { + if ((curr_device < 0) + || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d bad blocks:\n", curr_device); + nand_print_bad (&nand_dev_desc[curr_device]); + return 0; - printf ("\nDevice %d: ", dev); - if (dev >= CFG_MAX_NAND_DEVICE) { - puts ("unknown device\n"); - return 1; } - nand_print(&nand_dev_desc[dev]); - /*nand_print (dev);*/ + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp (argv[1], "device") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); - if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { - return 1; - } + printf ("\nDevice %d: ", dev); + if (dev >= CFG_MAX_NAND_DEVICE) { + puts ("unknown device\n"); + return 1; + } + nand_print (&nand_dev_desc[dev]); + /*nand_print (dev); */ + + if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { + return 1; + } - curr_device = dev; + curr_device = dev; - puts ("... is now current device\n"); + puts ("... is now current device\n"); - return 0; - } - else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { - struct nand_chip* nand = &nand_dev_desc[curr_device]; - ulong off = 0; - ulong size = nand->totlen; - int ret; + return 0; + } else if (strcmp (argv[1], "erase") == 0 + && strcmp (argv[2], "clean") == 0) { + struct nand_chip *nand = &nand_dev_desc[curr_device]; + ulong off = 0; + ulong size = nand->totlen; + int ret; - printf ("\nNAND erase: device %d offset %ld, size %ld ... ", - curr_device, off, size); + printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); - ret = nand_legacy_erase (nand, off, size, 1); + ret = nand_legacy_erase (nand, off, size, 1); - printf("%s\n", ret ? "ERROR" : "OK"); + printf ("%s\n", ret ? "ERROR" : "OK"); - return ret; - } + return ret; + } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - default: - /* at least 4 args */ - - if (strncmp(argv[1], "read", 4) == 0 || - strncmp(argv[1], "write", 5) == 0) { - ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong off = simple_strtoul(argv[3], NULL, 16); - ulong size = simple_strtoul(argv[4], NULL, 16); - int cmd = (strncmp(argv[1], "read", 4) == 0) ? + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strncmp (argv[1], "read", 4) == 0 || + strncmp (argv[1], "write", 5) == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong off = simple_strtoul (argv[3], NULL, 16); + ulong size = simple_strtoul (argv[4], NULL, 16); + int cmd = (strncmp (argv[1], "read", 4) == 0) ? NANDRW_READ : NANDRW_WRITE; - int ret, total; - char* cmdtail = strchr(argv[1], '.'); - - if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { - /* read out-of-band data */ - if (cmd & NANDRW_READ) { - ret = nand_read_oob(nand_dev_desc + curr_device, - off, size, (size_t *)&total, - (u_char*)addr); - } - else { - ret = nand_write_oob(nand_dev_desc + curr_device, - off, size, (size_t *)&total, - (u_char*)addr); + int ret, total; + char *cmdtail = strchr (argv[1], '.'); + + if (cmdtail && !strncmp (cmdtail, ".oob", 2)) { + /* read out-of-band data */ + if (cmd & NANDRW_READ) { + ret = nand_read_oob (nand_dev_desc + curr_device, + off, size, (size_t *) & total, + (u_char *) addr); + } else { + ret = nand_write_oob (nand_dev_desc + curr_device, + off, size, (size_t *) & total, + (u_char *) addr); + } + return ret; + } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ + else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ } - return ret; - } - else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ - else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } #ifdef SXNI855T - /* need ".e" same as ".j" for compatibility with older units */ - else if (cmdtail && !strcmp(cmdtail, ".e")) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ + /* need ".e" same as ".j" for compatibility with older units */ + else if (cmdtail && !strcmp (cmdtail, ".e")) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ #endif #ifdef CFG_NAND_SKIP_BAD_DOT_I - /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ - /* ".i" for image -> read skips bad block (no 0xff) */ - else if (cmdtail && !strcmp(cmdtail, ".i")) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ + /* ".i" for image -> read skips bad block (no 0xff) */ + else if (cmdtail && !strcmp (cmdtail, ".i")) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #endif /* CFG_NAND_SKIP_BAD_DOT_I */ - else if (cmdtail) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } + else if (cmdtail) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } - printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", - (cmd & NANDRW_READ) ? "read" : "write", - curr_device, off, size); + printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", + (cmd & NANDRW_READ) ? "read" : "write", + curr_device, off, size); - ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size, - (size_t *)&total, (u_char*)addr); + ret = nand_legacy_rw (nand_dev_desc + curr_device, + cmd, off, size, + (size_t *) & total, + (u_char *) addr); - printf (" %d bytes %s: %s\n", total, - (cmd & NANDRW_READ) ? "read" : "written", - ret ? "ERROR" : "OK"); + printf (" %d bytes %s: %s\n", total, + (cmd & NANDRW_READ) ? "read" : "written", + ret ? "ERROR" : "OK"); - return ret; - } else if (strcmp(argv[1],"erase") == 0 && - (argc == 4 || strcmp("clean", argv[2]) == 0)) { - int clean = argc == 5; - ulong off = simple_strtoul(argv[2 + clean], NULL, 16); - ulong size = simple_strtoul(argv[3 + clean], NULL, 16); - int ret; + return ret; + } else if (strcmp (argv[1], "erase") == 0 && + (argc == 4 || strcmp ("clean", argv[2]) == 0)) { + int clean = argc == 5; + ulong off = + simple_strtoul (argv[2 + clean], NULL, 16); + ulong size = + simple_strtoul (argv[3 + clean], NULL, 16); + int ret; - printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", - curr_device, off, size); + printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", + curr_device, off, size); - ret = nand_legacy_erase (nand_dev_desc + curr_device, - off, size, clean); + ret = nand_legacy_erase (nand_dev_desc + curr_device, + off, size, clean); - printf("%s\n", ret ? "ERROR" : "OK"); + printf ("%s\n", ret ? "ERROR" : "OK"); - return ret; - } else { - printf ("Usage:\n%s\n", cmdtp->usage); - rcode = 1; - } + return ret; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } - return rcode; - } + return rcode; + } } U_BOOT_CMD( diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index d98831cb4..f4e5fc504 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -229,7 +229,7 @@ soft_restart(unsigned long addr) void do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr; + ulong addr; /* flush and disable I/D cache */ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index cfc42c4a8..0d93f2e1e 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -117,7 +117,7 @@ long int spd_sdram() unsigned sdram_cfg; unsigned int ddrc_ecc_enable; - /* Read SPD parameters with I2C */ + /* Read SPD parameters with I2C */ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); @@ -147,7 +147,7 @@ long int spd_sdram() spd.ncol_addr); return 0; } - /* Setup DDR chip select register */ + /* Setup DDR chip select register */ #ifdef CFG_83XX_DDR_USES_CS0 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[0] = ( 1 << 31 @@ -218,13 +218,13 @@ long int spd_sdram() * CAS Lat DDR I Ctrl * Clocks SPD Bit Value * -------+--------+--------- - * 1.0 0 001 - * 1.5 1 010 - * 2.0 2 011 - * 2.5 3 100 - * 3.0 4 101 - * 3.5 5 110 - * 4.0 6 111 + * 1.0 0 001 + * 1.5 1 010 + * 2.0 2 011 + * 2.5 3 100 + * 3.0 4 101 + * 3.5 5 110 + * 4.0 6 111 */ caslat = __ilog2(spd.cas_lat); @@ -442,7 +442,7 @@ long int spd_sdram() /* SS_EN = 0, source synchronous disable * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd - */ + */ ddr->sdram_clk_cntl = 0x00000000; debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds index 2bb4dad8b..c87469f43 100644 --- a/doc/README.mpc8360emds +++ b/doc/README.mpc8360emds @@ -103,7 +103,7 @@ Freescale MPC8360EMDS Board Or via tftp: - tftp 10000 u-boot.bin + tftp 10000 u-boot.bin 5.1 Reflash U-boot Image using U-boot diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 013aa543d..c5477e0d7 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -46,7 +46,7 @@ u32 ucc_fast_get_qe_cr_subblock(int ucc_num) case 6: return QE_CR_SUBBLOCK_UCCFAST7; case 7: return QE_CR_SUBBLOCK_UCCFAST8; default: return QE_CR_SUBBLOCK_INVALID; - } + } } static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index fedf6361c..76fd38896 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -4,11 +4,11 @@ * Author: Shlomi Gridish * * Description: UCC GETH Driver -- PHY handling - * Driver for UEC on QE - * Based on 8260_io/fcc_enet.c + * Driver for UEC on QE + * Based on 8260_io/fcc_enet.c * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -30,16 +30,16 @@ #define UEC_VERBOSE_DEBUG #define ugphy_printk(format, arg...) \ - printf(format "\n", ## arg) + printf(format "\n", ## arg) -#define ugphy_dbg(format, arg...) \ - ugphy_printk(format , ## arg) -#define ugphy_err(format, arg...) \ - ugphy_printk(format , ## arg) -#define ugphy_info(format, arg...) \ - ugphy_printk(format , ## arg) -#define ugphy_warn(format, arg...) \ - ugphy_printk(format , ## arg) +#define ugphy_dbg(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_err(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_info(format, arg...) \ + ugphy_printk(format , ## arg) +#define ugphy_warn(format, arg...) \ + ugphy_printk(format , ## arg) #ifdef UEC_VERBOSE_DEBUG #define ugphy_vdbg ugphy_dbg @@ -47,558 +47,561 @@ #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) #endif /* UEC_VERBOSE_DEBUG */ -static void config_genmii_advert(struct uec_mii_info *mii_info); -static void genmii_setup_forced(struct uec_mii_info *mii_info); -static void genmii_restart_aneg(struct uec_mii_info *mii_info); -static int gbit_config_aneg(struct uec_mii_info *mii_info); -static int genmii_config_aneg(struct uec_mii_info *mii_info); -static int genmii_update_link(struct uec_mii_info *mii_info); -static int genmii_read_status(struct uec_mii_info *mii_info); -u16 phy_read(struct uec_mii_info *mii_info, u16 regnum); -void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val); +static void config_genmii_advert (struct uec_mii_info *mii_info); +static void genmii_setup_forced (struct uec_mii_info *mii_info); +static void genmii_restart_aneg (struct uec_mii_info *mii_info); +static int gbit_config_aneg (struct uec_mii_info *mii_info); +static int genmii_config_aneg (struct uec_mii_info *mii_info); +static int genmii_update_link (struct uec_mii_info *mii_info); +static int genmii_read_status (struct uec_mii_info *mii_info); +u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); +void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); /* Write value to the PHY for this device to the register at regnum, */ /* waiting until the write is done before it returns. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value) +void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) { - uec_private_t *ugeth = (uec_private_t *)dev->priv; - uec_t *ug_regs; - enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; - u32 tmp_reg; + uec_private_t *ugeth = (uec_private_t *) dev->priv; + uec_t *ug_regs; + enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; + u32 tmp_reg; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_regs; - /* Stop the MII management read cycle */ - out_be32(&ug_regs->miimcom, 0); - /* Setting up the MII Mangement Address Register */ - tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; - out_be32(&ug_regs->miimadd, tmp_reg); + /* Stop the MII management read cycle */ + out_be32 (&ug_regs->miimcom, 0); + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; + out_be32 (&ug_regs->miimadd, tmp_reg); - /* Setting up the MII Mangement Control Register with the value */ - out_be32(&ug_regs->miimcon, (u32)value); + /* Setting up the MII Mangement Control Register with the value */ + out_be32 (&ug_regs->miimcon, (u32) value); - /* Wait till MII management write is complete */ - while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY); + /* Wait till MII management write is complete */ + while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY); - udelay(100000); + udelay (100000); } /* Reads from register regnum in the PHY for device dev, */ /* returning the value. Clears miimcom first. All PHY */ /* configuration has to be done through the TSEC1 MIIM regs */ -int read_phy_reg(struct eth_device *dev, int mii_id, int regnum) +int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) { - uec_private_t *ugeth = (uec_private_t *)dev->priv; - uec_t *ug_regs; - enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum; - u32 tmp_reg; - u16 value; + uec_private_t *ugeth = (uec_private_t *) dev->priv; + uec_t *ug_regs; + enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; + u32 tmp_reg; + u16 value; - ug_regs = ugeth->uec_regs; + ug_regs = ugeth->uec_regs; - /* Setting up the MII Mangement Address Register */ - tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ; - out_be32(&ug_regs->miimadd, tmp_reg); + /* Setting up the MII Mangement Address Register */ + tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; + out_be32 (&ug_regs->miimadd, tmp_reg); - /* Perform an MII management read cycle */ - out_be32(&ug_regs->miimcom, 0); - out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE); + /* Perform an MII management read cycle */ + out_be32 (&ug_regs->miimcom, 0); + out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); - /* Wait till MII management write is complete */ - while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY)); + /* Wait till MII management write is complete */ + while ((in_be32 (&ug_regs->miimind)) & + (MIIMIND_NOT_VALID | MIIMIND_BUSY)); - udelay(100000); + udelay (100000); - /* Read MII management status */ - value = (u16)in_be32(&ug_regs->miimstat); - if(value == 0xffff) - ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x", - mii_id, mii_reg, (u32) &(ug_regs->miimcfg)); + /* Read MII management status */ + value = (u16) in_be32 (&ug_regs->miimstat); + if (value == 0xffff) + ugphy_warn + ("read wrong value : mii_id %d,mii_reg %d, base %08x", + mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); - return (value); + return (value); } -void mii_clear_phy_interrupt(struct uec_mii_info *mii_info) +void mii_clear_phy_interrupt (struct uec_mii_info *mii_info) { - if(mii_info->phyinfo->ack_interrupt) - mii_info->phyinfo->ack_interrupt(mii_info); + if (mii_info->phyinfo->ack_interrupt) + mii_info->phyinfo->ack_interrupt (mii_info); } -void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts) +void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, + u32 interrupts) { - mii_info->interrupts = interrupts; - if(mii_info->phyinfo->config_intr) - mii_info->phyinfo->config_intr(mii_info); + mii_info->interrupts = interrupts; + if (mii_info->phyinfo->config_intr) + mii_info->phyinfo->config_intr (mii_info); } /* Writes MII_ADVERTISE with the appropriate values, after * sanitizing advertise to make sure only supported features * are advertised */ -static void config_genmii_advert(struct uec_mii_info *mii_info) +static void config_genmii_advert (struct uec_mii_info *mii_info) { - u32 advertise; - u16 adv; - - /* Only allow advertising what this PHY supports */ - mii_info->advertising &= mii_info->phyinfo->features; - advertise = mii_info->advertising; - - /* Setup standard advertisement */ - adv = phy_read(mii_info, PHY_ANAR); - adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); - if (advertise & ADVERTISED_10baseT_Half) - adv |= ADVERTISE_10HALF; - if (advertise & ADVERTISED_10baseT_Full) - adv |= ADVERTISE_10FULL; - if (advertise & ADVERTISED_100baseT_Half) - adv |= ADVERTISE_100HALF; - if (advertise & ADVERTISED_100baseT_Full) - adv |= ADVERTISE_100FULL; - phy_write(mii_info, PHY_ANAR, adv); + u32 advertise; + u16 adv; + + /* Only allow advertising what this PHY supports */ + mii_info->advertising &= mii_info->phyinfo->features; + advertise = mii_info->advertising; + + /* Setup standard advertisement */ + adv = phy_read (mii_info, PHY_ANAR); + adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); + if (advertise & ADVERTISED_10baseT_Half) + adv |= ADVERTISE_10HALF; + if (advertise & ADVERTISED_10baseT_Full) + adv |= ADVERTISE_10FULL; + if (advertise & ADVERTISED_100baseT_Half) + adv |= ADVERTISE_100HALF; + if (advertise & ADVERTISED_100baseT_Full) + adv |= ADVERTISE_100FULL; + phy_write (mii_info, PHY_ANAR, adv); } -static void genmii_setup_forced(struct uec_mii_info *mii_info) +static void genmii_setup_forced (struct uec_mii_info *mii_info) { - u16 ctrl; - u32 features = mii_info->phyinfo->features; - - ctrl = phy_read(mii_info, PHY_BMCR); - - ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS| - PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON); - ctrl |= PHY_BMCR_RESET; - - switch(mii_info->speed) { - case SPEED_1000: - if(features & (SUPPORTED_1000baseT_Half - | SUPPORTED_1000baseT_Full)) { - ctrl |= PHY_BMCR_1000_MBPS; - break; - } - mii_info->speed = SPEED_100; - case SPEED_100: - if (features & (SUPPORTED_100baseT_Half - | SUPPORTED_100baseT_Full)) { - ctrl |= PHY_BMCR_100_MBPS; - break; - } - mii_info->speed = SPEED_10; - case SPEED_10: - if (features & (SUPPORTED_10baseT_Half - | SUPPORTED_10baseT_Full)) - break; - default: /* Unsupported speed! */ - ugphy_err("%s: Bad speed!", mii_info->dev->name); - break; - } - - phy_write(mii_info, PHY_BMCR, ctrl); + u16 ctrl; + u32 features = mii_info->phyinfo->features; + + ctrl = phy_read (mii_info, PHY_BMCR); + + ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | + PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); + ctrl |= PHY_BMCR_RESET; + + switch (mii_info->speed) { + case SPEED_1000: + if (features & (SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full)) { + ctrl |= PHY_BMCR_1000_MBPS; + break; + } + mii_info->speed = SPEED_100; + case SPEED_100: + if (features & (SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full)) { + ctrl |= PHY_BMCR_100_MBPS; + break; + } + mii_info->speed = SPEED_10; + case SPEED_10: + if (features & (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full)) + break; + default: /* Unsupported speed! */ + ugphy_err ("%s: Bad speed!", mii_info->dev->name); + break; + } + + phy_write (mii_info, PHY_BMCR, ctrl); } /* Enable and Restart Autonegotiation */ -static void genmii_restart_aneg(struct uec_mii_info *mii_info) +static void genmii_restart_aneg (struct uec_mii_info *mii_info) { - u16 ctl; + u16 ctl; - ctl = phy_read(mii_info, PHY_BMCR); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - phy_write(mii_info, PHY_BMCR, ctl); + ctl = phy_read (mii_info, PHY_BMCR); + ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + phy_write (mii_info, PHY_BMCR, ctl); } -static int gbit_config_aneg(struct uec_mii_info *mii_info) +static int gbit_config_aneg (struct uec_mii_info *mii_info) { - u16 adv; - u32 advertise; - - if(mii_info->autoneg) { - /* Configure the ADVERTISE register */ - config_genmii_advert(mii_info); - advertise = mii_info->advertising; - - adv = phy_read(mii_info, MII_1000BASETCONTROL); - adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | - MII_1000BASETCONTROL_HALFDUPLEXCAP); - if (advertise & SUPPORTED_1000baseT_Half) - adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; - if (advertise & SUPPORTED_1000baseT_Full) - adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; - phy_write(mii_info, MII_1000BASETCONTROL, adv); - - /* Start/Restart aneg */ - genmii_restart_aneg(mii_info); - } else - genmii_setup_forced(mii_info); - - return 0; + u16 adv; + u32 advertise; + + if (mii_info->autoneg) { + /* Configure the ADVERTISE register */ + config_genmii_advert (mii_info); + advertise = mii_info->advertising; + + adv = phy_read (mii_info, MII_1000BASETCONTROL); + adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | + MII_1000BASETCONTROL_HALFDUPLEXCAP); + if (advertise & SUPPORTED_1000baseT_Half) + adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; + if (advertise & SUPPORTED_1000baseT_Full) + adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; + phy_write (mii_info, MII_1000BASETCONTROL, adv); + + /* Start/Restart aneg */ + genmii_restart_aneg (mii_info); + } else + genmii_setup_forced (mii_info); + + return 0; } -static int marvell_config_aneg(struct uec_mii_info *mii_info) +static int marvell_config_aneg (struct uec_mii_info *mii_info) { - /* The Marvell PHY has an errata which requires - * that certain registers get written in order - * to restart autonegotiation */ - phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + /* The Marvell PHY has an errata which requires + * that certain registers get written in order + * to restart autonegotiation */ + phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); - phy_write(mii_info, 0x1d, 0x1f); - phy_write(mii_info, 0x1e, 0x200c); - phy_write(mii_info, 0x1d, 0x5); - phy_write(mii_info, 0x1e, 0); - phy_write(mii_info, 0x1e, 0x100); + phy_write (mii_info, 0x1d, 0x1f); + phy_write (mii_info, 0x1e, 0x200c); + phy_write (mii_info, 0x1d, 0x5); + phy_write (mii_info, 0x1e, 0); + phy_write (mii_info, 0x1e, 0x100); - gbit_config_aneg(mii_info); + gbit_config_aneg (mii_info); - return 0; + return 0; } -static int genmii_config_aneg(struct uec_mii_info *mii_info) +static int genmii_config_aneg (struct uec_mii_info *mii_info) { - if (mii_info->autoneg) { - config_genmii_advert(mii_info); - genmii_restart_aneg(mii_info); - } else - genmii_setup_forced(mii_info); + if (mii_info->autoneg) { + config_genmii_advert (mii_info); + genmii_restart_aneg (mii_info); + } else + genmii_setup_forced (mii_info); - return 0; + return 0; } -static int genmii_update_link(struct uec_mii_info *mii_info) +static int genmii_update_link (struct uec_mii_info *mii_info) { - u16 status; + u16 status; - /* Do a fake read */ - phy_read(mii_info, PHY_BMSR); + /* Do a fake read */ + phy_read (mii_info, PHY_BMSR); - /* Read link and autonegotiation status */ - status = phy_read(mii_info, PHY_BMSR); - if ((status & PHY_BMSR_LS) == 0) - mii_info->link = 0; - else - mii_info->link = 1; + /* Read link and autonegotiation status */ + status = phy_read (mii_info, PHY_BMSR); + if ((status & PHY_BMSR_LS) == 0) + mii_info->link = 0; + else + mii_info->link = 1; - /* If we are autonegotiating, and not done, - * return an error */ - if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) - return -EAGAIN; + /* If we are autonegotiating, and not done, + * return an error */ + if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) + return -EAGAIN; - return 0; + return 0; } -static int genmii_read_status(struct uec_mii_info *mii_info) +static int genmii_read_status (struct uec_mii_info *mii_info) { - u16 status; - int err; - - /* Update the link, but return if there - * was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - - if (mii_info->autoneg) { - status = phy_read(mii_info, PHY_ANLPAR); - - if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; - mii_info->pause = 0; - } - /* On non-aneg, we assume what we put in BMCR is the speed, - * though magic-aneg shouldn't prevent this case from occurring - */ - - return 0; + u16 status; + int err; + + /* Update the link, but return if there + * was an error */ + err = genmii_update_link (mii_info); + if (err) + return err; + + if (mii_info->autoneg) { + status = phy_read (mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + mii_info->pause = 0; + } + /* On non-aneg, we assume what we put in BMCR is the speed, + * though magic-aneg shouldn't prevent this case from occurring + */ + + return 0; } -static int marvell_read_status(struct uec_mii_info *mii_info) +static int marvell_read_status (struct uec_mii_info *mii_info) { - u16 status; - int err; - - /* Update the link, but return if there - * was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - - /* If the link is up, read the speed and duplex */ - /* If we aren't autonegotiating, assume speeds - * are as set */ - if (mii_info->autoneg && mii_info->link) { - int speed; - status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); - - /* Get the duplexity */ - if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - - /* Get the speed */ - speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; - switch(speed) { - case MII_M1011_PHY_SPEC_STATUS_1000: - mii_info->speed = SPEED_1000; - break; - case MII_M1011_PHY_SPEC_STATUS_100: - mii_info->speed = SPEED_100; - break; - default: - mii_info->speed = SPEED_10; - break; - } - mii_info->pause = 0; - } - - return 0; + u16 status; + int err; + + /* Update the link, but return if there + * was an error */ + err = genmii_update_link (mii_info); + if (err) + return err; + + /* If the link is up, read the speed and duplex */ + /* If we aren't autonegotiating, assume speeds + * are as set */ + if (mii_info->autoneg && mii_info->link) { + int speed; + + status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS); + + /* Get the duplexity */ + if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + + /* Get the speed */ + speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; + switch (speed) { + case MII_M1011_PHY_SPEC_STATUS_1000: + mii_info->speed = SPEED_1000; + break; + case MII_M1011_PHY_SPEC_STATUS_100: + mii_info->speed = SPEED_100; + break; + default: + mii_info->speed = SPEED_10; + break; + } + mii_info->pause = 0; + } + + return 0; } -static int marvell_ack_interrupt(struct uec_mii_info *mii_info) +static int marvell_ack_interrupt (struct uec_mii_info *mii_info) { - /* Clear the interrupts by reading the reg */ - phy_read(mii_info, MII_M1011_IEVENT); + /* Clear the interrupts by reading the reg */ + phy_read (mii_info, MII_M1011_IEVENT); - return 0; + return 0; } -static int marvell_config_intr(struct uec_mii_info *mii_info) +static int marvell_config_intr (struct uec_mii_info *mii_info) { - if(mii_info->interrupts == MII_INTERRUPT_ENABLED) - phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); - else - phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); + if (mii_info->interrupts == MII_INTERRUPT_ENABLED) + phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); + else + phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); - return 0; + return 0; } -static int dm9161_init(struct uec_mii_info *mii_info) +static int dm9161_init (struct uec_mii_info *mii_info) { - /* Reset the PHY */ - phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) | - PHY_BMCR_RESET); - /* PHY and MAC connect*/ - phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) & - ~PHY_BMCR_ISO); + /* Reset the PHY */ + phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | + PHY_BMCR_RESET); + /* PHY and MAC connect */ + phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & + ~PHY_BMCR_ISO); #ifdef CONFIG_RMII_MODE - phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); + phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); #else - phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); + phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); #endif - config_genmii_advert(mii_info); - /* Start/restart aneg */ - genmii_config_aneg(mii_info); - /* Delay to wait the aneg compeleted */ - udelay(3000000); + config_genmii_advert (mii_info); + /* Start/restart aneg */ + genmii_config_aneg (mii_info); + /* Delay to wait the aneg compeleted */ + udelay (3000000); - return 0; + return 0; } -static int dm9161_config_aneg(struct uec_mii_info *mii_info) +static int dm9161_config_aneg (struct uec_mii_info *mii_info) { - return 0; + return 0; } -static int dm9161_read_status(struct uec_mii_info *mii_info) +static int dm9161_read_status (struct uec_mii_info *mii_info) { - u16 status; - int err; - - /* Update the link, but return if there was an error*/ - err = genmii_update_link(mii_info); - if (err) - return err; - /* If the link is up, read the speed and duplex - If we aren't autonegotiating assume speeds are as set */ - if (mii_info->autoneg && mii_info->link) { - status = phy_read(mii_info, MII_DM9161_SCSR); - if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; - - if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - } - - return 0; + u16 status; + int err; + + /* Update the link, but return if there was an error */ + err = genmii_update_link (mii_info); + if (err) + return err; + /* If the link is up, read the speed and duplex + If we aren't autonegotiating assume speeds are as set */ + if (mii_info->autoneg && mii_info->link) { + status = phy_read (mii_info, MII_DM9161_SCSR); + if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + + if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } + + return 0; } -static int dm9161_ack_interrupt(struct uec_mii_info *mii_info) +static int dm9161_ack_interrupt (struct uec_mii_info *mii_info) { - /* Clear the interrupt by reading the reg */ - phy_read(mii_info, MII_DM9161_INTR); + /* Clear the interrupt by reading the reg */ + phy_read (mii_info, MII_DM9161_INTR); - return 0; + return 0; } -static int dm9161_config_intr(struct uec_mii_info *mii_info) +static int dm9161_config_intr (struct uec_mii_info *mii_info) { - if (mii_info->interrupts == MII_INTERRUPT_ENABLED) - phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); - else - phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); + if (mii_info->interrupts == MII_INTERRUPT_ENABLED) + phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); + else + phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); - return 0; + return 0; } -static void dm9161_close(struct uec_mii_info *mii_info) +static void dm9161_close (struct uec_mii_info *mii_info) { } static struct phy_info phy_info_dm9161 = { - .phy_id = 0x0181b880, - .phy_id_mask = 0x0ffffff0, - .name = "Davicom DM9161E", - .init = dm9161_init, - .config_aneg = dm9161_config_aneg, - .read_status = dm9161_read_status, - .close = dm9161_close, + .phy_id = 0x0181b880, + .phy_id_mask = 0x0ffffff0, + .name = "Davicom DM9161E", + .init = dm9161_init, + .config_aneg = dm9161_config_aneg, + .read_status = dm9161_read_status, + .close = dm9161_close, }; static struct phy_info phy_info_dm9161a = { - .phy_id = 0x0181b8a0, - .phy_id_mask = 0x0ffffff0, - .name = "Davicom DM9161A", - .features = MII_BASIC_FEATURES, - .init = dm9161_init, - .config_aneg = dm9161_config_aneg, - .read_status = dm9161_read_status, - .ack_interrupt = dm9161_ack_interrupt, - .config_intr = dm9161_config_intr, - .close = dm9161_close, + .phy_id = 0x0181b8a0, + .phy_id_mask = 0x0ffffff0, + .name = "Davicom DM9161A", + .features = MII_BASIC_FEATURES, + .init = dm9161_init, + .config_aneg = dm9161_config_aneg, + .read_status = dm9161_read_status, + .ack_interrupt = dm9161_ack_interrupt, + .config_intr = dm9161_config_intr, + .close = dm9161_close, }; static struct phy_info phy_info_marvell = { - .phy_id = 0x01410c00, - .phy_id_mask = 0xffffff00, - .name = "Marvell 88E11x1", - .features = MII_GBIT_FEATURES, - .config_aneg = &marvell_config_aneg, - .read_status = &marvell_read_status, - .ack_interrupt = &marvell_ack_interrupt, - .config_intr = &marvell_config_intr, + .phy_id = 0x01410c00, + .phy_id_mask = 0xffffff00, + .name = "Marvell 88E11x1", + .features = MII_GBIT_FEATURES, + .config_aneg = &marvell_config_aneg, + .read_status = &marvell_read_status, + .ack_interrupt = &marvell_ack_interrupt, + .config_intr = &marvell_config_intr, }; -static struct phy_info phy_info_genmii= { - .phy_id = 0x00000000, - .phy_id_mask = 0x00000000, - .name = "Generic MII", - .features = MII_BASIC_FEATURES, - .config_aneg = genmii_config_aneg, - .read_status = genmii_read_status, +static struct phy_info phy_info_genmii = { + .phy_id = 0x00000000, + .phy_id_mask = 0x00000000, + .name = "Generic MII", + .features = MII_BASIC_FEATURES, + .config_aneg = genmii_config_aneg, + .read_status = genmii_read_status, }; static struct phy_info *phy_info[] = { - &phy_info_dm9161, - &phy_info_dm9161a, - &phy_info_marvell, - &phy_info_genmii, - NULL + &phy_info_dm9161, + &phy_info_dm9161a, + &phy_info_marvell, + &phy_info_genmii, + NULL }; -u16 phy_read(struct uec_mii_info *mii_info, u16 regnum) +u16 phy_read (struct uec_mii_info *mii_info, u16 regnum) { - return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); + return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum); } -void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val) +void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) { - mii_info->mdio_write(mii_info->dev, - mii_info->mii_id, - regnum, val); + mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val); } /* Use the PHY ID registers to determine what type of PHY is attached * to device dev. return a struct phy_info structure describing that PHY */ -struct phy_info * get_phy_info(struct uec_mii_info *mii_info) +struct phy_info *get_phy_info (struct uec_mii_info *mii_info) { - u16 phy_reg; - u32 phy_ID; - int i; - struct phy_info *theInfo = NULL; - - /* Grab the bits from PHYIR1, and put them in the upper half */ - phy_reg = phy_read(mii_info, PHY_PHYIDR1); - phy_ID = (phy_reg & 0xffff) << 16; - - /* Grab the bits from PHYIR2, and put them in the lower half */ - phy_reg = phy_read(mii_info, PHY_PHYIDR2); - phy_ID |= (phy_reg & 0xffff); - - /* loop through all the known PHY types, and find one that */ - /* matches the ID we read from the PHY. */ - for (i = 0; phy_info[i]; i++) - if (phy_info[i]->phy_id == - (phy_ID & phy_info[i]->phy_id_mask)) { - theInfo = phy_info[i]; - break; - } - - /* This shouldn't happen, as we have generic PHY support */ - if (theInfo == NULL) { - ugphy_info("UEC: PHY id %x is not supported!", phy_ID); - return NULL; - } else { - ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID); - } - - return theInfo; + u16 phy_reg; + u32 phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = phy_read (mii_info, PHY_PHYIDR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = phy_read (mii_info, PHY_PHYIDR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for (i = 0; phy_info[i]; i++) + if (phy_info[i]->phy_id == + (phy_ID & phy_info[i]->phy_id_mask)) { + theInfo = phy_info[i]; + break; + } + + /* This shouldn't happen, as we have generic PHY support */ + if (theInfo == NULL) { + ugphy_info ("UEC: PHY id %x is not supported!", phy_ID); + return NULL; + } else { + ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID); + } + + return theInfo; } -void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) +void marvell_phy_interface_mode (struct eth_device *dev, + enet_interface_e mode) { - uec_private_t *uec = (uec_private_t *)dev->priv; - struct uec_mii_info *mii_info; + uec_private_t *uec = (uec_private_t *) dev->priv; + struct uec_mii_info *mii_info; if (!uec->mii_info) { - printf("%s: the PHY not intialized\n", __FUNCTION__); + printf ("%s: the PHY not intialized\n", __FUNCTION__); return; } mii_info = uec->mii_info; if (mode == ENET_100_RGMII) { - phy_write(mii_info, 0x00, 0x9140); - phy_write(mii_info, 0x1d, 0x001f); - phy_write(mii_info, 0x1e, 0x200c); - phy_write(mii_info, 0x1d, 0x0005); - phy_write(mii_info, 0x1e, 0x0000); - phy_write(mii_info, 0x1e, 0x0100); - phy_write(mii_info, 0x09, 0x0e00); - phy_write(mii_info, 0x04, 0x01e1); - phy_write(mii_info, 0x00, 0x9140); - phy_write(mii_info, 0x00, 0x1000); - udelay(100000); - phy_write(mii_info, 0x00, 0x2900); - phy_write(mii_info, 0x14, 0x0cd2); - phy_write(mii_info, 0x00, 0xa100); - phy_write(mii_info, 0x09, 0x0000); - phy_write(mii_info, 0x1b, 0x800b); - phy_write(mii_info, 0x04, 0x05e1); - phy_write(mii_info, 0x00, 0xa100); - phy_write(mii_info, 0x00, 0x2100); - udelay(1000000); + phy_write (mii_info, 0x00, 0x9140); + phy_write (mii_info, 0x1d, 0x001f); + phy_write (mii_info, 0x1e, 0x200c); + phy_write (mii_info, 0x1d, 0x0005); + phy_write (mii_info, 0x1e, 0x0000); + phy_write (mii_info, 0x1e, 0x0100); + phy_write (mii_info, 0x09, 0x0e00); + phy_write (mii_info, 0x04, 0x01e1); + phy_write (mii_info, 0x00, 0x9140); + phy_write (mii_info, 0x00, 0x1000); + udelay (100000); + phy_write (mii_info, 0x00, 0x2900); + phy_write (mii_info, 0x14, 0x0cd2); + phy_write (mii_info, 0x00, 0xa100); + phy_write (mii_info, 0x09, 0x0000); + phy_write (mii_info, 0x1b, 0x800b); + phy_write (mii_info, 0x04, 0x05e1); + phy_write (mii_info, 0x00, 0xa100); + phy_write (mii_info, 0x00, 0x2100); + udelay (1000000); } else if (mode == ENET_10_RGMII) { - phy_write(mii_info, 0x14, 0x8e40); - phy_write(mii_info, 0x1b, 0x800b); - phy_write(mii_info, 0x14, 0x0c82); - phy_write(mii_info, 0x00, 0x8100); - udelay(1000000); + phy_write (mii_info, 0x14, 0x8e40); + phy_write (mii_info, 0x1b, 0x800b); + phy_write (mii_info, 0x14, 0x0c82); + phy_write (mii_info, 0x00, 0x8100); + udelay (1000000); } } -void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode) +void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode) { #ifdef CONFIG_PHY_MODE_NEED_CHANGE - marvell_phy_interface_mode(dev, mode); + marvell_phy_interface_mode (dev, mode); #endif } #endif /* CONFIG_QE */ diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index a82f1f589..9bd926ddd 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -4,11 +4,11 @@ * Author: Shlomi Gridish <gridish@freescale.com> * * Description: UCC ethernet driver -- PHY handling - * Driver for UEC on QE - * Based on 8260_io/fcc_enet.c + * Driver for UEC on QE + * Based on 8260_io/fcc_enet.c * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * @@ -19,37 +19,37 @@ #define MII_end ((u32)-2) #define MII_read ((u32)-1) -#define MIIMIND_BUSY 0x00000001 -#define MIIMIND_NOTVALID 0x00000004 +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 -#define UGETH_AN_TIMEOUT 2000 +#define UGETH_AN_TIMEOUT 2000 /* 1000BT control (Marvell & BCM54xx at least) */ -#define MII_1000BASETCONTROL 0x09 +#define MII_1000BASETCONTROL 0x09 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 /* Cicada Extended Control Register 1 */ -#define MII_CIS8201_EXT_CON1 0x17 +#define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000 /* Cicada Interrupt Mask Register */ -#define MII_CIS8201_IMASK 0x19 -#define MII_CIS8201_IMASK_IEN 0x8000 -#define MII_CIS8201_IMASK_SPEED 0x4000 -#define MII_CIS8201_IMASK_LINK 0x2000 +#define MII_CIS8201_IMASK 0x19 +#define MII_CIS8201_IMASK_IEN 0x8000 +#define MII_CIS8201_IMASK_SPEED 0x4000 +#define MII_CIS8201_IMASK_LINK 0x2000 #define MII_CIS8201_IMASK_DUPLEX 0x1000 -#define MII_CIS8201_IMASK_MASK 0xf000 +#define MII_CIS8201_IMASK_MASK 0xf000 /* Cicada Interrupt Status Register */ -#define MII_CIS8201_ISTAT 0x1a +#define MII_CIS8201_ISTAT 0x1a #define MII_CIS8201_ISTAT_STATUS 0x8000 -#define MII_CIS8201_ISTAT_SPEED 0x4000 -#define MII_CIS8201_ISTAT_LINK 0x2000 +#define MII_CIS8201_ISTAT_SPEED 0x4000 +#define MII_CIS8201_ISTAT_LINK 0x2000 #define MII_CIS8201_ISTAT_DUPLEX 0x1000 /* Cicada Auxiliary Control/Status Register */ -#define MII_CIS8201_AUX_CONSTAT 0x1c +#define MII_CIS8201_AUX_CONSTAT 0x1c #define MII_CIS8201_AUXCONSTAT_INIT 0x0004 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 @@ -57,155 +57,156 @@ #define MII_CIS8201_AUXCONSTAT_100 0x0008 /* 88E1011 PHY Status Register */ -#define MII_M1011_PHY_SPEC_STATUS 0x11 -#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 -#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 -#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 -#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 -#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 -#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 - -#define MII_M1011_IEVENT 0x13 -#define MII_M1011_IEVENT_CLEAR 0x0000 - -#define MII_M1011_IMASK 0x12 -#define MII_M1011_IMASK_INIT 0x6400 -#define MII_M1011_IMASK_CLEAR 0x0000 - -#define MII_DM9161_SCR 0x10 -#define MII_DM9161_SCR_INIT 0x0610 +#define MII_M1011_PHY_SPEC_STATUS 0x11 +#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 +#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 +#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 +#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 +#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 +#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 + +#define MII_M1011_IEVENT 0x13 +#define MII_M1011_IEVENT_CLEAR 0x0000 + +#define MII_M1011_IMASK 0x12 +#define MII_M1011_IMASK_INIT 0x6400 +#define MII_M1011_IMASK_CLEAR 0x0000 + +#define MII_DM9161_SCR 0x10 +#define MII_DM9161_SCR_INIT 0x0610 #define MII_DM9161_SCR_RMII_INIT 0x0710 /* DM9161 Specified Configuration and Status Register */ -#define MII_DM9161_SCSR 0x11 -#define MII_DM9161_SCSR_100F 0x8000 -#define MII_DM9161_SCSR_100H 0x4000 -#define MII_DM9161_SCSR_10F 0x2000 -#define MII_DM9161_SCSR_10H 0x1000 +#define MII_DM9161_SCSR 0x11 +#define MII_DM9161_SCSR_100F 0x8000 +#define MII_DM9161_SCSR_100H 0x4000 +#define MII_DM9161_SCSR_10F 0x2000 +#define MII_DM9161_SCSR_10H 0x1000 /* DM9161 Interrupt Register */ -#define MII_DM9161_INTR 0x15 -#define MII_DM9161_INTR_PEND 0x8000 -#define MII_DM9161_INTR_DPLX_MASK 0x0800 -#define MII_DM9161_INTR_SPD_MASK 0x0400 -#define MII_DM9161_INTR_LINK_MASK 0x0200 -#define MII_DM9161_INTR_MASK 0x0100 -#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 -#define MII_DM9161_INTR_SPD_CHANGE 0x0008 -#define MII_DM9161_INTR_LINK_CHANGE 0x0004 -#define MII_DM9161_INTR_INIT 0x0000 -#define MII_DM9161_INTR_STOP \ +#define MII_DM9161_INTR 0x15 +#define MII_DM9161_INTR_PEND 0x8000 +#define MII_DM9161_INTR_DPLX_MASK 0x0800 +#define MII_DM9161_INTR_SPD_MASK 0x0400 +#define MII_DM9161_INTR_LINK_MASK 0x0200 +#define MII_DM9161_INTR_MASK 0x0100 +#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 +#define MII_DM9161_INTR_SPD_CHANGE 0x0008 +#define MII_DM9161_INTR_LINK_CHANGE 0x0004 +#define MII_DM9161_INTR_INIT 0x0000 +#define MII_DM9161_INTR_STOP \ (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) /* DM9161 10BT Configuration/Status */ -#define MII_DM9161_10BTCSR 0x12 -#define MII_DM9161_10BTCSR_INIT 0x7800 +#define MII_DM9161_10BTCSR 0x12 +#define MII_DM9161_10BTCSR_INIT 0x7800 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ - SUPPORTED_10baseT_Full | \ - SUPPORTED_100baseT_Half | \ - SUPPORTED_100baseT_Full | \ - SUPPORTED_Autoneg | \ - SUPPORTED_TP | \ - SUPPORTED_MII) + SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full | \ + SUPPORTED_Autoneg | \ + SUPPORTED_TP | \ + SUPPORTED_MII) #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ - SUPPORTED_1000baseT_Half | \ - SUPPORTED_1000baseT_Full) + SUPPORTED_1000baseT_Half | \ + SUPPORTED_1000baseT_Full) -#define MII_READ_COMMAND 0x00000001 +#define MII_READ_COMMAND 0x00000001 -#define MII_INTERRUPT_DISABLED 0x0 -#define MII_INTERRUPT_ENABLED 0x1 +#define MII_INTERRUPT_DISABLED 0x0 +#define MII_INTERRUPT_ENABLED 0x1 #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 /* Indicates what features are supported by the interface. */ -#define SUPPORTED_10baseT_Half (1 << 0) -#define SUPPORTED_10baseT_Full (1 << 1) -#define SUPPORTED_100baseT_Half (1 << 2) -#define SUPPORTED_100baseT_Full (1 << 3) -#define SUPPORTED_1000baseT_Half (1 << 4) -#define SUPPORTED_1000baseT_Full (1 << 5) -#define SUPPORTED_Autoneg (1 << 6) -#define SUPPORTED_TP (1 << 7) -#define SUPPORTED_AUI (1 << 8) -#define SUPPORTED_MII (1 << 9) -#define SUPPORTED_FIBRE (1 << 10) -#define SUPPORTED_BNC (1 << 11) -#define SUPPORTED_10000baseT_Full (1 << 12) - -#define ADVERTISED_10baseT_Half (1 << 0) -#define ADVERTISED_10baseT_Full (1 << 1) -#define ADVERTISED_100baseT_Half (1 << 2) -#define ADVERTISED_100baseT_Full (1 << 3) -#define ADVERTISED_1000baseT_Half (1 << 4) -#define ADVERTISED_1000baseT_Full (1 << 5) -#define ADVERTISED_Autoneg (1 << 6) -#define ADVERTISED_TP (1 << 7) -#define ADVERTISED_AUI (1 << 8) -#define ADVERTISED_MII (1 << 9) -#define ADVERTISED_FIBRE (1 << 10) -#define ADVERTISED_BNC (1 << 11) -#define ADVERTISED_10000baseT_Full (1 << 12) +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) + +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) /* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) + ADVERTISE_100HALF | ADVERTISE_100FULL) /* Taken from mii_if_info and sungem_phy.h */ struct uec_mii_info { - /* Information about the PHY type */ - /* And management functions */ - struct phy_info *phyinfo; + /* Information about the PHY type */ + /* And management functions */ + struct phy_info *phyinfo; - struct eth_device *dev; + struct eth_device *dev; - /* forced speed & duplex (no autoneg) - * partner speed & duplex & pause (autoneg) - */ - int speed; - int duplex; - int pause; + /* forced speed & duplex (no autoneg) + * partner speed & duplex & pause (autoneg) + */ + int speed; + int duplex; + int pause; - /* The most recently read link state */ - int link; + /* The most recently read link state */ + int link; - /* Enabled Interrupts */ - u32 interrupts; + /* Enabled Interrupts */ + u32 interrupts; - u32 advertising; - int autoneg; - int mii_id; + u32 advertising; + int autoneg; + int mii_id; - /* private data pointer */ - /* For use by PHYs to maintain extra state */ - void *priv; + /* private data pointer */ + /* For use by PHYs to maintain extra state */ + void *priv; - /* Provided by ethernet driver */ - int (*mdio_read) (struct eth_device *dev, int mii_id, int reg); - void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val); + /* Provided by ethernet driver */ + int (*mdio_read) (struct eth_device * dev, int mii_id, int reg); + void (*mdio_write) (struct eth_device * dev, int mii_id, int reg, + int val); }; /* struct phy_info: a structure which defines attributes for a PHY @@ -221,36 +222,38 @@ struct uec_mii_info { * Each PHY must declare config_aneg, and read_status. */ struct phy_info { - u32 phy_id; - char *name; - unsigned int phy_id_mask; - u32 features; + u32 phy_id; + char *name; + unsigned int phy_id_mask; + u32 features; - /* Called to initialize the PHY */ - int (*init)(struct uec_mii_info *mii_info); + /* Called to initialize the PHY */ + int (*init) (struct uec_mii_info * mii_info); - /* Called to suspend the PHY for power */ - int (*suspend)(struct uec_mii_info *mii_info); + /* Called to suspend the PHY for power */ + int (*suspend) (struct uec_mii_info * mii_info); - /* Reconfigures autonegotiation (or disables it) */ - int (*config_aneg)(struct uec_mii_info *mii_info); + /* Reconfigures autonegotiation (or disables it) */ + int (*config_aneg) (struct uec_mii_info * mii_info); - /* Determines the negotiated speed and duplex */ - int (*read_status)(struct uec_mii_info *mii_info); + /* Determines the negotiated speed and duplex */ + int (*read_status) (struct uec_mii_info * mii_info); - /* Clears any pending interrupts */ - int (*ack_interrupt)(struct uec_mii_info *mii_info); + /* Clears any pending interrupts */ + int (*ack_interrupt) (struct uec_mii_info * mii_info); - /* Enables or disables interrupts */ - int (*config_intr)(struct uec_mii_info *mii_info); + /* Enables or disables interrupts */ + int (*config_intr) (struct uec_mii_info * mii_info); - /* Clears up any memory if needed */ - void (*close)(struct uec_mii_info *mii_info); + /* Clears up any memory if needed */ + void (*close) (struct uec_mii_info * mii_info); }; -struct phy_info *get_phy_info(struct uec_mii_info *mii_info); -void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value); -int read_phy_reg(struct eth_device *dev, int mii_id, int regnum); -void mii_clear_phy_interrupt(struct uec_mii_info *mii_info); -void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts); +struct phy_info *get_phy_info (struct uec_mii_info *mii_info); +void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, + int value); +int read_phy_reg (struct eth_device *dev, int mii_id, int regnum); +void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); +void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, + u32 interrupts); #endif /* __UEC_PHY_H__ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 2a76a05c6..43cde5e28 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -5,18 +5,18 @@ * * History : * 20060601: Daveliu (daveliu@freescale.com) - * TanyaJiang (tanya.jiang@freescale.com) - * Unified variable names for mpc83xx - * 2005 : Mandy Lavi (mandy.lavi@freescale.com) - * support for mpc8360e - * 2004 : Eran Liberty (liberty@freescale.com) - * Initialized for mpc8349 - * based on: - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * MPC85xx Internal Memory Map - * Copyright(c) 2002,2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) + * TanyaJiang (tanya.jiang@freescale.com) + * Unified variable names for mpc83xx + * 2005 : Mandy Lavi (mandy.lavi@freescale.com) + * support for mpc8360e + * 2004 : Eran Liberty (liberty@freescale.com) + * Initialized for mpc8349 + * based on: + * MPC8260 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * MPC85xx Internal Memory Map + * Copyright(c) 2002,2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,7 +25,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -50,7 +50,7 @@ typedef struct law83xx { * access window n. The specified base address should be aligned to the * window size, as defined by LBLAWARn[SIZE]. */ -#define LAWBAR_BAR 0xFFFFF000 +#define LAWBAR_BAR 0xFFFFF000 #define LAWBAR_RES ~(LAWBAR_BAR) u32 ar; /* LBIU local access window attribute register */ } law83xx_t; @@ -66,7 +66,7 @@ typedef struct sysconf83xx { * address used for boot sequencer configuration accesses. */ #define ALTCBAR_BASE_ADDR 0xFFF00000 -#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ +#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ u8 res1[0x14]; law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; @@ -77,8 +77,8 @@ typedef struct sysconf83xx { u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ u8 res5[0x04]; u32 spcr; /* System Priority Configuration Register */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ @@ -184,7 +184,7 @@ typedef struct sysconf83xx { #define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ #define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ #define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ - SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) + SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) #endif u8 res6[0xE4]; } sysconf83xx_t; @@ -211,9 +211,9 @@ typedef struct rtclk83xx { u32 cnr; /* control register */ #define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ #define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ -#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ -#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ -#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) +#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ +#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ +#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) u32 ldr; /* load register */ #define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be * loaded in a 32-bit RTC counter.*/ @@ -240,11 +240,11 @@ typedef struct gtm83xx { #define CFR1_PCAS 0x80 /* Pair Cascade mode */ #define CFR1_BCM 0x40 /* Backward compatible mode */ #define CFR1_STP2 0x20 /* Stop timer */ -#define CFR1_RST2 0x10 /* Reset timer */ -#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ -#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ +#define CFR1_RST2 0x10 /* Reset timer */ +#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ +#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ #define CFR1_STP1 0x02 /* Stop timer */ -#define CFR1_RST1 0x01 /* Reset timer */ +#define CFR1_RST1 0x01 /* Reset timer */ #define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ CFR1_GM1 | CFR1_STP1 | CFR1_RST1) u8 res0[3]; @@ -252,29 +252,29 @@ typedef struct gtm83xx { #define CFR2_PCAS 0x80 /* Pair Cascade mode */ #define CFR2_SCAS 0x40 /* Super Cascade mode */ #define CFR2_STP4 0x20 /* Stop timer */ -#define CFR2_RST4 0x10 /* Reset timer */ -#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ -#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ +#define CFR2_RST4 0x10 /* Reset timer */ +#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ +#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ #define CFR2_STP3 0x02 /* Stop timer */ -#define CFR2_RST3 0x01 /* Reset timer */ +#define CFR2_RST3 0x01 /* Reset timer */ u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ -#define MDR_SPS 0xff00 /* Secondary Prescaler value */ -#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ -#define MDR_OM 0x0020 /* Output mode */ -#define MDR_ORI 0x0010 /* Output reference interrupt enable */ -#define MDR_FRR 0x0008 /* Free run/restart */ + u16 mdr1; /* Timer1 Mode Register */ +#define MDR_SPS 0xff00 /* Secondary Prescaler value */ +#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ +#define MDR_OM 0x0020 /* Output mode */ +#define MDR_ORI 0x0010 /* Output reference interrupt enable */ +#define MDR_FRR 0x0008 /* Free run/restart */ #define MDR_ICLK 0x0006 /* Input clock source for the timer */ -#define MDR_GE 0x0001 /* Gate enable */ - u16 mdr2; /* Timer2 Mode Register */ +#define MDR_GE 0x0001 /* Gate enable */ + u16 mdr2; /* Timer2 Mode Register */ u16 rfr1; /* Timer1 Reference Register */ u16 rfr2; /* Timer2 Reference Register */ u16 cpr1; /* Timer1 Capture Register */ u16 cpr2; /* Timer2 Capture Register */ u16 cnr1; /* Timer1 Counter Register */ u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ u16 rfr3; /* Timer3 Reference Register */ u16 rfr4; /* Timer4 Reference Register */ u16 cpr3; /* Timer3 Capture Register */ @@ -302,7 +302,7 @@ typedef struct gtm83xx { */ typedef struct ipic83xx { u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ -#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ +#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ #define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ #define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ #define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ @@ -313,28 +313,28 @@ typedef struct ipic83xx { #define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ #define SICVR_IVEC 0x0000007f /* Interrupt vector */ #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) - u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ + u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ #if defined (CONFIG_MPC8349) -#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ -#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ -#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ -#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ -#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ -#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ -#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ -#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ +#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ +#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ +#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ +#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ +#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ +#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ +#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ +#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ #endif #if defined (CONFIG_MPC8360) #define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ #define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ #endif -#define SIIH_UART1 0x00000080 /* UART1 interrupt */ -#define SIIH_UART2 0x00000040 /* UART2 interrupt */ -#define SIIH_SEC 0x00000020 /* SEC interrupt */ -#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ -#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ +#define SIIH_UART1 0x00000080 /* UART1 interrupt */ +#define SIIH_UART2 0x00000040 /* UART2 interrupt */ +#define SIIH_SEC 0x00000020 /* SEC interrupt */ +#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ +#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ #if defined (CONFIG_MPC8349) -#define SIIH_SPI 0x00000001 /* SPI interrupt */ +#define SIIH_SPI 0x00000001 /* SPI interrupt */ #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ @@ -345,15 +345,15 @@ typedef struct ipic83xx { #define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) #endif - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ #define SIIL_PIT 0x40000000 /* PIT interrupt */ #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ #if defined (CONFIG_MPC8349) #define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ #endif -#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ -#define SIIL_MU 0x04000000 /* Message Unit interrupt */ +#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ +#define SIIL_MU 0x04000000 /* Message Unit interrupt */ #define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ #define SIIL_DMA 0x01000000 /* DMA interrupt */ #define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ @@ -363,7 +363,7 @@ typedef struct ipic83xx { #define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ #endif #if defined (CONFIG_MPC8360) -#define SIIL_QEP 0x00200000 /* QE ports interrupt */ +#define SIIL_QEP 0x00200000 /* QE ports interrupt */ #define SIIL_SDDR 0x00100000 /* SDDR interrupt */ #endif #define SIIL_DDR 0x00080000 /* DDR interrupt */ @@ -375,7 +375,7 @@ typedef struct ipic83xx { #define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ -#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ +#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ #if defined (CONFIG_MPC8349) #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ @@ -385,9 +385,9 @@ typedef struct ipic83xx { | SIIL_GTM5 |SIIL_DPTC ) #endif #if defined (CONFIG_MPC8360) -#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ +#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ - |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ + |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ |SIIL_GTM5 ) #endif @@ -423,23 +423,23 @@ typedef struct ipic83xx { | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ | SEI_SIRQ0) u32 secnr; /* System External Interrupt Control Register (SECNR) */ -#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ -#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ -#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ -#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ -#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ -#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ -#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ -#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ -#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ -#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ -#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ -#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ +#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ +#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ +#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ +#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ +#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ +#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ +#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ +#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ +#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ +#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ +#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ +#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ #define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) - u32 sersr; /* System Error Status Register (SERR) */ + u32 sersr; /* System Error Status Register (SERR) */ u32 sermr; /* System Error Mask Register (SERR) */ #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ #define SERR_WDT 0x40000000 /* WDT MCP request */ @@ -455,15 +455,15 @@ typedef struct ipic83xx { #define SERR_CMEE 0x08000000 /* CMEEMCP request */ #define SERR_PCI 0x04000000 /* PCI MCP request */ #endif -#define SERR_MU 0x01000000 /* MU MCP request */ +#define SERR_MU 0x01000000 /* MU MCP request */ #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ #if defined (CONFIG_MPC8349) #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ |SERR_RNC ) #elif defined (CONFIG_MPC8360) -#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ - |SERR_CMEE|SERR_PCI|SERR_MU) +#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ + |SERR_CMEE|SERR_PCI|SERR_MU) #endif u32 sercr; /* System Error Control Register (SERCR) */ #define SERCR_MCPR 0x00000001 /* MCP Route */ @@ -472,7 +472,7 @@ typedef struct ipic83xx { u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ u32 sefcr; /* System External Interrupt Force Register (SEI) */ - u32 serfr; /* System Error Force Register (SERR) */ + u32 serfr; /* System Error Force Register (SERR) */ u32 scvcr; /* System Critical Interrupt Vector Register */ #define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible critical interrupt vector. */ @@ -506,7 +506,7 @@ typedef struct arbiter83xx { #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) u32 atr; /* Arbiter Timers Register */ #define ATR_DTO 0x00FF0000 /* Data time out. */ -#define ATR_ATO 0x000000FF /* Address time out. */ +#define ATR_ATO 0x000000FF /* Address time out. */ #define ATR_RES ~(ATR_DTO|ATR_ATO) u8 res[4]; u32 aer; /* Arbiter Event Register (AE) */ @@ -523,9 +523,9 @@ typedef struct arbiter83xx { u32 aerr; /* Arbiter Event Response Register (AE) */ #define AE_ETEA 0x00000020 /* Transfer error. */ #define AE_RES_ 0x00000010 /* Reserved transfer type. */ -#define AE_ECW 0x00000008 /* External control word transfer type. */ -#define AE_AO 0x00000004 /* Address Only transfer type. */ -#define AE_DTO 0x00000002 /* Data time out. */ +#define AE_ECW 0x00000008 /* External control word transfer type. */ +#define AE_AO 0x00000004 /* Address Only transfer type. */ +#define AE_DTO 0x00000002 /* Data time out. */ #define AE_ATO 0x00000001 /* Address time out. */ #define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) u8 res1[0xDC]; @@ -536,21 +536,21 @@ typedef struct arbiter83xx { */ typedef struct reset83xx { u32 rcwl; /* RCWL Register */ -#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ +#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ #define RCWL_LBIUCM_SHIFT 31 -#define RCWL_DDRCM 0x40000000 /* DDRCM */ +#define RCWL_DDRCM 0x40000000 /* DDRCM */ #define RCWL_DDRCM_SHIFT 30 #if defined (CONFIG_MPC8349) -#define RCWL_SVCOD 0x30000000 /* SVCOD */ +#define RCWL_SVCOD 0x30000000 /* SVCOD */ #endif -#define RCWL_SPMF 0x0f000000 /* SPMF */ -#define RCWL_SPMF_SHIFT 24 -#define RCWL_COREPLL 0x007F0000 /* COREPLL */ +#define RCWL_SPMF 0x0f000000 /* SPMF */ +#define RCWL_SPMF_SHIFT 24 +#define RCWL_COREPLL 0x007F0000 /* COREPLL */ #define RCWL_COREPLL_SHIFT 16 -#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ -#define RCWL_CEPDF 0x00000020 /* CEPDF */ +#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ +#define RCWL_CEPDF 0x00000020 /* CEPDF */ #define RCWL_CEPDF_SHIFT 5 -#define RCWL_CEPMF 0x0000001F /* CEPMF */ +#define RCWL_CEPMF 0x0000001F /* CEPMF */ #define RCWL_CEPMF_SHIFT 0 #if defined (CONFIG_MPC8349) #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) @@ -558,30 +558,30 @@ typedef struct reset83xx { #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) #endif u32 rcwh; /* RCHL Register */ -#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ +#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define RCWH_PCIHOST_SHIFT 31 #if defined (CONFIG_MPC8349) -#define RCWH_PCI64 0x40000000 /* PCI64 */ -#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ -#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ +#define RCWH_PCI64 0x40000000 /* PCI64 */ +#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ +#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ #elif defined (CONFIG_MPC8360) #define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ #define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ #endif -#define RCWH_COREDIS 0x08000000 /* COREDIS */ -#define RCWH_BMS 0x04000000 /* BMS */ -#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ -#define RCWH_SWEN 0x00800000 /* SWEN */ -#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ +#define RCWH_COREDIS 0x08000000 /* COREDIS */ +#define RCWH_BMS 0x04000000 /* BMS */ +#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ +#define RCWH_SWEN 0x00800000 /* SWEN */ +#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ #if defined (CONFIG_MPC8349) -#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ -#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ -#define RCWH_TPR 0x00000100 /* TPR */ +#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ +#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ +#define RCWH_TPR 0x00000100 /* TPR */ #elif defined (CONFIG_MPC8360) #define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ #endif -#define RCWH_TLE 0x00000008 /* TLE */ -#define RCWH_LALE 0x00000004 /* LALE */ +#define RCWH_TLE 0x00000008 /* TLE */ +#define RCWH_LALE 0x00000004 /* LALE */ #if defined (CONFIG_MPC8349) #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ @@ -595,58 +595,58 @@ typedef struct reset83xx { #endif u8 res0[8]; u32 rsr; /* Reset status Register */ -#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 29 -#define RSR_BSF 0x00010000 /* Boot seq. fail */ -#define RSR_BSF_SHIFT 16 -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWSR_SHIFT 13 -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_SWHR_SHIFT 12 -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JHRS_SHIFT 9 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 #define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_JSRS_SHIFT 8 +#define RSR_JSRS_SHIFT 8 #define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_CSHR_SHIFT 4 +#define RSR_CSHR_SHIFT 4 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_SWRS_SHIFT 3 +#define RSR_SWRS_SHIFT 3 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_BMRS_SHIFT 2 -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_SRS_SHIFT 1 -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_HRS_SHIFT 0 +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) - u32 rmr; /* Reset mode Register */ + u32 rmr; /* Reset mode Register */ #define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 +#define RMR_CSRE_SHIFT 0 #define RMR_RES ~(RMR_CSRE) u32 rpr; /* Reset protection Register */ u32 rcr; /* Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ #define RCR_RES ~(RCR_SWHR | RCR_SWSR) u32 rcer; /* Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_CRE 0x00000001 /* software hard reset */ #define RCER_RES ~(RCER_CRE) u8 res1[0xDC]; } reset83xx_t; typedef struct clk83xx { u32 spmr; /* system PLL mode Register */ -#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ -#define SPMR_DDRCM 0x40000000 /* DDRCM */ +#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ +#define SPMR_DDRCM 0x40000000 /* DDRCM */ #if defined (CONFIG_MPC8349) -#define SPMR_SVCOD 0x30000000 /* SVCOD */ +#define SPMR_SVCOD 0x30000000 /* SVCOD */ #endif -#define SPMR_SPMF 0x0F000000 /* SPMF */ -#define SPMR_CKID 0x00800000 /* CKID */ +#define SPMR_SPMF 0x0F000000 /* SPMF */ +#define SPMR_CKID 0x00800000 /* CKID */ #define SPMR_CKID_SHIFT 23 -#define SPMR_COREPLL 0x007F0000 /* COREPLL */ -#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ -#define SPMR_CEPDF 0x00000020 /* CEPDF */ -#define SPMR_CEPMF 0x0000001F /* CEPMF */ +#define SPMR_COREPLL 0x007F0000 /* COREPLL */ +#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ +#define SPMR_CEPDF 0x00000020 /* CEPDF */ +#define SPMR_CEPMF 0x0000001F /* CEPMF */ #if defined (CONFIG_MPC8349) #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ @@ -657,27 +657,27 @@ typedef struct clk83xx { | SPMR_CEPDF | SPMR_CEPMF) #endif u32 occr; /* output clock control Register */ -#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ -#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ -#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ +#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ +#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ +#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ #if defined (CONFIG_MPC8349) -#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ -#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ -#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ -#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ -#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ +#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ +#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ +#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ +#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ +#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ #endif -#define OCCR_PCICD0 0x00800000 /* PCICD0 */ -#define OCCR_PCICD1 0x00400000 /* PCICD1 */ -#define OCCR_PCICD2 0x00200000 /* PCICD2 */ +#define OCCR_PCICD0 0x00800000 /* PCICD0 */ +#define OCCR_PCICD1 0x00400000 /* PCICD1 */ +#define OCCR_PCICD2 0x00200000 /* PCICD2 */ #if defined (CONFIG_MPC8349) -#define OCCR_PCICD3 0x00100000 /* PCICD3 */ -#define OCCR_PCICD4 0x00080000 /* PCICD4 */ -#define OCCR_PCICD5 0x00040000 /* PCICD5 */ -#define OCCR_PCICD6 0x00020000 /* PCICD6 */ -#define OCCR_PCICD7 0x00010000 /* PCICD7 */ -#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ -#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ +#define OCCR_PCICD3 0x00100000 /* PCICD3 */ +#define OCCR_PCICD4 0x00080000 /* PCICD4 */ +#define OCCR_PCICD5 0x00040000 /* PCICD5 */ +#define OCCR_PCICD6 0x00020000 /* PCICD6 */ +#define OCCR_PCICD7 0x00010000 /* PCICD7 */ +#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ +#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ #define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ @@ -724,7 +724,7 @@ typedef struct pmc83xx { #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ #if defined (CONFIG_MPC8360) -#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ +#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) #elif defined (CONFIG_MPC8349) #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) @@ -733,7 +733,7 @@ typedef struct pmc83xx { #define PMCER_PMCI 0x00000001 /* PMC Interrupt */ #define PMCER_RES ~(PMCER_PMCI) u32 pmcmr; /* PMC Mask Register */ -#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ +#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ #define PMCMR_RES ~(PMCMR_PMCIE) u8 res0[0xF4]; } pmc83xx_t; @@ -919,9 +919,9 @@ typedef struct qesba83xx { typedef struct ddr_cs_bnds { u32 csbnds; #define CSBNDS_SA 0x00FF0000 -#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_SA_SHIFT 8 #define CSBNDS_EA 0x000000FF -#define CSBNDS_EA_SHIFT 24 +#define CSBNDS_EA_SHIFT 24 u8 res0[4]; } ddr_cs_bnds_t; @@ -929,8 +929,8 @@ typedef struct ddr83xx { ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ u8 res0[0x60]; u32 cs_config[4]; /**< Chip Select x Configuration */ -#define CSCONFIG_EN 0x80000000 -#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -953,7 +953,7 @@ typedef struct ddr83xx { #define TIMING_CFG1_REFREC 0x0000F000 #define TIMING_CFG1_REFREC_SHIFT 12 #define TIMING_CFG1_WRREC 0x00000700 -#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_WRREC_SHIFT 8 #define TIMING_CFG1_ACTTOACT 0x00000070 #define TIMING_CFG1_ACTTOACT_SHIFT 4 #define TIMING_CFG1_WRTORD 0x00000007 @@ -962,25 +962,25 @@ typedef struct ddr83xx { #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 -#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_CPO 0x0F000000 +#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_ACSM 0x00080000 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 -#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 -#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ u32 sdram_cfg; /**< SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_SREN 0x40000000 #define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_RD_EN 0x10000000 #define SDRAM_CFG_SDRAM_TYPE 0x03000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 u8 res2[4]; @@ -988,33 +988,33 @@ typedef struct ddr83xx { #define SDRAM_MODE_ESD 0xFFFF0000 #define SDRAM_MODE_ESD_SHIFT 16 #define SDRAM_MODE_SD 0x0000FFFF -#define SDRAM_MODE_SD_SHIFT 0 -#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ -#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ -#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ -#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ -#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ -#define DDR_MODE_WEAK 0x0002 /* weak drivers */ -#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ -#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ -#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ -#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ -#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ -#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ -#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ -#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ -#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ -#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ -#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ -#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ -#define DDR_MODE_MODEREG 0x0000 /* select mode register */ +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ u8 res3[8]; u32 sdram_interval; /**< SDRAM Interval Configuration */ #define SDRAM_INTERVAL_REFINT 0x3FFF0000 #define SDRAM_INTERVAL_REFINT_SHIFT 16 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF -#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 u8 res9[8]; u32 sdram_clk_cntl; #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 @@ -1024,8 +1024,8 @@ typedef struct ddr83xx { #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 u8 res4[0xCCC]; - u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ + u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ @@ -1039,7 +1039,7 @@ typedef struct ddr83xx { #define CAPTURE_ECC_ECE_SHIFT 0 u8 res6[0x14]; u32 err_detect; /**< Memory Error Detect */ -#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ @@ -1053,10 +1053,10 @@ typedef struct ddr83xx { #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) - u32 capture_attributes; /**< Memory Error Attributes Capture */ -#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ + u32 capture_attributes; /**< Memory Error Attributes Capture */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ #define ECC_CAPT_ATTR_BNUM_SHIFT 28 -#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 @@ -1084,7 +1084,7 @@ typedef struct ddr83xx { u32 capture_address; /**< Memory Error Address Capture */ u32 capture_ext_address;/**< Memory Error Extended Address Capture */ u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ -#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ #define ECC_ERROR_MAN_SBET_SHIFT 16 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 @@ -1119,8 +1119,8 @@ typedef struct duart83xx { * Local Bus Controller Registers */ typedef struct lbus_bank { - u32 br; /**< Base Register */ - u32 or; /**< Base Register */ + u32 br; /**< Base Register */ + u32 or; /**< Base Register */ } lbus_bank_t; typedef struct lbus83xx { @@ -1148,24 +1148,24 @@ typedef struct lbus83xx { u8 res6[0xC]; u32 lbcr; /**< Configuration Register */ #define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 +#define LBCR_LDIS_SHIFT 31 #define LBCR_BCTLC 0x00C00000 #define LBCR_BCTLC_SHIFT 22 #define LBCR_LPBSE 0x00020000 #define LBCR_LPBSE_SHIFT 17 #define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 +#define LBCR_EPAR_SHIFT 16 #define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 +#define LBCR_BMT_SHIFT 8 u32 lcrr; /**< Clock Ratio Register */ #define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 +#define LCRR_DBYP_SHIFT 31 #define LCRR_BUFCMDC 0x30000000 #define LCRR_BUFCMDC_SHIFT 28 #define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_SHIFT 24 #define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_SHIFT 16 #define LCRR_CLKDIV 0x0000000F #define LCRR_CLKDIV_SHIFT 0 @@ -1274,7 +1274,7 @@ typedef struct dma83xx { #define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ /* DMASRn bits */ -#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ +#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ #define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ /* @@ -1314,33 +1314,33 @@ typedef struct pci_outbound_window { typedef struct ios83xx { pot83xx_t pot[6]; #define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF +#define POBAR_BA_MASK 0x000fffff +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF u8 res0[0x60]; u32 pmcr; u8 res1[4]; @@ -1355,63 +1355,63 @@ typedef struct pcictrl83xx { u32 esr; #define ESR_MERR 0x80000000 #define ESR_APAR 0x00000400 -#define ESR_PCISERR 0x00000200 -#define ESR_MPERR 0x00000100 -#define ESR_TPERR 0x00000080 -#define ESR_NORSP 0x00000040 -#define ESR_TABT 0x00000020 +#define ESR_PCISERR 0x00000200 +#define ESR_MPERR 0x00000100 +#define ESR_TPERR 0x00000080 +#define ESR_NORSP 0x00000040 +#define ESR_TABT 0x00000020 u32 ecdr; #define ECDR_APAR 0x00000400 -#define ECDR_PCISERR 0x00000200 -#define ECDR_MPERR 0x00000100 -#define ECDR_TPERR 0x00000080 -#define ECDR_NORSP 0x00000040 -#define ECDR_TABT 0x00000020 +#define ECDR_PCISERR 0x00000200 +#define ECDR_MPERR 0x00000100 +#define ECDR_TPERR 0x00000080 +#define ECDR_NORSP 0x00000040 +#define ECDR_TABT 0x00000020 u32 eer; #define EER_APAR 0x00000400 -#define EER_PCISERR 0x00000200 -#define EER_MPERR 0x00000100 -#define EER_TPERR 0x00000080 -#define EER_NORSP 0x00000040 -#define EER_TABT 0x00000020 +#define EER_PCISERR 0x00000200 +#define EER_MPERR 0x00000100 +#define EER_TPERR 0x00000080 +#define EER_NORSP 0x00000040 +#define EER_TABT 0x00000020 u32 eatcr; -#define EATCR_ERRTYPR_MASK 0x70000000 -#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ -#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ -#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ -#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ -#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ -#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ -#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ -#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ +#define EATCR_ERRTYPR_MASK 0x70000000 +#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ +#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ +#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ +#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ +#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ +#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ +#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ +#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ #define EATCR_BN_MASK 0x0f000000 /* beat number */ -#define EATCR_BN_1st 0x00000000 -#define EATCR_BN_2ed 0x01000000 -#define EATCR_BN_3rd 0x02000000 -#define EATCR_BN_4th 0x03000000 -#define EATCR_BN_5th 0x0400000 -#define EATCR_BN_6th 0x05000000 -#define EATCR_BN_7th 0x06000000 -#define EATCR_BN_8th 0x07000000 -#define EATCR_BN_9th 0x08000000 +#define EATCR_BN_1st 0x00000000 +#define EATCR_BN_2ed 0x01000000 +#define EATCR_BN_3rd 0x02000000 +#define EATCR_BN_4th 0x03000000 +#define EATCR_BN_5th 0x0400000 +#define EATCR_BN_6th 0x05000000 +#define EATCR_BN_7th 0x06000000 +#define EATCR_BN_8th 0x07000000 +#define EATCR_BN_9th 0x08000000 #define EATCR_TS_MASK 0x00300000 /* transaction size */ -#define EATCR_TS_4 0x00000000 -#define EATCR_TS_1 0x00100000 -#define EATCR_TS_2 0x00200000 -#define EATCR_TS_3 0x00300000 -#define EATCR_ES_MASK 0x000f0000 /* error source */ -#define EATCR_ES_EM 0x00000000 /* external master */ -#define EATCR_ES_DMA 0x00050000 -#define EATCR_CMD_MASK 0x0000f000 +#define EATCR_TS_4 0x00000000 +#define EATCR_TS_1 0x00100000 +#define EATCR_TS_2 0x00200000 +#define EATCR_TS_3 0x00300000 +#define EATCR_ES_MASK 0x000f0000 /* error source */ +#define EATCR_ES_EM 0x00000000 /* external master */ +#define EATCR_ES_DMA 0x00050000 +#define EATCR_CMD_MASK 0x0000f000 #if defined (CONFIG_MPC8349) -#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ +#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ #endif -#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ +#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ #if defined (CONFIG_MPC8349) -#define EATCR_HPB 0x00000004 /* high parity bit */ +#define EATCR_HPB 0x00000004 /* high parity bit */ #endif -#define EATCR_PB 0x00000002 /* parity bit */ -#define EATCR_VI 0x00000001 /* error information valid */ +#define EATCR_PB 0x00000002 /* parity bit */ +#define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; #if defined (CONFIG_MPC8349) @@ -1448,33 +1448,33 @@ typedef struct pcictrl83xx { #define PIEBAR_EBA_MASK 0x000fffff #define PIWAR_EN 0x80000000 #define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 #define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 #define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; #if defined (CONFIG_MPC8349) @@ -1638,7 +1638,7 @@ typedef struct spi83xx { u8 spim; /* SPI mask register */ u8 res4[0x1]; u8 res5[0x1]; - u8 spcom; /* SPI command register */ + u8 spcom; /* SPI command register */ u8 res6[0x2]; u32 spitd; /* SPI transmit data register (cpu mode) */ u32 spird; /* SPI receive data register (cpu mode) */ @@ -1785,20 +1785,20 @@ typedef struct uslow { typedef struct ufast { u32 gumr; /* UCCx general mode register */ - u32 upsmr; /* UCCx protocol-specific mode register */ + u32 upsmr; /* UCCx protocol-specific mode register */ u16 utodr; /* UCCx transmit on demand register */ u8 res0[0x2]; u16 udsr; /* UCCx data synchronization register */ u8 res1[0x2]; u32 ucce; /* UCCx event register */ - u32 uccm; /* UCCx mask register. */ + u32 uccm; /* UCCx mask register. */ u8 uccs; /* UCCx status register */ u8 res2[0x7]; u32 urfb; /* UCC receive FIFO base */ u16 urfs; /* UCC receive FIFO size */ u8 res3[0x2]; - u16 urfet; /* UCC receive FIFO emergency threshold */ - u16 urfset; /* UCC receive FIFO special emergency threshold */ + u16 urfet; /* UCC receive FIFO emergency threshold */ + u16 urfset; /* UCC receive FIFO special emergency threshold */ u32 utfb; /* UCC transmit FIFO base */ u16 utfs; /* UCC transmit FIFO size */ u8 res4[0x2]; @@ -1816,7 +1816,7 @@ typedef struct ufast { u32 maccfg2; /* Mac configuration register #2 */ u16 ipgifg; /* Interframe gap register */ u8 res10[0x2]; - u32 hafdup; /* Half-duplex register */ + u32 hafdup; /* Half-duplex register */ u8 res11[0xC]; u32 emtr; /* Ethernet MAC test register */ u32 miimcfg; /* MII mgmt configuration register */ @@ -2046,7 +2046,7 @@ typedef struct immap { cp83xx_t cp; /* Communications Processor */ qmx83xx_t qmx; /* QE Multiplexer */ qet83xx_t qet; /* QE Timers */ - spi83xx_t spi[0x2]; /* spi */ + spi83xx_t spi[0x2]; /* spi */ mcc83xx_t mcc; /* mcc */ brg83xx_t brg; /* brg */ usb83xx_t usb; /* USB */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 8dc96352a..cbdbb2921 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -38,17 +38,17 @@ 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) I2C address list: - Align. Board - Bus Addr Part No. Description Length Location + Align. Board + Bus Addr Part No. Description Length Location ---------------------------------------------------------------- - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 + I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - I2C1 0x20 PCF8574 I2C Expander 0 U8 - I2C1 0x21 PCF8574 I2C Expander 0 U10 - I2C1 0x38 PCF8574A I2C Expander 0 U8 - I2C1 0x39 PCF8574A I2C Expander 0 U10 - I2C1 0x51 (DDR) DDR EEPROM 1 U1 - I2C1 0x68 DS1339 RTC 1 U68 + I2C1 0x20 PCF8574 I2C Expander 0 U8 + I2C1 0x21 PCF8574 I2C Expander 0 U10 + I2C1 0x38 PCF8574A I2C Expander 0 U8 + I2C1 0x39 PCF8574A I2C Expander 0 U10 + I2C1 0x51 (DDR) DDR EEPROM 1 U1 + I2C1 0x68 DS1339 RTC 1 U68 Note that a given board has *either* a pair of 8574s or a pair of 8574As. */ @@ -80,15 +80,15 @@ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ @@ -96,7 +96,7 @@ #define CFG_I2C_SLAVE 0x7F /* Don't probe these addresses: */ -#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ +#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ {1, CFG_I2C_8574_ADDR2}, \ {1, CFG_I2C_8574A_ADDR1}, \ {1, CFG_I2C_8574A_ADDR2}} @@ -131,9 +131,9 @@ #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00003000 /* memtest region */ +#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ /* * DDR Setup @@ -157,7 +157,7 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING +#undef CONFIG_DDR_2T_TIMING #define CFG_83XX_DDR_USES_CS0 #ifndef CONFIG_SPD_EEPROM @@ -214,13 +214,13 @@ #ifdef CONFIG_COMPACT_FLASH -#define CFG_CF_BASE 0xF0000000 +#define CFG_CF_BASE 0xF0000000 -#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) +#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) #define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ +#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ #undef CONFIG_IDE_RESET #undef CONFIG_IDE_PREINIT @@ -241,27 +241,27 @@ #define CONFIG_DOS_PARTITION -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* * Local Bus LCRR and LBCR regs @@ -287,7 +287,7 @@ * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ @@ -316,9 +316,9 @@ #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) @@ -329,16 +329,16 @@ #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ | CFG_LBC_LSDMR_BSMA1516 \ | CFG_LBC_LSDMR_RFCR8 \ | CFG_LBC_LSDMR_PRETOACT6 \ @@ -381,7 +381,7 @@ /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -430,7 +430,7 @@ #define _IO_BASE 0x00000000 /* points to PCI I/O space */ #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #ifdef CONFIG_RTL8139 /* This macro is used by RTL8139 but not defined in PPC architecture */ @@ -462,14 +462,14 @@ #ifdef CONFIG_MPC83XX_TSEC1 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CFG_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ +#define CFG_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 #endif #ifdef CONFIG_MPC83XX_TSEC2 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 @@ -486,7 +486,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -518,13 +518,13 @@ #define CONFIG_COMMANDS_I2C 0 #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CONFIG_COMMANDS_CF | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CONFIG_COMMANDS_I2C | \ - CONFIG_COMMANDS_PCI | \ - CFG_CMD_SDRAM | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CONFIG_COMMANDS_I2C | \ + CONFIG_COMMANDS_PCI | \ + CFG_CMD_SDRAM | \ CFG_CMD_DATE | \ CFG_CMD_CACHE | \ CFG_CMD_IRQ) @@ -534,13 +534,13 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 +#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 #endif /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ @@ -550,7 +550,7 @@ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -569,7 +569,7 @@ #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ @@ -623,7 +623,7 @@ #define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 HID2_HBE +#define CFG_HID2 HID2_HBE /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -741,7 +741,7 @@ #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_BOOTCOMMAND @@ -761,7 +761,7 @@ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ @@ -776,25 +776,25 @@ "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtaddr=400000\0" \ + "fdtfile=mpc8349emitx.dtb\0" \ + "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 2ff5f4898..8ad6551de 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -10,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -120,7 +120,7 @@ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) #define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ -#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ +#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ #define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ #define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ #endif @@ -141,7 +141,7 @@ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ @@ -217,7 +217,7 @@ * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * * CFG_LBC_SDRAM_BASE should be masked and OR'ed into @@ -233,10 +233,10 @@ * 64MB mask for AM, OR2[0:7] = 1111 1100 * XAM, OR2[17:18] = 11 * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 + * 13 rows OR2[23-25] = 100 * EAD set for extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ @@ -248,13 +248,13 @@ /* * LSDMR masks */ -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) #define CFG_LBC_LSDMR_COMMON 0x0063b723 @@ -311,7 +311,7 @@ /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -335,7 +335,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 +#define CFG_I2C2_OFFSET 0x3100 /* * Config on-board RTC @@ -369,7 +369,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ @@ -393,7 +393,7 @@ #define CFG_UEC1_TX_CLK QE_CLK9 #define CFG_UEC1_ETH_TYPE GIGA_ETH #define CFG_UEC1_PHY_ADDR 0 -#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -404,7 +404,7 @@ #define CFG_UEC2_TX_CLK QE_CLK4 #define CFG_UEC2_ETH_TYPE GIGA_ETH #define CFG_UEC2_PHY_ADDR 1 -#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII #endif /* @@ -414,7 +414,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ @@ -428,16 +428,16 @@ #if defined(CFG_RAMBOOT) #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_ASKENV \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_LOADS)) #else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_ASKENV \ | CFG_CMD_I2C) \ @@ -447,13 +447,13 @@ #endif #else #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ | CFG_CMD_ASKENV \ | CFG_CMD_I2C) #else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_ASKENV \ | CFG_CMD_I2C ) @@ -593,39 +593,39 @@ #if defined(CONFIG_UEC_ETH) #define CONFIG_ETHADDR 00:04:9f:ef:01:01 #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 +#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 #endif -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ "fdtaddr=400000\0" \ "fdtfile=mpc8349emds.dtb\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" diff --git a/include/ioports.h b/include/ioports.h index 91ca6fb48..cfba667ca 100644 --- a/include/ioports.h +++ b/include/ioports.h @@ -63,4 +63,3 @@ typedef struct { } qe_iop_conf_t; #define QE_IOP_TAB_END (-1) - diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 1866dc5cf..a11d3c0fd 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -521,17 +521,17 @@ void board_init_f (ulong bootflag) bd->bi_pevfreq = gd->pev_clk; bd->bi_flbfreq = gd->flb_clk; - /* store bootparam to sram (backward compatible), here? */ - { - u32 *sram = (u32 *)CFG_SRAM_BASE; - *sram++ = gd->ram_size; - *sram++ = gd->bus_clk; - *sram++ = gd->inp_clk; - *sram++ = gd->cpu_clk; - *sram++ = gd->vco_clk; - *sram++ = gd->flb_clk; - *sram++ = 0xb8c3ba11; /* boot signature */ - } + /* store bootparam to sram (backward compatible), here? */ + { + u32 *sram = (u32 *)CFG_SRAM_BASE; + *sram++ = gd->ram_size; + *sram++ = gd->bus_clk; + *sram++ = gd->inp_clk; + *sram++ = gd->cpu_clk; + *sram++ = gd->vco_clk; + *sram++ = gd->flb_clk; + *sram++ = 0xb8c3ba11; /* boot signature */ + } #endif bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ |