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authorYuri Tikhonov <yur@pollux.denx.de>2008-02-04 17:09:55 +0100
committerWolfgang Denk <wd@denx.de>2008-03-18 22:24:48 +0100
commitf694e32f93565ec1fa8d0226c584d6b89e931ed9 (patch)
tree0aea8d1de43dba00f85ef18f2389c14e1d63e9f9 /post/board
parentb428f6a8c65c5303e5f96db8d24f2f699d94a98c (diff)
downloadu-boot-linaro-stable-f694e32f93565ec1fa8d0226c584d6b89e931ed9.tar.gz
Some fixes to dspic, fpga, and gdc post tests for lwmon5. Disable external watch-dog for now.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Diffstat (limited to 'post/board')
-rw-r--r--post/board/lwmon5/dspic.c2
-rw-r--r--post/board/lwmon5/fpga.c4
-rw-r--r--post/board/lwmon5/gdc.c2
3 files changed, 6 insertions, 2 deletions
diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c
index 897a852e4..65b96bcc2 100644
--- a/post/board/lwmon5/dspic.c
+++ b/post/board/lwmon5/dspic.c
@@ -94,9 +94,9 @@ int dspic_post_test(int flags)
}
data = dspic_read(DSPIC_SYS_ERROR_REG);
- if (data != 0) ret = 1;
if (data == -1) {
post_log("dsPIC : failed read system error\n");
+ ret = 1;
} else {
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
}
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index 7a36c168c..dca7a30a9 100644
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define FPGA_VERSION_REG 0xC4000040
#define FPGA_RAM_START 0xC4200000
#define FPGA_RAM_END 0xC4203FFF
+#define FPGA_STAT 0xC400000C
#define FPGA_PWM_CTRL_REG 0xC4000020
#define FPGA_PWM_TV_REG 0xC4000024
@@ -93,6 +94,9 @@ int fpga_post_test(int flags)
post_log("FPGA : version %u.%u\n",
(version >> 8) & 0xFF, version & 0xFF);
+ /* Enable write to FPGA RAM */
+ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
+
read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
post_log("FPGA RAM size: %d bytes\n", read_value);
diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c
index 42da37019..73d5935ce 100644
--- a/post/board/lwmon5/gdc.c
+++ b/post/board/lwmon5/gdc.c
@@ -35,7 +35,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#define GDC_SCRATCH_REG 0xC1FF8044
+#define GDC_SCRATCH_REG 0xC1FF8008
#define GDC_VERSION_REG 0xC1FF8084
#define GDC_RAM_START 0xC0000000
#define GDC_RAM_END 0xC2000000