path: root/nand_spl
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authorStefan Roese <sr@denx.de>2007-03-06 07:47:04 +0100
committerStefan Roese <sr@denx.de>2007-03-06 07:47:04 +0100
commit07b7b0037aac5102939917d7cbe561b5c0d5aa44 (patch)
treef9dee6436517274555fea9d0bc551f221a9d0640 /nand_spl
parentfdd1d6dcc97c595bd9d598ed3b22a7038781272c (diff)
[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'nand_spl')
1 files changed, 5 insertions, 1 deletions
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
index b42da8cf6..510999db0 100644
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
-COBJS = nand_boot.o ndfc.o sdram.o
+COBJS = nand_boot.o ndfc.o sdram.o speed.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -69,6 +69,10 @@ $(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ @rm -f $(obj)speed.c
+ ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
# from board directory
@rm -f $(obj)init.S