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authorSimon Glass <sjg@chromium.org>2012-11-03 11:41:42 +0000
committerSimon Glass <sjg@chromium.org>2012-12-06 14:30:44 -0800
commitcbca883c46146e9b3128fcb51ab750089c47c241 (patch)
tree4716cae7db751753c16985df63cddd2bd8945bfd /include
parent058d59b08ddcc6fd3b59210a4605721cc96ead44 (diff)
downloadu-boot-linaro-stable-cbca883c46146e9b3128fcb51ab750089c47c241.tar.gz
x86: coreboot: Enable video display
Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r--include/configs/coreboot.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 94b691763..46b8d78fb 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -78,6 +78,7 @@
*/
#define CONFIG_RTC_MC146818
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
/*-----------------------------------------------------------------------
* Serial Configuration
@@ -136,8 +137,13 @@
/*-----------------------------------------------------------------------
* Video Configuration
*/
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_COREBOOT
+#define CONFIG_VIDEO_SW_CURSOR
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_I8042_KBD
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* x86 GPIOs are accessed through a PCI device */
#define CONFIG_INTEL_ICH6_GPIO