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authorwdenk <wdenk>2001-04-28 17:59:11 +0000
committerwdenk <wdenk>2001-04-28 17:59:11 +0000
commit4a5b6a356a79123d3fcd780139629213afcedca8 (patch)
treea54c1cec31c73462ba2c04fac3318a0990dd21b1 /include/mpc8xx_irq.h
parentb631bb9cad6b5553846f508fbfa5ba6362fb0677 (diff)
downloadu-boot-linaro-stable-4a5b6a356a79123d3fcd780139629213afcedca8.tar.gz
Initial revision
Diffstat (limited to 'include/mpc8xx_irq.h')
-rw-r--r--include/mpc8xx_irq.h59
1 files changed, 59 insertions, 0 deletions
diff --git a/include/mpc8xx_irq.h b/include/mpc8xx_irq.h
new file mode 100644
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+++ b/include/mpc8xx_irq.h
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+#ifndef _MPC8XX_IRQ_H
+#define _MPC8XX_IRQ_H
+
+/* The MPC8xx cores have 16 possible interrupts. There are eight
+ * possible level sensitive interrupts assigned and generated internally
+ * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
+ * There are eight external interrupts (IRQs) that can be configured
+ * as either level or edge sensitive.
+ *
+ * On some implementations, there is also the possibility of an 8259
+ * through the PCI and PCI-ISA bridges.
+ *
+ * We don't support the 8259 (yet).
+ */
+#define NR_SIU_INTS 16
+#define NR_8259_INTS 0
+
+#define NR_IRQS (NR_SIU_INTS + NR_8259_INTS)
+
+/* These values must be zero-based and map 1:1 with the SIU configuration.
+ * They are used throughout the 8xx I/O subsystem to generate
+ * interrupt masks, flags, and other control patterns. This is why the
+ * current kernel assumption of the 8259 as the base controller is such
+ * a pain in the butt.
+ */
+#define SIU_IRQ0 (0) /* Highest priority */
+#define SIU_LEVEL0 (1)
+#define SIU_IRQ1 (2)
+#define SIU_LEVEL1 (3)
+#define SIU_IRQ2 (4)
+#define SIU_LEVEL2 (5)
+#define SIU_IRQ3 (6)
+#define SIU_LEVEL3 (7)
+#define SIU_IRQ4 (8)
+#define SIU_LEVEL4 (9)
+#define SIU_IRQ5 (10)
+#define SIU_LEVEL5 (11)
+#define SIU_IRQ6 (12)
+#define SIU_LEVEL6 (13)
+#define SIU_IRQ7 (14)
+#define SIU_LEVEL7 (15)
+
+/* The internal interrupts we can configure as we see fit.
+ * My personal preference is CPM at level 2, which puts it above the
+ * MBX PCI/ISA/IDE interrupts.
+ */
+
+#ifdef CFG_CPM_INTERRUPT
+# define CPM_INTERRUPT CFG_CPM_INTERRUPT
+#else
+# define CPM_INTERRUPT SIU_LEVEL2
+#endif
+
+/* Some internal interrupt registers use an 8-bit mask for the interrupt
+ * level instead of a number.
+ */
+#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
+
+#endif /* _MPC8XX_IRQ_H */