diff options
| author | wdenk <wdenk> | 2003-10-15 23:53:47 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-10-15 23:53:47 +0000 |
| commit | 42d1f0394bef0624fc9664714d54bb137931d6a6 (patch) | |
| tree | 892a4130507484d25faf9a72e019cf88cfb3e3d9 /include/mpc85xx.h | |
| parent | 2d5b561e2bfdee8552a99b2cf93016cce2a74895 (diff) | |
* Patches by Xianghua Xiao, 15 Oct 2003:LABEL_2003_10_16_0200
- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Minor code cleanup
Diffstat (limited to 'include/mpc85xx.h')
| -rw-r--r-- | include/mpc85xx.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/mpc85xx.h b/include/mpc85xx.h new file mode 100644 index 000000000..a4f5c619d --- /dev/null +++ b/include/mpc85xx.h @@ -0,0 +1,32 @@ +/* + * Copyright(c) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + */ + +#ifndef __MPC85xx_H__ +#define __MPC85xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ + +#if defined(CONFIG_E500) +#include <e500.h> +#endif + +#if defined(CONFIG_DDR_ECC) +void dma_init(void); +uint dma_check(void); +int dma_xfer(void *dest, uint count, void *src); +#endif +/*----------------------------------------------------------------------- + * SCCR - System Clock Control Register 9-8 + */ +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ +#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ +#define SCCR_DFBRG_SHIFT 0 + +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ +#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ + +#endif /* __MPC85xx_H__ */ |