path: root/doc
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authorYork Sun <yorksun@freescale.com>2010-09-28 15:20:33 -0700
committerKumar Gala <galak@kernel.crashing.org>2010-10-20 02:28:00 -0500
commitebbe11dd365b16573e25b1b361287f9539daa33c (patch)
tree17981124c3cbdb2ae4dd8b2ad3bd0288a31655bc /doc
parentc02ce6e5a1bc65831c8f638268defa9c6ae70bf1 (diff)
Add memory test feature for mpc85xx POST.
The memory test is performed after DDR initialization when U-boot stills runs in flash and cache. On recent mpc85xx platforms, the total memory can be more than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a sliding TLB window. After the testing, DDR is remapped with up to 2GB memory from the lowest address as normal. If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for further debugging. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'doc')
1 files changed, 14 insertions, 0 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index e108a0d50..1657ef617 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -78,6 +78,20 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig.
Syntax is:
+Memory testing options for mpc85xx
+1. Memory test can be done once U-boot prompt comes up using mtest, or
+2. Memory test can be done with Power-On-Self-Test function, activated at
+ compile time.
+ In order to enable the POST memory test, CONFIG_POST needs to be
+ defined in board configuraiton header file. By default, POST memory test
+ performs a fast test. A slow test can be enabled by changing the flag at
+ compiling time. To test memory bigger than 2GB, 36BIT support is needed.
+ Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
+ window to physical address so that all physical memory can be tested.
Combination of hwconfig
Hwconfig can be combined with multiple parameters, for example, on a supported